JPH05267527A - Structure of lead frame for semiconductor device - Google Patents

Structure of lead frame for semiconductor device

Info

Publication number
JPH05267527A
JPH05267527A JP4092066A JP9206692A JPH05267527A JP H05267527 A JPH05267527 A JP H05267527A JP 4092066 A JP4092066 A JP 4092066A JP 9206692 A JP9206692 A JP 9206692A JP H05267527 A JPH05267527 A JP H05267527A
Authority
JP
Japan
Prior art keywords
lead
frame
semiconductor device
island
tie bar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4092066A
Other languages
Japanese (ja)
Inventor
Koji Ishikawa
耕二 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP4092066A priority Critical patent/JPH05267527A/en
Publication of JPH05267527A publication Critical patent/JPH05267527A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve mounting strength at the time of surface mounting by forming solder-plated portion at the nose of a lead. CONSTITUTION:A solder-plated portion is formed at a nose 4a of a lead 4 by supporting the nose 4a of the lead 4 with the use of a double tie-bar method of a lead-fixing tie bar 2 and a resin-sealing tie bar 3. By this double tie-bar method, the solder-plated portion is formed at the nose of the lead, thereby the strength at the time of mounting is improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体装置を製造する
のに用いられるリードフレーム構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame structure used for manufacturing a semiconductor device.

【０００２】[0002]

【従来の技術】従来、この種の半導体装置に用いられる
リードフレームは図３及び図４に示すように、リード４
の変形防止又は樹脂封止の際、樹脂が全リード４に漏れ
ないようにするため、樹脂封止タイバー３が枠１に取付
けられていた。2. Description of the Related Art Conventionally, as shown in FIGS. 3 and 4, a lead frame used in a semiconductor device of this type has a lead 4
In order to prevent the resin from leaking to all the leads 4 at the time of deformation prevention or resin sealing, the resin sealing tie bar 3 is attached to the frame 1.

【０００３】[0003]

【発明が解決しようとする課題】上述した従来の表面実
装用半導体装置を製造するのに用いられるリードフレー
ムは、リードタイバー部及びリードフレーム先端枠はリ
ード変形防止又は樹脂封止の際、樹脂が全リードに漏れ
ないようにするためにあるが、図４に示すように、ベー
スの表面に電解半田メッキ５を形成した後にリードフレ
ーム先端を切り落した時にリード４の先端４ａの下地が
露出し、現在の実装ではリード４の先端４ａに半田６を
付けて基板７に実装することから実装不良及び実装強度
不良等の問題点があった。In the lead frame used for manufacturing the above-described conventional surface mounting semiconductor device, the lead tie bar portion and the lead frame front end frame are made of resin when the lead deformation prevention or resin sealing is performed. This is to prevent leakage to all the leads, but as shown in FIG. 4, when the tip of the lead frame is cut off after the electrolytic solder plating 5 is formed on the surface of the base, the base of the tip 4a of the lead 4 is exposed, In the current mounting, since the solder 6 is attached to the tips 4a of the leads 4 and mounted on the substrate 7, there are problems such as mounting failure and mounting strength failure.

【０００４】本発明の目的は、実装時の実装強度を向上
させる半導体装置用リードフレームの構造を提供するこ
とにある。An object of the present invention is to provide a structure of a lead frame for a semiconductor device which improves mounting strength during mounting.

【０００５】[0005]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体装置用リードフレームの構造
は、少なくともアイランドと、リードと、リード固定タ
イバーとを枠に組込んでなる半導体装置用リードフレー
ムの構造であって、アイランドは、ＩＣチップが搭載さ
れるものであり、リードは、前記アイランドの周辺部に
配置され、アイランド上のＩＣチップと電気的に接続さ
れる信号入出力用端子をなすものであり、リード固定タ
イバーは、前記枠に取付けられ、前記リードの先端を前
記枠から分離した状態で該リードを支持するものであ
る。In order to achieve the above object, the structure of a lead frame for a semiconductor device according to the present invention has a structure for a semiconductor device in which at least an island, a lead and a lead fixing tie bar are incorporated in a frame. In the lead frame structure, an IC chip is mounted on the island, and leads are arranged around the island and electrically connected to the IC chip on the island. The lead fixing tie bar is attached to the frame and supports the lead in a state where the tip of the lead is separated from the frame.

【０００６】[0006]

【作用】リードの先端をリードフレームの枠から分離し
た状態で支持し、メッキ工程においてリードの先端にメ
ッキを施すようにする。The tip of the lead is supported in a state of being separated from the frame of the lead frame, and the tip of the lead is plated in the plating process.

【０００７】[0007]

【実施例】以下、本発明の一実施例を図により説明す
る。図１は、本発明の一実施例を示す平面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing an embodiment of the present invention.

【０００８】図１において、本実施例に係るリードフレ
ームの構造は、アイランド１ａと、リード４と、樹脂封
止タイバー３と、リード固定タイバー２とを井桁状の枠
１に組込んだものである。In FIG. 1, the structure of the lead frame according to the present embodiment is one in which an island 1a, a lead 4, a resin-sealed tie bar 3, and a lead fixing tie bar 2 are assembled in a double-framed frame 1. is there.

【０００９】アイランド１ａは、ＩＣチップが搭載され
るものであり、枠１のほぼ中央部に支持されている。An IC chip is mounted on the island 1a, and is supported by the frame 1 at a substantially central portion thereof.

【００１０】リード４は、アイランド１ａの周辺部に配
置され、アイランド１ａ上のＩＣチップと電気的に接続
される信号入出力用端子をなすものである。The leads 4 are arranged around the island 1a and serve as signal input / output terminals electrically connected to the IC chip on the island 1a.

【００１１】樹脂封止タイバー３は、ＩＣチップを樹脂
封止８する際に樹脂がリードを伝って漏れるのを阻止す
るものである。The resin sealing tie bar 3 prevents the resin from leaking along the leads when the IC chip is sealed with the resin 8.

【００１２】リード固定タイバー２は、リード４の先端
４ａが枠１から分離した状態で該リード４を支持するも
のである。The lead fixing tie bar 2 supports the lead 4 with the tip 4a of the lead 4 separated from the frame 1.

【００１３】実施例において、リード４の先端４ａは枠
１から分離して露出しているため、電解半田メッキ時に
リード４の先端４ａにもメッキが形成されることとな
る。In the embodiment, since the tip 4a of the lead 4 is separated and exposed from the frame 1, the tip 4a of the lead 4 is also plated during electrolytic solder plating.

【００１４】したがって、図２に示すようにリード４の
表面及び先端４ａに渡って半田メッキ５が形成されるた
め、リード４の先端４ａと半田６とのなじみが向上さ
れ、基板７との間での実装強度を増すこととなる。Therefore, as shown in FIG. 2, since the solder plating 5 is formed over the surface of the lead 4 and the tip 4a, the familiarity between the tip 4a of the lead 4 and the solder 6 is improved and the space between the lead 7 and the substrate 7 is improved. Will increase the mounting strength.

【００１５】[0015]

【発明の効果】以上説明したように本発明は、半導体装
置の製造に用いられるリードフレームのリード先端を露
出した状態とすることにより、リード先端にメッキが形
成され、実装不良，強度不足等を低減させることができ
るという効果を有する。As described above, according to the present invention, by exposing the lead tips of the lead frame used for manufacturing the semiconductor device, plating is formed on the lead tips, which may cause mounting defects, insufficient strength, and the like. It has an effect that it can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例を示す正面図である。FIG. 1 is a front view showing an embodiment of the present invention.

【図２】本発明の実装図である。FIG. 2 is a mounting diagram of the present invention.

【図３】従来のリードフレームを示す正面図である。FIG. 3 is a front view showing a conventional lead frame.

【図４】従来例の実装図である。FIG. 4 is a mounting diagram of a conventional example.

【符号の説明】[Explanation of symbols]

１ 枠 ２ リード固定タイバー ３ 樹脂封止タイバー ４ リード ４ａ リードの先端 ５ 半田メッキ ６ 半田 ７ 基板 1 Frame 2 Lead Fixing Tie Bar 3 Resin Sealing Tie Bar 4 Lead 4a Lead Tip 5 Solder Plating 6 Solder 7 Board

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 少なくともアイランドと、リードと、リ
ード固定タイバーとを枠に組込んでなる半導体装置用リ
ードフレームの構造であって、 アイランドは、ＩＣチップが搭載されるものであり、 リードは、前記アイランドの周辺部に配置され、アイラ
ンド上のＩＣチップと電気的に接続される信号入出力用
端子をなすものであり、 リード固定タイバーは、前記枠に取付けられ、前記リー
ドの先端を前記枠から分離した状態で該リードを支持す
るものであることを特徴とする半導体装置用リードフレ
ームの構造。1. A structure of a lead frame for a semiconductor device, which comprises at least an island, a lead, and a lead fixing tie bar in a frame, wherein the island has an IC chip mounted thereon, and the lead has a A lead input / output terminal is arranged on the periphery of the island and electrically connected to an IC chip on the island. The lead fixing tie bar is attached to the frame, and the tip of the lead is attached to the frame. A structure of a lead frame for a semiconductor device, which supports the lead in a state of being separated from the lead frame.
JP4092066A 1992-03-18 1992-03-18 Structure of lead frame for semiconductor device Pending JPH05267527A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4092066A JPH05267527A (en) 1992-03-18 1992-03-18 Structure of lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4092066A JPH05267527A (en) 1992-03-18 1992-03-18 Structure of lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPH05267527A true JPH05267527A (en) 1993-10-15

Family

ID=14044104

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4092066A Pending JPH05267527A (en) 1992-03-18 1992-03-18 Structure of lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPH05267527A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004303715A (en) * 2003-03-20 2004-10-28 Matsushita Electric Ind Co Ltd Battery

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004303715A (en) * 2003-03-20 2004-10-28 Matsushita Electric Ind Co Ltd Battery
JP4522107B2 (en) * 2003-03-20 2010-08-11 パナソニック株式会社 Battery

Similar Documents

Publication Publication Date Title
KR0185247B1 (en) Resin-sealed semiconductor device
JPH04299851A (en) Lead frame for semiconductor device
JPH05267527A (en) Structure of lead frame for semiconductor device
JPS6365655A (en) Resin-sealed semiconductor device
JPH05136309A (en) Lead frame for pressure sensor and production of same
JPH0738051A (en) Resin mold electric device and its manufacture
JPH05121618A (en) Lead frame for semiconductor device and manufacture thereof
JPH06132443A (en) Semiconductor device and lead frame used for manufacture thereof
JPS622560A (en) Resin-sealed type semiconductor device
JP3230318B2 (en) Lead frame for semiconductor device
JPH04346257A (en) Manufacture of lead frame for semiconductor
JPH04322435A (en) Semiconductor device and manufacture thereof
JPH05251619A (en) Resin seal semiconductor device and manufacture thereof
JP2004200719A (en) Semiconductor device
JP2946775B2 (en) Resin sealing mold
KR0148083B1 (en) Lead frame having dummy pad and the use package
JPH0555433A (en) Semiconductor device
JPH07176673A (en) Lead frame and manufacture of semiconductor device employing lead frame
JPH02146740A (en) Semiconductor device
JPH08316371A (en) Resin sealed semiconductor device
JPH0574996A (en) Semiconductor sealed with resin
JPS6060743A (en) Lead frame
JPS63110661A (en) Resin sealed package for semiconductor integrated circuit
JPH08116013A (en) Lead frame and assembled semiconductor device using the lead frame
JPS61206247A (en) Lead frame for semiconductor device