JPS61206247A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPS61206247A JPS61206247A JP60046668A JP4666885A JPS61206247A JP S61206247 A JPS61206247 A JP S61206247A JP 60046668 A JP60046668 A JP 60046668A JP 4666885 A JP4666885 A JP 4666885A JP S61206247 A JPS61206247 A JP S61206247A
- Authority
- JP
- Japan
- Prior art keywords
- bed
- lead
- chip mounting
- straight line
- external lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の技術分野］
本発明は、樹脂封止型半導体装置に使用するリードフレ
ームに関するもので、特に半導体チップ装着ベッドのア
イランド形状の改善に係るものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a lead frame used in a resin-sealed semiconductor device, and particularly relates to an improvement in the island shape of a semiconductor chip mounting bed.
［発明の技術的背景］
半導体装置用リードフレームは一枚の金属板をプレス又
はエツチングして作られる。 リードフレームは、半導
体チップを装着するためのベッドと、チップの電極を外
部回路に導く複数のリードと、ベッド及びリードを製造
工程中所定の位置に保持するための連結バーとを単位フ
レームとし、この単位フレームを多数種べて搬送フレー
ムで連結した帯状の金属板である。 トランジスタやＩ
Ｃの組立は自動機械化した生産方式がとられ、リードフ
レームはこれに適した部材として一般に広く用いられて
いる。[Technical Background of the Invention] Lead frames for semiconductor devices are made by pressing or etching a single metal plate. The lead frame has a unit frame including a bed for mounting a semiconductor chip, a plurality of leads for guiding the electrodes of the chip to an external circuit, and a connecting bar for holding the bed and leads in a predetermined position during the manufacturing process, It is a band-shaped metal plate made up of a large number of unit frames connected by a transport frame. Transistor or I
C is assembled using an automatic mechanized production method, and lead frames are generally widely used as a member suitable for this purpose.
従来の樹脂封止型半導体装置に使用されるリードフレー
ムの単位フレームを例とし以下図面にもとづいて説明す
る。 第３図及び第４図は従来の樹脂封止型トランジス
タの平面図であって、図面を見易くづるため樹脂外囲器
の上側の樹脂を除去し、組立てられた半導体チップ及び
リード等を露出させた状態の平面図である。 第５図は
第４図のトランジスタに使用される単位リードフレーム
の平面図である。 １の半導体チップ（トランジスタチ
ップ）は２のチップ装着ベッド（アイランド）にロー材
等により装着固定される。 ３はリードでチップの電極
を外部回路に導出するためのものである。 この例でリ
ード３はチップ装着ベッド２から突出するリード３ａと
ベッド２から分離配４されるリード３ｂとから構成され
ている。A unit frame of a lead frame used in a conventional resin-sealed semiconductor device will be described below with reference to the drawings. FIGS. 3 and 4 are plan views of conventional resin-sealed transistors. In order to make the drawings easier to see, the resin on the upper side of the resin envelope has been removed to expose the assembled semiconductor chip, leads, etc. FIG. FIG. 5 is a plan view of a unit lead frame used in the transistor of FIG. 4. A semiconductor chip (transistor chip) 1 is mounted and fixed on a chip mounting bed 2 (island) using a brazing material or the like. 3 is a lead for leading out the electrodes of the chip to an external circuit. In this example, the lead 3 is composed of a lead 3a projecting from the chip mounting bed 2 and a lead 3b separated from the bed 2.
品種によってはチップ装着ベッドより突出するり一ドを
設けていないものもある。 ４は半導体チップ１とリー
ド３ｂとを電気接続するＡｌ１又はＡＩ等のボンディン
グワイＡ７である。 リード３ｂの端部の幅が広くなっ
ているのは主としてワイ■ボンディング作業を容易にす
るためである。Some types do not have a groove that protrudes from the chip mounting bed. 4 is a bonding wire A7 made of Al1 or AI, which electrically connects the semiconductor chip 1 and the leads 3b. The reason why the ends of the leads 3b are wide is mainly to facilitate the wire bonding operation.
一点鎖線７はチップ装着ベッド２から突出するリード３
ａの軸の中心線を延長した中心直線７である。 第３図
の例ではこの中心直線７に対しほぼ対称の位置にチップ
装着ベッドを設は半導体チップを装着している。 第４
図の例では中心直線７の一方の側に位置をずらして装着
している。 半導体デツプ１をチップ装着ベッド２に装
着し、ボンディングワイヤ４をボンディングした後トラ
ンスフ１モールド法等によりエポキシ等の樹脂により封
止される。 ５はこの封止用成形樹脂（樹脂外囲器）で
ある。 またリード３は樹脂封止された部分を内部リー
ド（インナーリード）、樹脂封止されず外側に露出する
部分を外部リード（アウターリード）と呼ぶ。 第５図
において８はダムバーで樹脂封止工程で樹脂の流出を防
止すると共にリードを互いに連結する。 また９は搬送
フレーム、１０は搬送孔で組立工程中リードフレームを
移動し所定の位置決めをする機能を持っている。A dashed line 7 indicates a lead 3 protruding from the chip mounting bed 2.
This is a center line 7 that is an extension of the center line of the axis a. In the example shown in FIG. 3, a chip mounting bed is provided at a position approximately symmetrical with respect to the center line 7, and semiconductor chips are mounted thereon. Fourth
In the example shown in the figure, the position is shifted to one side of the center straight line 7. After mounting the semiconductor dip 1 on a chip mounting bed 2 and bonding the bonding wire 4, it is sealed with a resin such as epoxy by a transfer molding method or the like. 5 is this molded resin for sealing (resin envelope). Further, the resin-sealed portion of the lead 3 is called an internal lead (inner lead), and the portion that is not sealed with resin and is exposed to the outside is called an external lead (outer lead). In FIG. 5, a dam bar 8 prevents resin from flowing out during the resin sealing process and connects the leads to each other. Further, reference numeral 9 denotes a conveyance frame, and 10 denotes a conveyance hole, which has the function of moving the lead frame and positioning it at a predetermined position during the assembly process.
ダムバー及び搬送フレームは製造過程でのみ必要なもの
で樹脂封止後切除される。 なおリードフレームの材料
は銅又は銅合金或いは鉄、ニッケルコバルト合金が一般
に使用される。The dam bar and transport frame are necessary only during the manufacturing process and are removed after resin sealing. Note that copper, a copper alloy, or an iron, nickel-cobalt alloy is generally used as the material of the lead frame.
［背景技術の問題点］
一般に半導体装置は回路基板等に外部リードによって取
り付けられる。 この取り付けは、装置の外部リードを
基板等のビン穴に挿入或いはプリント配線上の所定の位
置に外部リードを合わせた後半田付等により装着される
。 従って半導体装置の外部リードは樹脂封止後、取り
付は易い形状に成形加工する必要がある。 第２図は、
第３図及び第４図に示すような形状の半導体装置の外部
リードの成形加工後の一例を示す斜視図である。[Problems with Background Art] Generally, semiconductor devices are attached to a circuit board or the like using external leads. This attachment is carried out by inserting the external leads of the device into holes in the board, etc., or by soldering after aligning the external leads with predetermined positions on the printed wiring. Therefore, after the external leads of the semiconductor device are sealed with resin, it is necessary to mold them into a shape that is easy to attach. Figure 2 shows
FIG. 4 is a perspective view showing an example of an external lead of a semiconductor device having a shape as shown in FIGS. 3 and 4 after molding.
他方半導体装置は樹脂封止後の取り扱い中にリード間隔
やリードの直線度がくずれる場合がある。On the other hand, during handling of semiconductor devices after resin sealing, lead spacing and lead straightness may deteriorate.
特に小形の装置で外部リードの機械的強度が弱い場合に
は正常の形状からのズレがしばしば発生する。 この場
合においては装置を取り付ける直前、例えばビンレット
等によりズレを直すため成形が行われる。Particularly in small devices where the mechanical strength of the external leads is weak, deviations from the normal shape often occur. In this case, immediately before installing the device, molding is performed to correct misalignment using, for example, a binlet.
以上のように半導体装置は樹脂封止後その外部リードを
成形加工する必要がある。 この成形加工作業において
外部リードはその軸方向に引張り応力を受けることにな
る。 外部リードがチップ装置ベッドから突出するリー
ド（３ａ）の場合には、リードと同体のベッドに装着固
定されているチップにも当然応力が加わりその応力が一
定の限界を越えるとチップを破壊することになる。 外
形の小さい数ｍｍ程度の半導体装置においては特に成形
加工中のチップクラックは無視できない問題である。As described above, it is necessary to mold the external leads of a semiconductor device after resin sealing. During this molding process, the external lead is subjected to tensile stress in its axial direction. In the case where the external lead is a lead (3a) that protrudes from the chip device bed, stress is naturally applied to the chip attached and fixed to the same bed as the lead, and if the stress exceeds a certain limit, the chip may be destroyed. become. Chip cracks during molding are a problem that cannot be ignored, especially in semiconductor devices with small external dimensions on the order of several millimeters.
［発明の目的］
本発明の目的は、樹脂封止された半導体装置の樹脂成形
後外部リードを成形加工する工程において、外部リード
を介してチップ装着ベッドに加えられる外力を極力軽減
する形状の半導体装置用リードフレームを提供すること
である。[Object of the Invention] An object of the present invention is to provide a semiconductor having a shape that reduces as much as possible the external force applied to the chip mounting bed through the external leads in the process of molding the external leads after resin molding of a resin-sealed semiconductor device. An object of the present invention is to provide a lead frame for a device.
Ｕ発明の概要コ
本発明は、チップ装着ベッドから突出するリードを有す
る半導体装置用リードフレームにおいて、チップ装着ベ
ッドの中心の位置が、該ベッドから突出するリードの軸
の中心線を延長した中心直線の一方の側に偏在し、且つ
該ベッドが、前記中心直線の他方の側に突出する突起部
を有することを特徴とする半導体装置用リードフレーム
である。U Overview of the Invention The present invention provides a lead frame for a semiconductor device having leads protruding from a chip mounting bed, in which the center position of the chip mounting bed is located on a central straight line extending the center line of the axis of the lead projecting from the bed. The lead frame for a semiconductor device is characterized in that the bed has a protrusion that is unevenly distributed on one side of the bed and that protrudes to the other side of the center line.
本発明によるリードフレームは、半導体チップ装着ベッ
ド（アイランド）の形状を改善したものである。 即ち
ベッドと同体のリード軸の中心直線を挾んで一方の側に
ベッドを、他方の側に突起部を設けたものである。 ま
たこの突起部は、前記中心直線に対してベッドと反対方
向で、ベッド上部の樹脂外囲器面に平行に、ベッドと同
等又はそれに近い大きさで突出した形状を有する。 こ
のように装着ベッドを突起部付きのベッド形状とすると
、外部リード成形加工時、リードに引張り力が加わって
もその応力の一部は突起部が負担し、又せん断路力も突
起部で一部打消され、チップ装着ベッドに加わる外力が
従来に比し著しく軽減される。The lead frame according to the present invention has an improved shape of the semiconductor chip mounting bed (island). That is, the bed is provided on one side of the center straight line of the lead shaft, which is integral with the bed, and the protrusion is provided on the other side. Moreover, this protrusion has a shape that protrudes in a direction opposite to the bed with respect to the center line, parallel to the surface of the resin envelope at the upper part of the bed, and with a size equal to or close to that of the bed. If the mounting bed is shaped like a bed with protrusions in this way, even if tensile force is applied to the lead during external lead molding, part of the stress will be borne by the protrusions, and some of the shear path force will also be borne by the protrusions. As a result, the external force applied to the chip mounting bed is significantly reduced compared to the conventional method.
［発明の実施例］
この発明は主として従来の経験と試行にもとづき一部推
論を加えて行われた。 第３図の従来の半導体装置の場
合は、リード３ａに引張り力が加わるとリードの軸の中
心直線７上即ち引張り力の作用線上にチップ装着ベッド
２は設けられているので、ベッドの中央部に他部分に比
し強い応力が作用する。 また第４図においては、チッ
プ装着ベッド２がリード３ａの中心直１９７の右側（図
面上）に片寄って設けられているので、ベッドは直接の
引張り力は受けないが曲げモーメントによるせん断力が
作用する。 この為いずれの場合においても装着ベッド
に固定された半導体ベレットは強い応力を受は破壊しや
すくなるものと推論された。 これを解決する為装着ベ
ッドの位置を引張り外力の作用線上より片寄った位置と
し且つ曲げモーメントによるせん断力を相殺する為リー
ド軸の中心直線に対しベッドと反対側に突起部を設ける
こととした。[Embodiments of the Invention] This invention was made mainly based on conventional experience and trials, with some inferences added. In the case of the conventional semiconductor device shown in FIG. 3, when a tensile force is applied to the lead 3a, the chip mounting bed 2 is provided on the center straight line 7 of the axis of the lead, that is, on the line of action of the tensile force. A stronger stress acts on the area than on other parts. In addition, in FIG. 4, the chip mounting bed 2 is provided offset to the right side (in the drawing) of the center line 197 of the lead 3a, so the bed is not subjected to direct tensile force, but is subjected to shear force due to bending moment. do. For this reason, it was inferred that in any case, the semiconductor pellet fixed to the mounting bed would be susceptible to strong stress and would be easily destroyed. To solve this problem, the mounting bed was positioned off to the line of action of the tensile external force, and a protrusion was provided on the opposite side of the bed with respect to the center line of the lead shaft in order to offset the shear force caused by the bending moment.
第１図はベッドに突起部を設けた本発明のリードフレー
ムの １つの実施例を示すもので、図面はこのリードフ
レームを使用した半導体装置の平面図であり、図面を見
易くする為半導体チップ１、チップ装着ベッド２等の上
側の樹脂を除いて図示したものである。 なお図面にお
いて同一符号は第３図等と同一部分を表わす。 チップ
装着ベッド２の中心１１の位置はベッド２から突出する
リード３ａの軸の中心直１ｉ１７の一方の側（この図面
では右側）に偏在している。 又チップ装着ベッド２は
中心直線７の他方の側（この図面では左側）に突出する
突起部６を有している。FIG. 1 shows one embodiment of the lead frame of the present invention in which a protrusion is provided on the bed, and the drawing is a plan view of a semiconductor device using this lead frame. , the resin on the upper side of the chip mounting bed 2 and the like is not shown. In the drawings, the same reference numerals represent the same parts as in FIG. 3, etc. The center 11 of the chip mounting bed 2 is located unevenly on one side (on the right side in this drawing) of the axis 1i17 of the lead 3a projecting from the bed 2. The chip mounting bed 2 also has a protrusion 6 that protrudes to the other side of the center straight line 7 (to the left in this drawing).
第１図に示す形状のリードフレームを外囲器の小さい樹
脂封止型の製品に適用した実施例について説明する。
樹脂外囲器の外形寸法は幅１．５ａｍ、横３ｍｎ＋ 、
高さ１，１１１１ＩＩｌのものを用いた。 組み立てて
樹脂封止した後の上記装置（外部リードの成形をしてい
ない）の外部リードの先端部分をテスト基板等の所定の
位置に半田付を行い固定する。An example in which a lead frame having the shape shown in FIG. 1 is applied to a resin-sealed product with a small envelope will be described.
The external dimensions of the resin envelope are width 1.5am, width 3mm+,
The one with a height of 1,1111 IIl was used. After being assembled and resin-sealed, the tips of the external leads of the above device (no external lead molding) are soldered and fixed to a predetermined position on a test board or the like.
次に第２図に示すような形状に外部リードを成形加工す
る。 外部リードの成形加工の前後で装置の特性を調べ
、特性変化及びチップの破壊の有無を調べた。 その結
果不良発生は皆無であった。Next, external leads are molded into the shape shown in FIG. The characteristics of the device were examined before and after the external lead molding process, and changes in characteristics and chip breakage were examined. As a result, there were no defects.
このことにより突起部は外部リードに印加される引張り
力のかなりの部分を負担し、引張り応力を止める役目を
することが確認された。This confirms that the protrusion bears a significant portion of the tensile force applied to the external lead and serves to stop the tensile stress.
［発明の効果］
従来のリードフレームを用いた樹脂封止型半導体装置で
は、リード成形を行うことによりチップの破壊及び特性
不良となるものが５〜３０％も発生していた。 本発明
によるリードフレームを用いることによりリード成形に
よる不良発生を皆無にすることができた。[Effects of the Invention] In resin-sealed semiconductor devices using conventional lead frames, 5 to 30% of chips were destroyed or had poor characteristics due to lead molding. By using the lead frame according to the present invention, it was possible to completely eliminate defects caused by lead molding.
第１図は本発明のリードフレームを使用した半導体装置
の平面図、第２図は第１図、第３図及び第４図の半導体
装置の外部リードを成形加工した状態を表わす斜視図、
第３図及び第４図は従来の半導体装置の平面図、第５図
は従来のリードフレームの平面図である。
１・・・半導体チップ、 ２・・・チップ装着ベッド（
アイランド）、 ３・・・リード、 ３ａ・・・チップ
装着ベッドから突出するリード、 ５・・・樹脂外囲器
、 ６・・・突起部、 ７・・・リード軸の中心直線、
１１・・・チップ装着ベッドの中心。
第１図
第２図
第３図
第４図
「
第５図FIG. 1 is a plan view of a semiconductor device using the lead frame of the present invention, and FIG. 2 is a perspective view showing the state in which the external leads of the semiconductor devices of FIGS. 1, 3, and 4 have been formed.
3 and 4 are plan views of a conventional semiconductor device, and FIG. 5 is a plan view of a conventional lead frame. 1... Semiconductor chip, 2... Chip mounting bed (
3...Lead, 3a...Lead protruding from the chip mounting bed, 5...Resin envelope, 6...Protrusion, 7...Center straight line of lead axis,
11... Center of chip installation bed. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5
Claims (1)
ッドから突出するリードとを有する半導体装置用リード
フレームにおいて、 チップ装着ベッドの中心の位置が該ベッドから突出する
リード軸の中心直線の一方の側に偏在すると共に該ベッ
ドが前記中心直線の他方の側に突出する突起部を有する
ことを特徴とする半導体装置用リードフレーム。[Claims] 1. In a lead frame for a semiconductor device having a chip mounting bed on which a semiconductor chip is mounted and leads protruding from the bed, the center of the chip mounting bed is located at the center of the lead shaft protruding from the bed. A lead frame for a semiconductor device, characterized in that the bed has protrusions that are unevenly distributed on one side of the straight line and protrude to the other side of the center straight line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60046668A JPS61206247A (en) | 1985-03-11 | 1985-03-11 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60046668A JPS61206247A (en) | 1985-03-11 | 1985-03-11 | Lead frame for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61206247A true JPS61206247A (en) | 1986-09-12 |
| JPH0527986B2 JPH0527986B2 (en) | 1993-04-22 |
Family
ID=12753732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60046668A Granted JPS61206247A (en) | 1985-03-11 | 1985-03-11 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61206247A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012015202A (en) * | 2010-06-29 | 2012-01-19 | On Semiconductor Trading Ltd | Semiconductor device, and method of manufacturing the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS555586A (en) * | 1978-06-29 | 1980-01-16 | Mitsubishi Electric Corp | Demodulation circuit for digital signal |
| JPS5555586A (en) * | 1978-10-19 | 1980-04-23 | Matsushita Electric Ind Co Ltd | Luminous part |
| JPS57155757A (en) * | 1981-03-23 | 1982-09-25 | Hitachi Ltd | Semiconductor device |
| JPS59191360A (en) * | 1983-04-15 | 1984-10-30 | Internatl Rectifier Corp Japan Ltd | Lead frame material for semiconductor device and lead frame as well as assembling for semiconductor device |
-
1985
- 1985-03-11 JP JP60046668A patent/JPS61206247A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS555586A (en) * | 1978-06-29 | 1980-01-16 | Mitsubishi Electric Corp | Demodulation circuit for digital signal |
| JPS5555586A (en) * | 1978-10-19 | 1980-04-23 | Matsushita Electric Ind Co Ltd | Luminous part |
| JPS57155757A (en) * | 1981-03-23 | 1982-09-25 | Hitachi Ltd | Semiconductor device |
| JPS59191360A (en) * | 1983-04-15 | 1984-10-30 | Internatl Rectifier Corp Japan Ltd | Lead frame material for semiconductor device and lead frame as well as assembling for semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012015202A (en) * | 2010-06-29 | 2012-01-19 | On Semiconductor Trading Ltd | Semiconductor device, and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0527986B2 (en) | 1993-04-22 |
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