JPS61168947A - Manufacture of semiconductor device and leadframe used in said device - Google Patents

Abstract

PURPOSE:To prevent deformation of the inner end parts of leads, by performing patterning of parts other than the inner end regions of the leads and a chip arranging area at first, and performing the patterning of the inner end regions of the leads and the chip arranging region immediately before chip bonding. CONSTITUTION:The unit lead pattern of a leadframe 1 becomes a conveying pattern 2 by the first lead-pattern forming process. A bonding pattern 3 is obtained by the second lead-pattern forming process. A tab 4 and leads 5 are linked to the conveying pattern 2. The central part of the leadframe 1 is hard to be deformed in handling such as conveying. In the second lead-pattern forming process, precision press molding of the central part of the leadframe is carried out and the tab 4 and the inner end parts of the leads 5 are molded. Thus, the bonding pattern 3 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing a semiconductor device and a lead frame used in the manufacturing.

[Background technology]

A member called a lead frame is used in the manufacture of resin package type semiconductor devices. This lead frame can be found, for example, in "Monthly Se-m1conductor" published by Press Journal Co., Ltd.
WorldJ May 1984 issue, July 15, 1984
As described in the Japanese publication, pH1 to P115, lead frames are formed by etching or punching thin metal plates such as copper or iron-nickel alloys, and include tabs for attaching chips and leads for connecting wires. It has pattern members that make up the pattern. Further, the bonding portions of the tabs and leads to which chips and wires are attached are plated with gold, silver, etc. in order to improve the reliability of the connection.

On the other hand, as described in the above-mentioned literature, the thickness of the lead frame made of a metal plate is as thin as 100 to 250 μm, and the number of leads is 8 (the number of pins is, for example, 60 to 250 μm) due to the high integration of semiconductor devices. 80), and the width and pitch of the lead tips (inner ends) are also becoming narrower due to the miniaturization of semiconductor devices. Further, in manufacturing the lead frame, attention is paid to flatness so as to prevent warping or deformation.

Incidentally, these conventional lead frames are handled and sold with the tips of the leads separated from each other.

However, when handling such lead frames,
The inside of the lead and the tab part that fixes the chip are easily deformed.
The inventors have found that it is difficult to accurately and reliably perform chip bonding and wire bonding on deformed products, leading to lower bonding reliability and the possibility of producing defective products. That is, as mentioned above, since the lead is thin and thin, for example, when the lead frame is manufactured and wound onto a reel, overlaps occur.
Furthermore, it has been found that leads and tabs are often contacted during masking and the like during the meshing work after lead frame formation, and deformations such as deviation, inclination, twisting, and floating occur at times.

[Purpose of the invention]

An object of the present invention is to provide a method for manufacturing a semiconductor device of excellent quality.

Another object of the present invention is to provide a method of manufacturing a semiconductor device that can improve assembly yield.

Another object of the present invention is to provide a lead frame in which the inner end portions of the leads are not easily deformed until just before chip bonding.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in the present invention, when forming the first lead pattern, the lead frame is patterned except for the inner end NkR of the lead and the chip placement area, and then partial plating is applied, and the 21st lead frame is patterned just before chip bonding.
7-Card patterning is performed to pattern the inner end area of the leads and the chip placement area in the center of the lead frame, and then chip bonding and wire bonding are performed, so that the leads and tabs may become uneven during chip bonding. , deformations such as twisting, ups and downs are less likely to occur, chimp bonding and wire bonding can be performed accurately and reliably, and improvements in bonding reliability and assembly yield can be achieved.

〔Example〕

FIG. 1 is a plan view of a lead frame according to an embodiment of the present invention, FIG. 2 is a flowchart showing the method for manufacturing a semiconductor device of the present invention, and FIG. 3 is a plan view of a lead frame according to an embodiment of the present invention. FIG. 4 is a plan view of the lead frame; FIG. 4 is a sectional view showing the tab portion of the lead frame; FIG. 5 is a plan view of the lead frame after chip bonding, wire bonding, sealing, etc. FIG. 6 is a perspective view of a semiconductor device having a resin package structure in a completed state.

In this embodiment, a resin package type semiconductor device (FC
) manufacturing method will be explained.

This IC has an external appearance as shown in FIG. 6, and as shown in the flowchart of FIG. It is manufactured through a chimp bonding process, a wire bonding process, a sealing process, and a cutting and molding process.

When manufacturing this IC, first a lead frame material made of an iron-nickel metal plate with a thickness of about 0.2 μm is prepared. This lead frame material is subjected to a first lead pattern forming process and a 21st J-do pattern forming process to form a final unit lead pattern. That is, the lead frame 1 is formed by performing two thick molding processes (precision press molding process) on the lead frame material, and the unit lead pattern of the lead frame 1 is formed by performing the first lead pattern forming process. By,
The conveyance pattern 2 as shown in FIG. 1 is formed, and by the second lead pattern forming process, as shown in FIG.
This becomes bonding pattern 3. In the conveyance pattern 2, tabs 4 and leads 5, which will be described later, are connected, and the central portion of the lead frame 1 is difficult to deform during handling such as transportation. Further, the bonding pattern 3 is formed on the lead frame 1 by the first lead pattern forming process.
The inner end portions of the tab 4 and the lead 5 are formed by precision press molding of the center portion.

Next, the lead frame 1 that becomes the conveyance pattern 2 shown in FIG. 1 will be explained. The lead frame 1 has a pair of outer frames 6 and tie bars 7 that connect the outer frames 6 at regular intervals. A first lead pattern forming pattern is formed by a pair of corresponding outer frames 6 and tie bars 7 in a rectangular shape. This unit lead pattern has a substantially rectangular wide portion 8 in the central portion. Further, this lead frame 1 has thin tab leads 9 extending from the inside center of the outer frame 6, as in the conventional lead frame. These tab leads 9 are bent in the middle to absorb thermal strain, and their tips (inner ends) are connected to the wide portion 8 . Also, leads 5 protrude from the inside of the tie bar 7 at regular intervals. These leads 5 extend parallel to the outer frame 6, but most of them are complicatedly bent in the middle because they are connected to the wide portion 8 located at the center of the lead frame 1. Further, the unit lead pattern has a thin dam 10 located on a line connecting the outer frames 6 facing each other and connecting the adjacent leads 5 and the leads 5 and the outer frame 6. This dam IO functions as a dam to prevent the molten resin from flowing out during resin molding to form a resin buff cage 11 (see FIG. 5), which will be described later.

On the other hand, since the portion of the lead 5 extending from the dam 10 to the tie bar 7 protrudes from the resin puff cage 11,
This is called an outer lead 12, and the inner part of the dam 10 is called an inner lead 13 because it enters the resin package 11. The tip (inner end) of the inner lead 13 is connected to the wide portion 8 as described above. Further, this inner lead 13 is provided with a hole 14 and an overhang 15 (or a notch), etc., so that the lead 5 does not bite into the resin part of the resin package 11 and come out from the resin package 11. ing. Further, the outer frame 6 is provided with guide holes 16 to 18, which are used as guides in transporting or positioning the lead frame 1.

Next, the lead frame 1 having such a transfer pattern 2 is partially plated in the chip mounting area, wire bonding area, etc. (for example, plating is applied to the dotted areas in FIG. 1). ).

Next, as shown in FIG. 3, the lead frame l is subjected to a 217th pattern forming process (precision press process), and the central tab 4 of the single lead pattern is partially cut and removed to form a tab lead. A rectangular tab 4 with a series of 9 is formed, and each lead 5 is separated. Further, during this process, the tab 4 is formed one step lower, as shown in FIG.

This is a chip (semiconductor element) 1 fixed on tab 4.
Even if the wire 20 connecting the electrode 9 and the inner end of the lead 5 were to hang down, consideration should be given to prevent the wire 20 from coming into contact with the periphery of the chip 19 and causing a short circuit. It is.

Next, in such a lead frame 1, as shown in FIG. 5, a chip 19 is bonded onto the tab 4, and the electrodes (not shown) of this chip 19 are connected to the inner ends of the adhesives 5 on both sides. Connected by wire 20. after that,
This lead frame 1 is resin molded, and the tip portion of the lead 5 (most portion of the inner lead 13)
is covered with a resin package 11 made of insulating resin.

Next, as shown in FIG. (Outer lead 12) is
By folding it to the same side, a dual in-line resin packaged semiconductor device 21 is manufactured.

〔effect〕

(1) According to the present invention, during transportation, storage, or pretreatment before the chip bonding process, the inner ends of the leads 5 are connected to each other by the wide part 8 including the tab 4 portion, and the inner ends of the leads 5 are connected to each other by the wide part 8 including the tab 4 portion, and the inner ends of the leads 5 are connected to each other by the wide part 8 including the tab 4 portion. Cut off tab 4
．． Since the inner end portion of the lead 5 is formed, it is difficult to deform even if an external force is applied to the center portion of the lead frame I before the second lead pattern formation process just before chip bonding.
For this reason, tab 4. The effect is that the frequency or degree of deformation of the leads 5, etc., such as deviation, twisting, ups and downs, etc., is extremely less and smaller than in conventional lead frames.

(2) According to the above (1), according to the present invention, there is almost no deformation of the tab 4 or lead 5 during chip bonding or wire bonding, so that accurate and reliable chip bonding and wire bonding can be performed, and the bonding characteristics of the semiconductor device This has the effect of achieving an improvement in .

(3) According to the above (11), according to the present invention, there is almost no deformation of the tab 4 or lead 5 during chip bonding or wire bonding, so that the deformed portion of the lead frame 1 does not come into contact with the device.

Since it is difficult for the device to get stuck, the operating rate of the device is improved and the standard time (ST) of the work can be reduced.

(4) According to the above (2), according to the present invention, wire bonding becomes accurate and reliable, the shape of the stretched wire loop becomes good, and there is no risk of short circuits, etc., so the quality of the semiconductor device is improved. (characteristics) can be improved.

(5) According to the above (2) to (4), according to the present invention, since chip bonding or wire bonding becomes positive and reliable, it is possible to achieve the effect of improving the yield.

(6) According to the above (1) to (5), according to the present invention, deformation of the tab 4 and lead 5 is less likely to occur in the manufacturing of semiconductor devices, and the frequency of occurrence of defective products can be reduced. A synergistic effect can be obtained in that cost reduction can be achieved.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, even if the inner ends of the leads in the lead frame are only partially connected, the same effect as in the embodiment described above can be obtained. In addition, the plating process in the above embodiment is performed without any problems even before the first lead pattern forming process. Further, even if the unit lead patterns of the first lead pattern and the second lead pattern in the lead frame are formed by an etching method, the same effects as in the above embodiment can be obtained. In particular, lead pattern formation by etching becomes more effective as the number of leads increases and the pattern becomes finer.

Further, as shown in FIGS. 7 to 9, the present invention can be applied to the production of glass package products in the same manner as in the embodiment described above, and the same effects as in the embodiment described above can be obtained. In this case, as shown in FIG.
After the lead pattern forming process, the leads 5 are bent. Thereafter, as shown in FIG. 8, the soft frame 1 is subjected to a second lead pattern forming process. As a result, the inner ends of each lead 5 are independent from each other. At this time, the lead frame 1 for the glass package is not provided with a tab or a tab lead, and a space slightly larger than the chip (a space where the chip is placed) is formed in the center of the single lead pattern. The lead frame 1 after the second lead pattern forming process is fixed to a base 22 made of ceramic, as shown in FIG. Since the base 22 is coated with glass (not shown) on its upper surface in advance, the lead frame 1 can be heated by overlapping the lead frame 1 on the base 22 and temporarily heating the glass portion in this state. lead 5
The inner edges of the are glued together. Further, when the glass is melted, the chip 19 is placed in the center of the base 22 and is adhesively fixed by the glass. Thereafter, an unillustrated electrode of the chip 19 and the inner end of each lead 5 are connected by a wire 20. Further, a camp 23 made of ceramic is airtightly mounted on the base 22, and the leads 5 are cut from the outer frame 6 to produce a glass package type semiconductor device 24 as shown in FIG. 9.

[Application field]

The above description has mainly been about the case where the invention made by the present inventor is applied to the manufacturing technology of a dual in-line type semiconductor device, which is the background field of application, but the invention is not limited to this, for example, It can be applied to manufacturing technology for flat semiconductor devices.

The present invention can be applied at least to techniques such as press molding.

[Brief explanation of drawings]

FIG. 1 is a plan view of a lead frame according to an embodiment of the present invention, FIG. 2 is a flowchart showing a method for manufacturing a semiconductor device according to the present invention, and FIG. 3 is a lead used in manufacturing a semiconductor device according to the present invention. A plan view of the frame; FIG. 4 is a sectional view showing the tab portion of the lead frame; FIG. 5 is a plan view of the lead frame after chimp bonding, wire bonding, sealing, etc. have been completed; 7 is a perspective view of a lead frame according to another embodiment of the present invention, and FIG. 8 is the same (a perspective view showing a state of chip bonding using the lead frame). 9 is a perspective view showing a glass-sealed semiconductor device manufactured using the lead frame. 1. Lead frame, 2. Conveyance pattern, 3.
... bonde ink pattern, 4... tab, 5...
・Lead, 6... Outer frame, 7... Tie bar, 8...
Wide part, 9...Tab lead, 10...Dam, 11.
...Resin package, 12...Outer lead, 1
3... Inner lead, 14... Hole, 15... Overhang, 16-18... Guide hole, 19... Chip (semiconductor element), 20... Wire, 21... Resin package type semiconductor device, 22... base, 23...
・Cap, 24...Glass bag Figure 1 Figure 2 Figure 6 Figure 7

Claims (1)

[Claims] 1. The method includes the steps of patterning a lead frame material, performing chip bonding and wire bonding on the patterned lead frame, and sealing the inner ends of the chip, wire, and lead. A method for manufacturing a semiconductor device, which includes the steps of preparing the lead frame material, and forming a first lead pattern in which a patterning process is performed on the lead frame material to pattern a portion excluding an inner end region of the lead and a chip placement region. and a second lead frame pattern forming step of subjecting the lead frame material to patterning again to pattern the inner end region of the lead and the chip placement region immediately before the chip bonding operation. A method for manufacturing a semiconductor device, characterized by: 2. The method for manufacturing a semiconductor device according to claim 1, wherein a tab for mounting a chip is formed during the second lead pattern forming process, and this tab portion is formed one step lower. . 3. A lead frame characterized in that a plate-shaped wide portion made of a lead frame material is provided in the lead frame portion corresponding to the chip placement area, and the inner ends of each lead are connected to this wide portion.