JPH07201928A - Film carrier and semiconductor device - Google Patents
Film carrier and semiconductor deviceInfo
- Publication number
- JPH07201928A JPH07201928A JP5352989A JP35298993A JPH07201928A JP H07201928 A JPH07201928 A JP H07201928A JP 5352989 A JP5352989 A JP 5352989A JP 35298993 A JP35298993 A JP 35298993A JP H07201928 A JPH07201928 A JP H07201928A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor element
- semiconductor device
- film carrier
- base film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、フィルムキャリア及び
このフィルムキャリアに半導体素子を搭載した半導体装
置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a film carrier and a semiconductor device having a semiconductor element mounted on the film carrier.
【０００２】[0002]
【従来の技術】従来の半導体装置として、例えば図７に
示すリードフレームを用いたものがある。即ち、金属製
リードフレーム１１のマウント部１１ａ上に半導体素子
１２を搭載し、金線ワイヤ１３により半導体素子１２の
電極部とリードフレーム１１の外部リード１１ｂとの電
気的な接続をとった後、樹脂１４により封止を行ってい
る。2. Description of the Related Art As a conventional semiconductor device, there is one using a lead frame shown in FIG. 7, for example. That is, after mounting the semiconductor element 12 on the mount portion 11a of the metal lead frame 11 and electrically connecting the electrode portion of the semiconductor element 12 and the outer lead 11b of the lead frame 11 by the gold wire 13, The resin 14 is used for sealing.
【０００３】ところが、このようなリードフレーム１１
を用いた半導体装置においては、半導体素子１２と外部
リード１１ｂとの電気的接続をワイヤ１３によって行っ
ているため、ワイヤ１３のルーピングのためのスペース
が必要になり、樹脂部１４を小型薄型にするのが困難で
あった。However, such a lead frame 11
In the semiconductor device using, since the semiconductor element 12 and the external lead 11b are electrically connected by the wire 13, a space for looping the wire 13 is required, and the resin portion 14 is made small and thin. Was difficult.
【０００４】そこで、小型薄型化が可能な半導体装置と
して、例えば図８に示すＴＡＢ（Tape Automated Bondi
ng）方式が知られている。即ち、絶縁性ベースフィルム
２２上に導体リード２３を形成してなるフィルムキャリ
ア２１を用い、ベースフィルム２２のデバイス孔２２ａ
内に突出されたインナーリード２３ａに半導体素子２４
の電極部を接合し、ベースフィルム２２のリード孔２２
ｂに架橋されたアウターリード２３ｂが露出するよう
に、半導体素子２４とベースフィルム（サポート部）２
２とを樹脂２５により封止する。この後、アウターリー
ド２３ｂをベースフィルム２２の外枠部２２ｃから切断
してフォーミングしている。Therefore, as a semiconductor device which can be made smaller and thinner, for example, a TAB (Tape Automated Bondi) shown in FIG.
ng) method is known. That is, the film carrier 21 formed by forming the conductor leads 23 on the insulating base film 22 is used, and the device hole 22a of the base film 22 is used.
The semiconductor element 24 is attached to the inner lead 23a protruding inward.
Of the base film 22 by joining the electrode portions of
The semiconductor element 24 and the base film (support part) 2 are exposed so that the outer leads 23b cross-linked to the b are exposed.
2 is sealed with resin 25. After that, the outer leads 23b are cut from the outer frame portion 22c of the base film 22 and are formed.
【０００５】[0005]
【発明が解決しようとする課題】ところが、上述したよ
うなＴＡＢ方式におけるフィルムキャリア及び半導体装
置では、前記リードフレーム１１の外部リード１１ｂよ
りも遙かに薄く撓み易いフィルムキャリア２１のアウタ
ーリード２３ｂを切断・フォーミングしているために、
このアウターリード２３ｂが変形し易い。また、アウタ
ーリード２３ｂを切断することによって、その切断面が
酸化する上に、切断時にバリも発生し易い。このような
アウターリード２３ｂの変形や切断面の酸化等によっ
て、基板等への実装時にアウターリード２３ｂの接合精
度が低下するという問題があった。However, in the film carrier and the semiconductor device in the TAB method as described above, the outer lead 23b of the film carrier 21 which is much thinner and more flexible than the outer lead 11b of the lead frame 11 is cut.・ Because they are forming,
This outer lead 23b is easily deformed. Further, by cutting the outer leads 23b, the cut surface is oxidized and burrs are easily generated during cutting. Due to such deformation of the outer lead 23b and oxidation of the cut surface, there has been a problem that the accuracy of joining the outer lead 23b is lowered during mounting on a substrate or the like.
【０００６】そこで本発明は、上記課題を解決するため
になされたもので、小型薄型化が可能でかつリード変形
が生じないフィルムキャリア及び半導体装置を提供する
ことを目的とする。Therefore, the present invention has been made to solve the above problems, and an object of the present invention is to provide a film carrier and a semiconductor device which can be reduced in size and thickness and in which lead deformation does not occur.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に、本発明は、半導体素子に接続される導体リードを絶
縁性ベースフィルム上に形成してなるフィルムキャリア
において、前記ベースフィルムが、前記半導体素子を配
置する素子搭載部と前記導体リードを保持するリード保
持部とを有し、前記半導体素子の電極部に接続される前
記導体リードの両端部が、それぞれ前記ベースフィルム
の素子搭載部とリード保持部とによって支持されている
ものである。In order to achieve the above object, the present invention provides a film carrier in which conductor leads connected to a semiconductor element are formed on an insulating base film, wherein the base film is The semiconductor device has an element mounting portion for arranging a semiconductor element and a lead holding portion for holding the conductor lead, and both ends of the conductor lead connected to the electrode portion of the semiconductor element are respectively the element mounting portion of the base film. It is supported by the lead holding portion.
【０００８】また、本発明による半導体装置は、前記フ
ィルムキャリアと、このフィルムキャリアに搭載される
半導体素子とからなり、前記ベースフィルムの素子搭載
部上に前記半導体素子の回路面側が搭載されており、前
記ベースフィルムの素子搭載部とリード保持部とによっ
て支持された前記導体リードの両端部間の一部が前記半
導体素子の電極部に接続されているものである。The semiconductor device according to the present invention comprises the film carrier and a semiconductor element mounted on the film carrier, and the circuit surface side of the semiconductor element is mounted on the element mounting portion of the base film. A part between both ends of the conductor lead supported by the element mounting portion and the lead holding portion of the base film is connected to the electrode portion of the semiconductor element.
【０００９】なお、前記半導体装置において、前記半導
体素子及び前記フィルムキャリアが樹脂によって封止さ
れ、前記ベースフィルムのリード保持部によって保持さ
れた前記導体リードの先端部が樹脂部の下面から露出し
てその下面に固定されているものである。In the semiconductor device, the semiconductor element and the film carrier are sealed with resin, and the tip ends of the conductor leads held by the lead holding portion of the base film are exposed from the lower surface of the resin portion. It is fixed to the lower surface.
【００１０】さらに、前記半導体装置において、前記導
体リードの全面がメッキにより被覆されているものであ
る。Further, in the semiconductor device, the entire surface of the conductor lead is covered by plating.
【００１１】[0011]
【作用】上記のように構成された本発明によれば、ベー
スフィルムの導体リードが半導体素子の電極部に接続さ
れるため、樹脂封止した場合には樹脂部の厚さを薄くす
ることができるが、特に、ベースフィルムのリード保持
部によって保持された導体リードの先端部が外部リード
となるので、その外部リードを切断する必要がなく、外
部リードの変形を防止することができる。そして、樹脂
封止した場合には、外部リードが樹脂部の下面から露出
してその下面に固定されるため、外部リードを短くして
変形なく配列することができる。また、外部リードを切
断する必要がないので、切断面の酸化やバリの発生等を
防止することができる上に、導体リードの全面にメッキ
を施しておけば、外部リードの端面にもメッキ被覆を最
後まで残存させることができる。According to the present invention configured as described above, since the conductor lead of the base film is connected to the electrode portion of the semiconductor element, it is possible to reduce the thickness of the resin portion when the resin is sealed. However, in particular, since the tip end portion of the conductor lead held by the lead holding portion of the base film becomes the external lead, it is not necessary to cut the external lead, and the deformation of the external lead can be prevented. In the case of resin sealing, the external leads are exposed from the lower surface of the resin portion and fixed to the lower surface, so that the external leads can be shortened and arranged without deformation. Also, since it is not necessary to cut the external leads, it is possible to prevent oxidation and burrs on the cut surface, and if the entire surface of the conductor leads is plated, the end faces of the external leads will also be plated. Can remain until the end.
【００１２】[0012]
【実施例】以下、本発明によるフィルムキャリア及び半
導体装置の実施例について図１〜図６を参照して説明す
る。Embodiments of the film carrier and semiconductor device according to the present invention will be described below with reference to FIGS.
【００１３】図１は本実施例における半導体装置の断面
図、図２（Ａ）はその上面図、図２（Ｂ）はその裏面図
である。FIG. 1 is a sectional view of a semiconductor device according to this embodiment, FIG. 2A is a top view thereof, and FIG. 2B is a back view thereof.
【００１４】１は半導体素子、２はフィルムキャリアで
ある。フィルムキャリア２は、ポリイミド等からなる絶
縁性のベースフィルム３と、銅箔等によりパターン形成
された複数の導体リード４とによって構成されている。
５はＡｕ等からなる金属バンプ、６は樹脂モールドであ
る。Reference numeral 1 is a semiconductor element, and 2 is a film carrier. The film carrier 2 is composed of an insulating base film 3 made of polyimide or the like, and a plurality of conductor leads 4 pattern-formed with copper foil or the like.
Reference numeral 5 is a metal bump made of Au or the like, and 6 is a resin mold.
【００１５】ベースフィルム３は、半導体素子１を搭載
する内側域の素子搭載部３ａと、外側域のリード保持部
３ｂとを有しており、素子搭載部３ａとリード保持部３
ｂとの間は電極部接続用のリード孔３ｃとなっている。
導体リード４は、その内端部４ａ及び先端部４ｂがそれ
ぞれ素子搭載部３ａ及びリード保持部３ｂにより支持さ
れ、リード孔３ｃに架橋されている。The base film 3 has an element mounting portion 3a in the inner area for mounting the semiconductor element 1 and a lead holding portion 3b in the outer area. The element mounting portion 3a and the lead holding portion 3 are provided.
A lead hole 3c for connecting the electrode portion is formed between the lead wire 3b and the electrode b.
The conductor lead 4 has its inner end portion 4a and tip portion 4b supported by the element mounting portion 3a and the lead holding portion 3b, respectively, and is bridged to the lead hole 3c.
【００１６】半導体素子１は、その回路面１ａ側が絶縁
性の接着剤等を介してベースフィルム３の素子搭載部３
ａ上に接着されている。そして、導体リード４の内端部
４ａ及び先端部４ｂ間の一部（内端部４ａ寄り）が、バ
ンプ５を介して半導体素子１の電極部に接合されてい
る。The semiconductor element 1 has an element mounting portion 3 of the base film 3 on the circuit surface 1a side with an insulating adhesive or the like interposed therebetween.
It is glued on a. A part (closer to the inner end 4 a) between the inner end 4 a and the tip 4 b of the conductor lead 4 is bonded to the electrode portion of the semiconductor element 1 via the bump 5.
【００１７】半導体素子１及びフィルムキャリア２が樹
脂モールド６によって封止された際、ベースフィルム３
のリード保持部３ｂはリード先端部４ｂと共に樹脂モー
ルド６の下面６ａから露出している。リード先端部４ｂ
はリード保持部３ｂにより保持されているので、このリ
ード先端部４ｂ即ち外部リードは樹脂モールド６の下面
６ａに固定されることになる。なお、ベースフィルム３
のリード保持部３ｂは必ずしも露出している必要はな
い。When the semiconductor element 1 and the film carrier 2 are sealed by the resin mold 6, the base film 3
The lead holding portion 3b is exposed from the lower surface 6a of the resin mold 6 together with the lead tip portion 4b. Lead tip 4b
Is held by the lead holding portion 3b, the lead tip portion 4b, that is, the external lead, is fixed to the lower surface 6a of the resin mold 6. The base film 3
The lead holding portion 3b does not necessarily have to be exposed.
【００１８】次に、図３は上記フィルムキャリアの構成
を示す平面図である。フィルムキャリア２は長尺テープ
状をなし、前記１つの半導体装置を構成する１ブロック
がテープの長手方向に沿って多数列設されている。な
お、２ａはスプロケット孔である。Next, FIG. 3 is a plan view showing the structure of the film carrier. The film carrier 2 is in the form of a long tape, and a large number of one block constituting one semiconductor device are arranged in the longitudinal direction of the tape. In addition, 2a is a sprocket hole.
【００１９】フィルムキャリア２のベースフィルム３に
おいて、素子搭載部３ａは連結部３ｄにより外枠部３ｅ
に支持されているが、リード保持部３ｂは外枠部３ｅか
ら分離されている。そして、素子搭載部３ａからリード
孔３ｃを経てリード保持部３ｂまで形成された導体リー
ド４は外枠部３ｅへは延長されていない。In the base film 3 of the film carrier 2, the element mounting portion 3a is connected to the outer frame portion 3e by the connecting portion 3d.
However, the lead holding portion 3b is separated from the outer frame portion 3e. The conductor lead 4 formed from the element mounting portion 3a through the lead hole 3c to the lead holding portion 3b is not extended to the outer frame portion 3e.
【００２０】樹脂モールド６の外形線６ｂに示すよう
に、リード保持部３ｂにより保持されたリード先端部４
ｂが外部リードとなるので、このリード先端部４ｂを切
断する必要はない。そして、半導体素子１を搭載する前
のフィルムキャリア２の段階で、導体リード４の全面に
Ａｕ等によるメッキが施されるが、リード先端部４ｂを
切断しないので、そのリード先端部４ｂの端面にもメッ
キ被覆が最後まで残存し、下地は露出しない。従って、
リード先端部４ｂの端面が酸化したりバリが発生したり
することはない。As shown by the outline 6b of the resin mold 6, the lead tip portion 4 held by the lead holding portion 3b.
Since b serves as an external lead, it is not necessary to cut the lead tip 4b. Then, at the stage of the film carrier 2 before mounting the semiconductor element 1, the entire surface of the conductor lead 4 is plated with Au or the like, but since the lead tip 4b is not cut, the end surface of the lead tip 4b is not cut. However, the plating coating remains to the end and the base is not exposed. Therefore,
The end face of the lead tip portion 4b is not oxidized or burrs are generated.
【００２１】なお、フィルムキャリア２を図４に示すよ
うな配線パターンにしてもよい。この例では、導体リー
ド４の内端部４ａが、ベースフィルム３の素子搭載部３
ａへ延長され、連結部３ｄ上から外枠部３ｅへ導かれ、
先端にテストパッド４ｃが設けられている。The film carrier 2 may have a wiring pattern as shown in FIG. In this example, the inner end portion 4 a of the conductor lead 4 is the element mounting portion 3 of the base film 3.
a, and is guided to the outer frame portion 3e from above the connecting portion 3d,
A test pad 4c is provided at the tip.
【００２２】次に、図５を参照して上記半導体装置の組
立工程を説明する。（Ａ）は図３のフィルムキャリアの
断面図であり、（Ｂ）において、ベースフィルム３の素
子搭載部３ａ上に半導体素子１の回路面１ａ側を接着剤
等を介して固着する。次に（Ｃ）において、導体リード
４と半導体素子１の電極部とをバンプ５を介して接合す
ると共に、導体リード４を成形加工する。そして（Ｄ）
において、（Ｃ）の加工品をモールド金型７ａ及び７ｂ
内に保持する。このとき、リード保持部３ｂ及びリード
先端部４ｂを金型７ａ及び７ｂによって挟持する。この
状態で樹脂封止を行い、図１の半導体装置が完成する。Next, the assembling process of the semiconductor device will be described with reference to FIG. 3A is a cross-sectional view of the film carrier of FIG. 3, and in FIG. 3B, the circuit surface 1a side of the semiconductor element 1 is fixed onto the element mounting portion 3a of the base film 3 with an adhesive or the like. Next, in (C), the conductor lead 4 and the electrode portion of the semiconductor element 1 are bonded via the bump 5, and the conductor lead 4 is molded. And (D)
In (C), the processed product is molded with molds 7a and 7b.
Hold in. At this time, the lead holding portion 3b and the lead tip portion 4b are held by the molds 7a and 7b. Resin sealing is performed in this state to complete the semiconductor device of FIG.
【００２３】この図１の半導体装置を基板等に実装する
際には、樹脂モールド６の下面６ａに露出するリード先
端部４ｂが接合される。このリード先端部４ｂは、短く
変形なく樹脂モールド６の下面６ａに固定配列されてい
ると共に、端面の酸化やバリ等がないので、高精度で確
実な接合を行うことができる。When the semiconductor device of FIG. 1 is mounted on a substrate or the like, the lead tips 4b exposed on the lower surface 6a of the resin mold 6 are joined. The lead tip portion 4b is fixedly arranged on the lower surface 6a of the resin mold 6 without being deformed in a short manner, and since there is no oxidation or burrs on the end surface, highly accurate and reliable joining can be performed.
【００２４】次に、図６は別の実施例における半導体装
置の断面図であり、半導体素子１の裏面に放熱板８を接
着し、この放熱板８を樹脂モールド６の表面に露出させ
ることによって、放熱性を高めたものである。Next, FIG. 6 is a cross-sectional view of a semiconductor device according to another embodiment. A heat sink 8 is adhered to the back surface of the semiconductor element 1 and the heat sink 8 is exposed on the surface of the resin mold 6. , With improved heat dissipation.
【００２５】以上、本発明の実施例について説明した
が、本発明は上記実施例に限定されることなく、本発明
の技術的思想に基づいて各種の有効な変更並びに応用が
可能である。例えば、実施例では樹脂モールドの２辺か
らリード先端部が露出するタイプを示したが、１辺のみ
もしくは３辺以上でも同等の効果が得られる。Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various effective modifications and applications are possible based on the technical idea of the present invention. For example, in the embodiment, the lead end portions are exposed from the two sides of the resin mold, but the same effect can be obtained with only one side or with three or more sides.
【００２６】[0026]
【発明の効果】以上説明したように、本発明によれば、
小型薄型化を図ることができると共に、外部リードが短
く樹脂部の下面に固定されているためリード変形がな
く、しかも外部リードは切断面がないため酸化し難くバ
リの発生等もない。従って、基板等への実装時に極めて
良好な接合を行うことができる。さらに、外部リードの
切断が不要なので、特性試験や出荷等を連続したテープ
形態のフィルムキャリアで行え、工数及び材料等を簡略
化することができる。As described above, according to the present invention,
The external lead is short and is fixed to the lower surface of the resin portion so that the lead is not deformed. Moreover, since the external lead has no cut surface, it is difficult to oxidize and burrs do not occur. Therefore, extremely good bonding can be performed when mounting on a substrate or the like. Further, since it is not necessary to cut the external leads, the characteristic test and shipping can be performed with the continuous tape-shaped film carrier, and the man-hours and materials can be simplified.
【図１】本発明の実施例における半導体装置の断面図で
ある。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.
【図２】上記実施例における半導体装置の（Ａ）は上面
図、（Ｂ）は裏面図である。FIG. 2A is a top view and FIG. 2B is a back view of the semiconductor device in the above embodiment.
【図３】上記実施例におけるフィルムキャリアの構成を
示す平面図である。FIG. 3 is a plan view showing a configuration of a film carrier in the above embodiment.
【図４】別の実施例におけるフィルムキャリアの構成を
示す平面図である。FIG. 4 is a plan view showing the structure of a film carrier according to another embodiment.
【図５】上記実施例における半導体装置の組立工程を示
す断面図である。FIG. 5 is a cross-sectional view showing the assembly process of the semiconductor device in the above-mentioned embodiment.
【図６】別の実施例における放熱板付きの半導体装置の
断面図である。FIG. 6 is a cross-sectional view of a semiconductor device with a heat sink according to another embodiment.
【図７】従来のリードフレームを用いた半導体装置の断
面図である。FIG. 7 is a sectional view of a semiconductor device using a conventional lead frame.
【図８】従来のＴＡＢ方式による半導体装置の断面図で
ある。FIG. 8 is a cross-sectional view of a conventional TAB semiconductor device.
１ 半導体素子 １ａ 回路面 ２ フィルムキャリア ３ ベースフィルム ３ａ 素子搭載部 ３ｂ リード保持部 ４ 導体リード ４ａ 内端部 ４ｂ 先端部 ５ バンプ ６ 樹脂モールド ６ａ 下面 ７ａ、７ｂ モールド金型 ８ 放熱板 DESCRIPTION OF SYMBOLS 1 Semiconductor element 1a Circuit surface 2 Film carrier 3 Base film 3a Element mounting part 3b Lead holding part 4 Conductor lead 4a Inner end part 4b Tip part 5 Bump 6 Resin mold 6a Lower surface 7a, 7b Mold die 8 Heat sink
Claims (4)
縁性ベースフィルム上に形成してなるフィルムキャリア
において、 前記ベースフィルムが、前記半導体素子を配置する素子
搭載部と前記導体リードを保持するリード保持部とを有
し、前記半導体素子の電極部に接続される前記導体リー
ドの両端部が、それぞれ前記ベースフィルムの素子搭載
部とリード保持部とによって支持されていることを特徴
とするフィルムキャリア。1. A film carrier having conductor leads connected to a semiconductor element formed on an insulating base film, wherein the base film holds an element mounting portion on which the semiconductor element is arranged and the conductor lead. A film carrier having a holding portion, wherein both ends of the conductor lead connected to the electrode portion of the semiconductor element are supported by the element mounting portion and the lead holding portion of the base film, respectively. .
のフィルムキャリアに搭載される半導体素子とからな
り、 前記ベースフィルムの素子搭載部上に前記半導体素子の
回路面側が搭載されており、前記ベースフィルムの素子
搭載部とリード保持部とによって支持された前記導体リ
ードの両端部間の一部が前記半導体素子の電極部に接続
されていることを特徴とする半導体装置。2. The film carrier according to claim 1, and a semiconductor element mounted on the film carrier, wherein a circuit surface side of the semiconductor element is mounted on an element mounting portion of the base film, A semiconductor device, wherein a part between both ends of the conductor lead supported by an element mounting portion and a lead holding portion of the film is connected to an electrode portion of the semiconductor element.
記半導体素子及び前記フィルムキャリアが樹脂によって
封止され、前記ベースフィルムのリード保持部によって
保持された前記導体リードの先端部が樹脂部の下面から
露出してその下面に固定されていることを特徴とする半
導体装置。3. The semiconductor device according to claim 2, wherein the semiconductor element and the film carrier are sealed with resin, and the tip end of the conductor lead held by the lead holding portion of the base film is a lower surface of the resin portion. A semiconductor device, which is exposed from and fixed to the lower surface thereof.
記導体リードの全面がメッキにより被覆されていること
を特徴とする半導体装置。4. The semiconductor device according to claim 2, wherein the entire surface of the conductor lead is covered by plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5352989A JPH07201928A (en) | 1993-12-29 | 1993-12-29 | Film carrier and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5352989A JPH07201928A (en) | 1993-12-29 | 1993-12-29 | Film carrier and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07201928A true JPH07201928A (en) | 1995-08-04 |
Family
ID=18427819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5352989A Withdrawn JPH07201928A (en) | 1993-12-29 | 1993-12-29 | Film carrier and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07201928A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0883174A2 (en) * | 1997-06-04 | 1998-12-09 | Fujitsu Limited | Semiconductor device and semiconductor device module |
| US5926062A (en) * | 1997-06-23 | 1999-07-20 | Nec Corporation | Reference voltage generating circuit |
| US6084310A (en) * | 1997-04-21 | 2000-07-04 | Nec Corporation | Semiconductor device, lead frame, and lead bonding |
| JP2009514250A (en) * | 2005-11-01 | 2009-04-02 | アレグロ・マイクロシステムズ・インコーポレーテッド | Flip chip on lead semiconductor package method and apparatus |
-
1993
- 1993-12-29 JP JP5352989A patent/JPH07201928A/en not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6084310A (en) * | 1997-04-21 | 2000-07-04 | Nec Corporation | Semiconductor device, lead frame, and lead bonding |
| EP0883174A2 (en) * | 1997-06-04 | 1998-12-09 | Fujitsu Limited | Semiconductor device and semiconductor device module |
| EP0883174A3 (en) * | 1997-06-04 | 2000-04-19 | Fujitsu Limited | Semiconductor device and semiconductor device module |
| US6094356A (en) * | 1997-06-04 | 2000-07-25 | Fujitsu Limited | Semiconductor device and semiconductor device module |
| US5926062A (en) * | 1997-06-23 | 1999-07-20 | Nec Corporation | Reference voltage generating circuit |
| JP2009514250A (en) * | 2005-11-01 | 2009-04-02 | アレグロ・マイクロシステムズ・インコーポレーテッド | Flip chip on lead semiconductor package method and apparatus |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
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