JPH11204525A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH11204525A
JPH11204525A JP601698A JP601698A JPH11204525A JP H11204525 A JPH11204525 A JP H11204525A JP 601698 A JP601698 A JP 601698A JP 601698 A JP601698 A JP 601698A JP H11204525 A JPH11204525 A JP H11204525A
Authority
JP
Japan
Prior art keywords
pad
semiconductor substrate
semiconductor device
teg
metal wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP601698A
Other languages
Japanese (ja)
Inventor
Kazuo Koga
和雄 古賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP601698A priority Critical patent/JPH11204525A/en
Publication of JPH11204525A publication Critical patent/JPH11204525A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48095Kinked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dicing (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent the turning-up of metals and the formation of burrs, when dicing ie performed for a semiconductor substrate by etching the metal wiring exposed from the opening of a protecting insulation film at the part of the metal wiring pad from the circuit of a monitoring transistor formed in a scribing region. SOLUTION: When a monitoring transistor (TEG) is formed in a scribing region 105, it is necessary to open a hole in a protective insulation film at a pad part 101 of the TEG for measuring the electrical characteristics of a semiconductor device formed on a semiconductor substrate. That is to say, the part, which is exposed from the opening 102 of the protecting insulation film of the pad of the TSG formed on the scribing region 105 on the semiconductor substrate, is removed by etching. In this way, the problem of the occurrence of the burrs at dicing time can be ressolved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置の製造方
法、特にスクライブ領域の構造に関する。
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a structure of a scribe region.

【0002】[0002]

【従来の技術】半導体装置のスクライブ領域の構造には
従来から特開平01−186652号公報のように図3
に示すようなスクライブ領域に形成されるモニタートラ
ンジスタ(以下「TEG」と呼ぶ)の回路からの引き出
し電極を形成する金属配線パッド部分(以下「パッド」
と呼ぶ)にスリットを形成したり、特開昭62−299
08のように図3に示すようなTEGのパッド部分の保
護絶縁膜を開口しないような構造が用いられている。
2. Description of the Related Art Conventionally, the structure of a scribe region of a semiconductor device has been disclosed in Japanese Patent Application Laid-Open No. 01-186652.
A metal wiring pad portion (hereinafter, “pad”) that forms an extraction electrode from a circuit of a monitor transistor (hereinafter, referred to as “TEG”) formed in a scribe region as shown in FIG.
To form a slit,
As shown in FIG. 8, a structure is used in which the protective insulating film in the pad portion of the TEG is not opened as shown in FIG.

【0003】[0003]

【発明が解決しようとする課題】従来、図4に示すよう
に半導体基板上のスクライブ領域上で保護絶縁膜が開口
され金属が露出した部分では、半導体基板をダイシング
する際に金属がめくれ上がってバリとなり、ボンディン
グワイヤーや実装のためのリードと短絡し電気的な不良
を発生させることが起きる。本発明の目的は半導体基板
をダイシングする際に金属がめくれ上がってバリとなる
ことのないスクライブ領域の構造を実現することにあ
る。
Conventionally, as shown in FIG. 4, in a portion where a protective insulating film is opened on a scribe region on a semiconductor substrate and the metal is exposed, the metal is turned up when dicing the semiconductor substrate. Burrs may occur and short-circuit with bonding wires or mounting leads to cause electrical failure. SUMMARY OF THE INVENTION It is an object of the present invention to realize a structure of a scribe region in which metal does not turn up when dicing a semiconductor substrate and does not become burrs.

【0004】[0004]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明の半導体装置の製造方法は、半導体基板上
のスクライブ領域に形成されるモニタートランジスタの
回路からの引き出し電極を形成する金属配線パッドの部
分の保護絶縁膜の開口から露出する金属配線をエッチン
グすることを特徴とする。
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is directed to a method of forming a metal electrode for forming an extraction electrode from a circuit of a monitor transistor formed in a scribe region on a semiconductor substrate. The metal wiring exposed from the opening of the protective insulating film at the wiring pad portion is etched.

【0005】[0005]

【作用】以上説明した本発明の半導体装置の製造方法に
よれば、半導体基板上のスクライブ領域に形成されるT
EGのパッドの保護絶縁膜の開口から露出する部分をエ
ッチングで取り除くことによって、半導体基板をダイシ
ングする際に金属がめくれ上がってバリとなることのな
いスクライブ領域の構造を実現することができる。
According to the method of manufacturing a semiconductor device of the present invention described above, the T formed in the scribe region on the semiconductor substrate is reduced.
By removing the portion of the EG pad exposed from the opening of the protective insulating film by etching, it is possible to realize a structure of a scribe region in which metal does not turn up to form burrs when dicing the semiconductor substrate.

【0006】[0006]

【発明の実施の形態】本発明の半導体装置の製造方法の
一実施例について図面を参照にして説明する。図1にお
いて101はTEGの金属配線パッド、102はTEG
のパッド部の保護絶縁膜の開口、103は実素子の金属
配線パッド、104は実素子のパッド部の保護絶縁膜の
開口、105はスクライブ領域を示す。スクライブ領域
にTEGを形成する場合、半導体基板上に形成された半
導体装置の電気的特性を測定するためにTEGのパッド
部分の保護絶縁膜を開口することが必要になる。これに
よって図4に示す従来例のようにスクライブ領域で保護
絶縁膜から露出した金属401のように半導体基板のダ
イシング時に切り口に沿ってめくれ上がり、ボンディン
グワイヤーや実装のためのリード407と短絡し電気的
な不良の原因となる。この対策として図3に示す従来例
のようにパッド301にスリット306を入れることが
行われることがあるが、実装のために実素子領域のパッ
ド上にバンプを形成する場合には本来バンプが形成され
てはならないスクライブ領域にメッキが成長するという
問題を引き起こす。これはバンプ形成のメッキを行う際
に本来バンプが形成されてはならないスクライブ領域は
レジストで覆われていなければならないが、レジストの
粘度が高いためにスリット306にレジストが入り込ま
ず気泡を形成することになり、その気泡がベークの際に
はじけてレジストに欠陥を生じるためである。このよう
な問題のために実装のために実素子領域のパッド上にバ
ンプを形成する場合のスクライブ領域のTEGのパッド
にはスリット306を入れることができない。この場
合、図2に示すようにスクライブ領域のTEGのパッド
が露出しないような構造をとればダイシング時のバリ発
生の問題は起こらないが、半導体基板上に形成された半
導体装置の電気的特性を測定するために最低限必要な数
のTEGについてはパッド部分の保護絶縁膜を開口する
ことが必要になり、この部分ではダイシング時のバリ発
生の問題が避けられない。これに対して本発明では図1
のように半導体基板上に形成された半導体装置の電気的
特性を測定するために保護絶縁膜を開口した部分102
のTEGのパッド金属101をエッチングすることによ
ってダイシング時のバリ発生の問題を解決することが可
能となる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. In FIG. 1, 101 is a metal wiring pad of TEG, and 102 is TEG.
Reference numeral 103 denotes a metal wiring pad of a real element, 104 denotes an opening of the protective insulating film of a pad part of the real element, and 105 denotes a scribe region. When forming a TEG in a scribe region, it is necessary to open a protective insulating film in a pad portion of the TEG in order to measure electrical characteristics of a semiconductor device formed on a semiconductor substrate. Thus, as in the conventional example shown in FIG. 4, the metal 401 exposed from the protective insulating film in the scribe region is turned up along the cut when dicing the semiconductor substrate, and short-circuited with the bonding wire or the lead 407 for mounting, and Cause serious failure. As a countermeasure, a slit 306 may be formed in the pad 301 as in the conventional example shown in FIG. 3, but when a bump is formed on the pad in the actual element area for mounting, the bump is not formed. This causes a problem that plating grows in the scribe area that should not be done. This means that the scribe area where bumps should not be formed when plating for bump formation must be covered with resist, but because the viscosity of the resist is high, the resist does not enter the slit 306 and bubbles are formed. This is because the bubbles pop out during baking to cause defects in the resist. Due to such a problem, a slit 306 cannot be formed in a TEG pad in a scribe area when a bump is formed on a pad in an actual element area for mounting. In this case, as shown in FIG. 2, if the structure of the TEG pad in the scribe area is not exposed, the problem of burr generation at the time of dicing does not occur, but the electrical characteristics of the semiconductor device formed on the semiconductor substrate are reduced. For the minimum number of TEGs required for measurement, it is necessary to open the protective insulating film in the pad portion, and in this portion, the problem of burrs during dicing is inevitable. In contrast, in the present invention, FIG.
Of a semiconductor device formed on a semiconductor substrate as shown in FIG.
By etching the TEG pad metal 101, the problem of burr generation at the time of dicing can be solved.

【0007】[0007]

【発明の効果】以上説明した本発明の半導体装置の製造
方法によれば、半導体基板をダイシングする際にスクラ
イブ領域上で金属がめくれ上がってバリとなり、ボンデ
ィングワイヤーや実装のためのリードと短絡して電気的
な不良を発生させることを防止することができるもので
ある。
According to the method of manufacturing a semiconductor device of the present invention described above, when dicing a semiconductor substrate, the metal is turned up on the scribe region and becomes a burr, and short-circuits with a bonding wire or a lead for mounting. Thus, it is possible to prevent the occurrence of electrical failure.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置の一実施例を示す断面図。FIG. 1 is a sectional view showing one embodiment of a semiconductor device of the present invention.

【図2】従来の半導体装置の実施例を示す断面図。FIG. 2 is a sectional view showing an example of a conventional semiconductor device.

【図3】従来の半導体装置の実施例を示す平面図。FIG. 3 is a plan view showing an embodiment of a conventional semiconductor device.

【図4】従来の半導体装置の実施例を示す断面図。FIG. 4 is a sectional view showing an embodiment of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

101、201、301、401 TEGの金属配線パ
ッド 102 TEGのパッド部の保護絶縁膜の開口 103、203、403 実素子の金属配線パッド 104、204 実素子のパッド部の保護絶縁膜の開口 105、205、305、405 スクライブ領域 306 パッド部のスリット 407 ボンディングワイヤー
101, 201, 301, 401 Metal wiring pad of TEG 102 Opening of protective insulating film in pad section of TEG 103, 203, 403 Metal wiring pad 104 of real element 104, 204 Opening of protective insulating film in pad section of real element 105, 205, 305, 405 Scribe area 306 Pad slit 407 Bonding wire

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上のスクライブ領域に形成され
るモニタートランジスタの回路からの引き出し電極を形
成する金属配線パッドの部分の保護絶縁膜の開口から露
出する金属配線をエッチングすることを特徴とする半導
体装置の製造方法。
1. A metal wiring exposed from an opening of a protective insulating film in a portion of a metal wiring pad forming a lead electrode from a circuit of a monitor transistor formed in a scribe region on a semiconductor substrate. A method for manufacturing a semiconductor device.
JP601698A 1998-01-14 1998-01-14 Manufacture of semiconductor device Withdrawn JPH11204525A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP601698A JPH11204525A (en) 1998-01-14 1998-01-14 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP601698A JPH11204525A (en) 1998-01-14 1998-01-14 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH11204525A true JPH11204525A (en) 1999-07-30

Family

ID=11626911

Family Applications (1)

Application Number Title Priority Date Filing Date
JP601698A Withdrawn JPH11204525A (en) 1998-01-14 1998-01-14 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH11204525A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6426556B1 (en) * 2001-01-16 2002-07-30 Megic Corporation Reliable metal bumps on top of I/O pads with test probe marks
US6511897B2 (en) 2001-02-13 2003-01-28 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device as well as reticle and wafer used therein
JP2006516824A (en) * 2003-01-27 2006-07-06 フリースケール セミコンダクター インコーポレイテッド Metal reduction in wafer scribe area
KR100699384B1 (en) 2004-09-29 2007-03-26 산요덴키가부시키가이샤 Semiconductor device and manufacturing method thereof
US8901733B2 (en) 2001-02-15 2014-12-02 Qualcomm Incorporated Reliable metal bumps on top of I/O pads after removal of test probe marks

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6426556B1 (en) * 2001-01-16 2002-07-30 Megic Corporation Reliable metal bumps on top of I/O pads with test probe marks
US6511897B2 (en) 2001-02-13 2003-01-28 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device as well as reticle and wafer used therein
US8901733B2 (en) 2001-02-15 2014-12-02 Qualcomm Incorporated Reliable metal bumps on top of I/O pads after removal of test probe marks
JP2006516824A (en) * 2003-01-27 2006-07-06 フリースケール セミコンダクター インコーポレイテッド Metal reduction in wafer scribe area
KR100699384B1 (en) 2004-09-29 2007-03-26 산요덴키가부시키가이샤 Semiconductor device and manufacturing method thereof
US7256420B2 (en) 2004-09-29 2007-08-14 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US7820548B2 (en) 2004-09-29 2010-10-26 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20050405