JPH10173015A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the chip area of a semiconductor device and to reduce the size of the chip. SOLUTION: A plurality of chip regions 5 separated by scribe lines 6 are provided on a wafer, and a desired circuit 1 and wire bonding pads 2 for connecting the signal lines 7 of the desired circuit 1 with a lead frame are formed in each chip region 5, and probe inspecting pads 3 to be used only at the time of probe inspection are formed in the scribe lines 6. After probe inspection is performed in this state of the wafer, cutting at the scribe lines 6 is performed to divide it into chips. Since the probe inspecting pads 3 in the scribe lines are cut off on the occasion of this dividing, the divided chips do not need areas corresponding to the probe inspecting pads 3 cut off, so it becomes possible to reduce each chip area and to reduce the size of the chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art A conventional semiconductor device will be described with reference to FIG. FIG. 2A is a plan view showing a state before chip division in a conventional semiconductor device, and FIG. 2B is a plan view showing a state after chip division in a conventional semiconductor device. In FIG. 2, reference numeral 21 denotes a desired circuit, and reference numeral 22 denotes a signal line 27 of the desired circuit 21 by a lead frame (not shown).
, A probe inspection pad 23, a probe inspection wiring 24 made of aluminum for connecting a desired circuit 21 and the probe inspection pad 23, a chip area 25, a scribe line 26 Line.

FIG. 2A shows a state of a conventional semiconductor device before chip division, as shown in FIG.
A plurality of chip regions 25 separated by scribe lines 26 are provided on each of the chip regions 25. In each chip region 25, a desired circuit 21 and a wire bonding pad for connecting a signal line 27 of the desired circuit 21 to a lead frame are provided. 22
And probe inspection pad 2 used only during probe inspection
3 are formed. In this wafer state, the probe is brought into contact with the wire bonding pad 22 and the probe inspection pad 23 to measure the electrical characteristics of the desired circuit 21. After performing the probe test, the probe is cut along the scribe line 26 and divided into chips shown in FIG.

[0004]

In the above-mentioned conventional configuration,
Probe inspection pad 2 not required after probe inspection
Since 3 is formed in the chip region 25, the chip region 25 becomes large, the chip area after division is large, and it has been difficult to reduce the size of the chip. An object of the present invention is to provide a semiconductor device capable of reducing a chip area and a chip size, and a method of manufacturing the same.

[0005]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a desired circuit formed in a plurality of chip regions separated by scribe lines on a semiconductor substrate; A probe inspection pad connected to a desired circuit and wiring is provided. According to this configuration, since the probe inspection pad is provided in the scribe line, the probe inspection pad is separated when the chip is divided at the scribe line, and the separated chip is used for the separated probe inspection pad. Since the pad area is not required, the chip area can be reduced, and the chip can be downsized.

A semiconductor device according to a second aspect of the present invention is a semiconductor device in which a desired circuit is formed on a semiconductor substrate and divided into chips, and a wiring for probe inspection connected to the desired circuit is connected to the desired circuit and the chip. It is characterized by remaining between the end face. According to this configuration, the probe test wiring remains between the desired circuit and the chip end face, and the probe test pad connected to the probe test wiring is cut off when divided into chips. I have. In this manner, the chip does not require the separated area of the probe inspection pad, so that the chip area can be reduced and the chip can be reduced in size.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the wiring is made of polysilicon, a high melting point metal or a high melting point metal alloy. This wiring connects the desired circuit and the probe inspection pad. When divided into chips, the wiring is exposed on the chip end surface, which is a cut surface of the chip, but it is made of polysilicon, high melting point metal or high melting point metal alloy. Accordingly, corrosion of wiring due to intrusion of moisture or the like from the outside can be prevented, and a decrease in reliability of the semiconductor device can be prevented.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
A desired circuit is formed in a plurality of chip regions separated by a scribe line on a semiconductor substrate, and a probe test pad connected to a desired circuit in the chip region by wiring is formed in the scribe line, thereby performing a probe test. After that, cutting is performed at a scribe line to divide the probe inspection pad into chips separated from each other.

According to this manufacturing method, the probe inspection pad is formed in the scribe line, the probe inspection is performed, and then the probe inspection pad is cut along the scribe line to divide the probe inspection pad into the separated chips. The separated chip does not require the separated area of the probe inspection pad, so that the chip area can be reduced and the chip can be reduced in size.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
According to a fourth aspect of the present invention, the wiring connecting the desired circuit and the probe inspection pad is formed of polysilicon, a high melting point metal or a high melting point metal alloy. As described above, by forming the wiring connecting the desired circuit and the probe inspection pad with polysilicon, a high melting point metal or a high melting point metal alloy, moisture from the outside of the wiring exposed on the divided chip end surface can be reduced. Corrosion due to intrusion or the like can be prevented, and a decrease in the reliability of the semiconductor device can be prevented.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. FIG. 1A is a plan view showing a state of the semiconductor device according to the embodiment of the present invention before chip division, and FIG. 1B is a plan view showing a state of the semiconductor device after chip division according to the embodiment of the present invention. FIG.
In FIG. 1, reference numeral 1 denotes a desired circuit, 2 denotes a wire bonding pad for connecting the signal line 7 of the desired circuit 1 to a lead frame (not shown), 3 denotes a probe inspection pad, and 4 denotes a desired circuit. A probe inspection wiring made of polysilicon, a high melting point metal or a high melting point metal alloy for connecting 1 to the probe inspection pad 3, 5 is a chip area, and 6 is a scribe line.

In the state of the semiconductor device according to this embodiment before chip division, as shown in FIG. 1A, a plurality of chip regions 5 separated by scribe lines 6 are provided on a wafer (semiconductor substrate). In each chip area 5, a desired circuit 1 and a wire bonding pad 2 for connecting a signal line 7 of the desired circuit 1 to a lead frame are formed, and a probe test is performed in a scribe line 6. The probe inspection pad 3 used only at the time is formed. In the state of the wafer, a probe is brought into contact with the wire bonding pad 2 and the probe inspection pad 3 to perform a probe inspection for measuring an electrical characteristic of a desired circuit 1.

After performing the probe inspection, the wafer is cut along the scribe line 6 and divided into chips. At this time, the probe inspection pad 3 is cut off, and after the chip is divided, as shown in FIG. 1B. As described above, the probe test wiring 4 only remains between the desired circuit 1 and the chip end surface (cut surface) 8, but the probe test pad 3 does not exist on the chip.

As described above, according to this embodiment, since the probe inspection pads 3 are provided in the scribe lines 6, the probe inspection pads 3 are separated when the chips are divided at the scribe lines 6. Therefore, the divided chip does not require the separated area of the probe test pad 3, so that the chip area is reduced.
The size of the chip can be reduced.

In this embodiment, all the probe inspection pads 3 are formed in the scribe line 6, but even if some of the probe inspection pads 3 are formed in the scribe line 6, only a portion corresponding thereto is formed. It goes without saying that the chip area can be reduced and the chip can be downsized.
Further, by forming the wiring 4 for probe inspection with polysilicon, a high melting point metal or a high melting point metal alloy, it is possible to prevent corrosion due to invasion of moisture from the outside of the wiring 4 exposed on the divided chip end face 8. In addition, it is possible to prevent a decrease in the reliability of the semiconductor device.

[0016]

As described above, according to the present invention, since the probe test pads are provided in the scribe line, the probe test pads are separated when the chips are divided along the scribe line, and the divided chips are separated. Since the area of the separated probe inspection pad is not required, the chip area can be reduced and the chip can be downsized.

Further, by forming the wiring for the probe inspection with polysilicon, a high melting point metal or a high melting point metal alloy, it is possible to prevent corrosion due to invasion of moisture from the outside of the wiring exposed on the divided chip end faces. In addition, it is possible to prevent a decrease in the reliability of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a plan view showing a state before and after chip division of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view showing a state of a conventional semiconductor device before and after chip division.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Desired circuit 2 Pad for wire bonding 3 Pad for probe inspection 4 Wiring for probe inspection 5 Chip area 6 Scribe line 7 Signal line of desired circuit 8 Chip end face

Claims (5)

[Claims] 1. A probe test formed in a plurality of chip regions separated by scribe lines on a semiconductor substrate and a probe test formed in the scribe lines and connected to the desired circuits in the chip regions by wiring. Semiconductor device provided with a pad for use. 2. A semiconductor device in which a desired circuit is formed on a semiconductor substrate and divided into chips, wherein a wiring for probe inspection connected to the desired circuit is provided between the desired circuit and the chip end surface. A semiconductor device characterized by remaining in a semiconductor device. 3. The semiconductor device according to claim 1, wherein the wiring is made of polysilicon, a refractory metal or a refractory metal alloy. 4. A method for forming a desired circuit in a plurality of chip areas separated by scribe lines on a semiconductor substrate, and connecting a probe test pad connected to the desired circuit in the chip area by wiring to the scribe line. A method of manufacturing a semiconductor device, comprising: forming in a line, performing a probe test, and cutting along the scribe line to divide the probe test pad into separated chips. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the wiring connecting the desired circuit and the pad for probe inspection is formed of polysilicon, a high melting point metal or a high melting point metal alloy.