JP2003347482A - Semiconductor package, method for manufacturing semiconductor package and method for inspecting semiconductor package - Google Patents
Semiconductor package, method for manufacturing semiconductor package and method for inspecting semiconductor packageInfo
- Publication number
- JP2003347482A JP2003347482A JP2002153922A JP2002153922A JP2003347482A JP 2003347482 A JP2003347482 A JP 2003347482A JP 2002153922 A JP2002153922 A JP 2002153922A JP 2002153922 A JP2002153922 A JP 2002153922A JP 2003347482 A JP2003347482 A JP 2003347482A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- inspection
- mounting
- electrode
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73227—Wire and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92162—Sequential connecting processes the first connecting process involving a wire connector
- H01L2224/92164—Sequential connecting processes the first connecting process involving a wire connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体パッケージ、
半導体パッケージの製造方法及び半導体パッケージの検
査方法に関し、詳しくはパッケージ構造を問わず検査パ
ッド数が増加でき、電気的検査が容易で検査時間の短縮
ができる半導体パッケージ、半導体パッケージの製造方
法及び半導体パッケージの検査方法に関する。The present invention relates to a semiconductor package,
More specifically, the present invention relates to a method of manufacturing a semiconductor package and a method of inspecting a semiconductor package. More specifically, the number of test pads can be increased irrespective of the package structure. The inspection method.
【０００２】[0002]
【従来の技術】従来、モールド、ポッティング又は印刷
等により封止された半導体パッケージの検査方法は、封
じ面と反対側又は封じ面の側面に外部接続端子を設けて
電気的検査を行っているため、検査用ソケット側が半導
体のファインピッチ化が進むにしたがって製作困難とな
るため、半導体検査のコスト高になる問題があった。2. Description of the Related Art Conventionally, a method for inspecting a semiconductor package sealed by molding, potting, printing, or the like, is such that an external connection terminal is provided on the side opposite to the sealing surface or on the side surface of the sealing surface to perform electrical inspection. In addition, there is a problem that the cost of the semiconductor inspection increases because the inspection socket side becomes difficult to manufacture as the fine pitch of the semiconductor advances.
【０００３】また、特開平９-２２９２９号公報には、
電気的特性検査のためのテストパッドを半導体チップが
マウントされる基板上の半田ボール形成面と反対側に設
けたＢＧＡタイプの半導体パッケージが記載されてい
る。しかし、かかる構成の半導体パッケージは、半田ボ
ールを傷つけずに検査することができるが、ＢＧＡタイ
プでしか構成できず、その検査装置もＢＧＡタイプとは
別の検査装置を用いなければならなかった。また、電気
的検査をするためには、半田ボール掲載面と反対側に設
けたテストパッドしか用いることができず、検査時間の
短縮はできなかった。[0003] Also, Japanese Patent Application Laid-Open No. 9-22929 discloses that
A BGA type semiconductor package in which test pads for electrical characteristic inspection are provided on a side opposite to a solder ball forming surface on a substrate on which a semiconductor chip is mounted is described. However, the semiconductor package having such a configuration can be inspected without damaging the solder balls, but can be configured only of the BGA type, and the inspection apparatus must use an inspection apparatus different from the BGA type. Further, in order to perform an electrical inspection, only a test pad provided on the side opposite to the solder ball mounting surface can be used, and the inspection time cannot be reduced.
【０００４】[0004]
【発明が解決しようとする課題】そこで本発明の課題
は、ＤＩＰ、ＱＦＰ、ＢＧＡ等のパッケージ構造の種類
を問わず検査パッド数が増加でき、電気的検査が容易
で、検査時間の短縮ができる半導体パッケージ、半導体
パッケージの製造方法及び半導体パッケージの検査方法
を提供することにある。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to increase the number of test pads regardless of the type of package structure, such as DIP, QFP, BGA, etc., to facilitate electrical testing, and to reduce testing time. An object of the present invention is to provide a semiconductor package, a method of manufacturing a semiconductor package, and a method of inspecting a semiconductor package.
【０００５】本発明の他の課題は、以下の記載によって
明らかになる。[0005] Other objects of the present invention will become apparent from the following description.
【０００６】[0006]
【課題を解決するための手段】上記課題は、以下の各発
明によって解決される。The above objects can be attained by the following inventions.
【０００７】（請求項１）半導体チップを封止した半導
体パッケージにおいて、実装用端子と反対側の封止面側
に電気的検査を行える検査パッドを有することを特徴と
する半導体パッケージ。(1) A semiconductor package in which a semiconductor chip is sealed, the semiconductor package having an inspection pad for performing an electrical inspection on a sealing surface side opposite to a mounting terminal.
【０００８】（請求項２）前記半導体チップは検査用電
極と実装用電極とを有し、前記検査用電極は、前記検査
パッドと導通可能とされ、前記実装用電極は、前記実装
用端子と導通可能とされていることを特徴とする請求項
１記載の半導体パッケージ。(Claim 2) The semiconductor chip has an inspection electrode and a mounting electrode, wherein the inspection electrode is made conductive with the inspection pad, and the mounting electrode is connected to the mounting terminal. 2. The semiconductor package according to claim 1, wherein the semiconductor package is made conductive.
【０００９】（請求項３）実装用端子を有する基板上に
検査用電極と実装用電極を備えた半導体チップを載置す
る工程と、金属バンプを検査用電極に導通可能に設ける
と共に、実装用電極と実装用端子とを導通可能に接続す
る工程と、半導体チップを固定するための樹脂封じを行
う工程と、金属バンプの露出工程と、金属バンプと検査
パッドを導通する金属パターンを形成する工程とを有す
ることを特徴とする半導体パッケージの製造方法。(Claim 3) A step of mounting a semiconductor chip having an electrode for inspection and a mounting electrode on a substrate having terminals for mounting, and providing a metal bump to the electrode for inspection so as to be electrically conductive, A step of connecting the electrodes and the mounting terminals in a conductive manner, a step of sealing the resin for fixing the semiconductor chip, a step of exposing the metal bumps, and a step of forming a metal pattern for conducting the metal bumps and the test pads And a method for manufacturing a semiconductor package.
【００１０】（請求項４）前記樹脂封じを行う工程にお
いて、金属バンプの部分を漏斗状の傾斜面を有する凹部
とすることを特徴とする請求項３記載の半導体パッケー
ジの製造方法。(4) The method of manufacturing a semiconductor package according to (3), wherein in the step of sealing the resin, a portion of the metal bump is formed as a concave portion having a funnel-shaped inclined surface.
【００１１】（請求項５）請求項１〜２に記載の半導体
パッケージを検査する方法であって、半導体パッケージ
の実装面側と反対面側の両方から検査用の信号を送受す
ることを特徴とする半導体パッケージの検査方法。(Claim 5) A method for inspecting a semiconductor package according to any one of claims 1 to 2, wherein signals for inspection are transmitted and received from both the mounting surface side and the opposite surface side of the semiconductor package. Semiconductor package inspection method.
【００１２】[0012]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１３】初めに、半導体パッケージの製造方法の一
例について、図面に基づいて説明する。First, an example of a method for manufacturing a semiconductor package will be described with reference to the drawings.
【００１４】最初に、基板１上の中央に半導体チップ２
を載置している。First, a semiconductor chip 2 is provided at the center on a substrate 1.
Is placed.
【００１５】基板１の上面には、上部端子１００を備
え、基板１の下面には、実装用端子１０１を備えてお
り、上部端子１００と実装用端子１０１は導通可能に接
続されている。尚、上部端子１００と実装用端子１０１
は基板１に埋設されていても良い。半導体チップ２は、
半導体ウェハをダイシングして、個片に分離して得られ
る。係る半導体チップ２の表面には、電極が設けられて
おり、その電極は、半導体チップの中心近傍に、一列あ
るいは複数列に並んだ態様や、半導体チップ２の外周粋
に沿って、配置された態様等のいずれでもよい。本実施
の対応では、後者を採用している。好ましい半導体チッ
プの一例を図２に示す。図２において、２００は複数の
電極部であり、各電極部２００、２００，２００・・・
は、検査用電極２００ａと実装用電極２００ｂに機能分
離されている。実装用電極２００ｂは、ボンディングワ
イヤ１０２を介して、上部端子１００と導通可能に接続
されている。An upper terminal 100 is provided on the upper surface of the substrate 1, and a mounting terminal 101 is provided on the lower surface of the substrate 1. The upper terminal 100 and the mounting terminal 101 are connected to be conductive. The upper terminal 100 and the mounting terminal 101
May be embedded in the substrate 1. The semiconductor chip 2
A semiconductor wafer is obtained by dicing and separating into individual pieces. Electrodes are provided on the surface of the semiconductor chip 2, and the electrodes are arranged in the vicinity of the center of the semiconductor chip in one or more rows or along the outer periphery of the semiconductor chip 2. Any of the embodiments and the like may be used. In the present embodiment, the latter is adopted. FIG. 2 shows an example of a preferable semiconductor chip. In FIG. 2, reference numeral 200 denotes a plurality of electrode units, and each of the electrode units 200, 200, 200,.
Are functionally separated into an inspection electrode 200a and a mounting electrode 200b. The mounting electrode 200b is electrically connected to the upper terminal 100 via the bonding wire 102.
【００１６】半導体チップ２の上面に、金属バンプ２０
１を設ける。金属バンプ２０１は基板１に半導体チップ
２を載置する前に、設けられていても良いし、載置後に
設けても良い。金属バンプ２０１は、半導体チップ２の
検査用電極２００ａに半田付け等の方法で固着すること
により導通可能に構成されている。A metal bump 20 is formed on the upper surface of the semiconductor chip 2.
1 is provided. The metal bump 201 may be provided before the semiconductor chip 2 is mounted on the substrate 1 or after the mounting. The metal bump 201 is configured to be conductive by being fixed to the inspection electrode 200a of the semiconductor chip 2 by a method such as soldering.
【００１７】次に、図３に示すように、半導体チップ２
を固定するための樹脂封じを行う。具体的には、図３に
示すように、樹脂封じ用の型枠３を設け、該型枠３の内
部に樹脂４を充填する。型枠３を形成する際には、後述
する金属バンプ２０１の露出工程を容易にするために、
金属バンプ２０１の部分を漏斗状の傾斜面を有する凹部
とすることが好ましい。かかる凹部を設ける効果は、以
下のことが考えられる。まず、金属バンプ２０１の高さ
方向の長さは、短いほうがコスト上好ましいため、かか
る短い金属バンプ２０１の先端を露出させる際に、樹脂
４に凹部を形成すれば露出しやすい。凹部の周辺の樹脂
部位はボンディングワイヤ１０２を埋設できる厚みを有
していることが好ましい。型枠３の材質は、樹脂との関
係で脱型しやすいものを選定することが好ましく、また
型枠の内面に離型剤を塗布しておくことも好ましい。Next, as shown in FIG.
Is sealed with resin to fix the resin. Specifically, as shown in FIG. 3, a mold 3 for sealing the resin is provided, and the inside of the mold 3 is filled with the resin 4. When forming the mold 3, in order to facilitate the step of exposing the metal bump 201 described below,
It is preferable that the portion of the metal bump 201 be a concave portion having a funnel-shaped inclined surface. The effect of providing such a concave portion is considered to be as follows. First, since the shorter the length of the metal bump 201 in the height direction is, the more preferable it is from the viewpoint of cost. The resin portion around the concave portion preferably has a thickness that allows the bonding wire 102 to be embedded. It is preferable to select a material for the mold 3 that is easy to remove in relation to the resin, and it is also preferable to apply a release agent to the inner surface of the mold.
【００１８】次に、脱型を行う。脱型後の状態は図４に
示すとおりである。Next, demolding is performed. The state after demolding is as shown in FIG.
【００１９】次に、金属バンプ２０１の露出工程を行
う。図４に示す半導体チップ２の上部に位置する斜線部
４００で示す領域の樹脂を除去する。除去した結果が図
５に示されている。除去手段としては、化学材料を用い
て溶解したり、あるいは機械的に研磨したりする等が挙
げられる。このとき用いることができる化学材料として
は、発煙硝酸等を用いることができる。また、斜線部４
００を削らないでいいように、予め型の形状を調整する
こともできる。Next, an exposure step of the metal bump 201 is performed. The resin in a region indicated by a hatched portion 400 located above the semiconductor chip 2 shown in FIG. 4 is removed. The result of the removal is shown in FIG. Examples of the removing means include dissolving using a chemical material, or mechanically polishing. As the chemical material that can be used at this time, fuming nitric acid or the like can be used. Also, the shaded area 4
The shape of the mold can be adjusted in advance so as not to cut 00.
【００２０】次に、上記のようにして、図５に示すよう
に金属バンプ２０１を露出させた後、図６に示すように
樹脂４の上面にレジスト層４０１を形成する。レジスト
層４０１の厚みは、金属バンプ２０１の上端を覆い隠す
程度でよい。Next, after the metal bump 201 is exposed as shown in FIG. 5 as described above, a resist layer 401 is formed on the upper surface of the resin 4 as shown in FIG. The thickness of the resist layer 401 may be such that the upper end of the metal bump 201 is covered.
【００２１】その後、レジスト層４０１のうち配線部分
をフォトエッチングによりパターニングする。具体的に
は配線部分の溝が形成される。この形成された溝に無電
解メッキ等の方法により金属パターン４０２（金属配
線、例えば、銅配線）を形成する。この状態が図７に示
されている。このように、金属パターン４０２は樹脂の
上面に形成され、一端は金属バンプ２０１に導通可能に
接続され、他端は、後述する検査用パットとして機能す
る。次に、金属パターン４０２が被覆するように、レジ
スト層４０３を形成する。その状態が図８に示されてい
る。かかるレジスト層４０３により、金属パターン４０
２が外気に曝されることによる酸化を防止できる。Thereafter, the wiring portion of the resist layer 401 is patterned by photoetching. Specifically, a groove in the wiring portion is formed. A metal pattern 402 (metal wiring, for example, copper wiring) is formed in the formed groove by a method such as electroless plating. This state is shown in FIG. As described above, the metal pattern 402 is formed on the upper surface of the resin, one end thereof is connected to the metal bump 201 so as to be conductive, and the other end functions as an inspection pad described later. Next, a resist layer 403 is formed so as to cover the metal pattern 402. This state is shown in FIG. The resist pattern 403 allows the metal pattern 40
2 can be prevented from being oxidized due to exposure to the outside air.
【００２２】次に、検査パッド４０４が設けられる部分
のレジスト層４０３をフォトエッチングすることにより
金属パターン４０２を部分的に露出させる。この状態が
図９に示されている。かかる金属パターン４０２を露出
させて検査パッド４０４を設けた半導体パッケージ５０
が得られる。Next, the metal pattern 402 is partially exposed by photo-etching the resist layer 403 where the inspection pad 404 is to be provided. This state is shown in FIG. The semiconductor package 50 having the metal pattern 402 exposed and the inspection pad 404 provided.
Is obtained.
【００２３】以上、半導体パッケージの製造方法につい
て一例を挙げて説明したが、上記に限定されない。上記
の態様では、樹脂４による樹脂封じの形態として金属バ
ンプ形成部に漏斗状の凹部を形成する方法を採用した
が、ボンディングワイヤ１０２の湾曲高さが金属バンプ
２０１の上端の位置とほぼ同等、若しくは湾曲高さが低
い場合は、かかる凹部設けることなく、樹脂４の厚みを
ほぼ一定とすることができる。このような場合は、金属
パターン４０２をプリント印刷により形成できる。Although the method of manufacturing a semiconductor package has been described above by way of example, the present invention is not limited to the above. In the above embodiment, a method of forming a funnel-shaped concave portion in the metal bump forming portion as a form of resin sealing with the resin 4 is adopted. However, the bending height of the bonding wire 102 is substantially equal to the position of the upper end of the metal bump 201. Alternatively, when the curved height is low, the thickness of the resin 4 can be made substantially constant without providing such a concave portion. In such a case, the metal pattern 402 can be formed by print printing.
【００２４】以上の方法によって、製造された半導体パ
ッケージは、図９及び図１０に示すように半導体チップ
２を封止した半導体パッケージ１において、実装用端子
１０１と反対側の封止面側に電気的検査を行える検査パ
ッド４０４を備えた構成である。As shown in FIGS. 9 and 10, the semiconductor package manufactured by the above-described method has the same structure as the semiconductor package 1 in which the semiconductor chip 2 is sealed. This is a configuration including an inspection pad 404 that can perform a dynamic inspection.
【００２５】かかる構成により、本発明の半導体パッケ
ージは、（実装用端子と同一面側に検査パッドを設ける
従来の半導体パッケージと比較すると）単位時間当たり
に半導体パッケージに送れる検査用の信号が多くなるの
で、検査時間が短くてすむ。半導体パッケージの表面積
の割に、電気的検査時に用いることができる端子を多く
設けることができるので、電気的検査にかかる時間が短
くて済む。With this configuration, in the semiconductor package of the present invention, the number of inspection signals that can be sent to the semiconductor package per unit time (compared with a conventional semiconductor package in which an inspection pad is provided on the same side as the mounting terminal) is increased. Therefore, the inspection time is short. Many terminals that can be used for electrical inspection can be provided for the surface area of the semiconductor package, so that the time required for electrical inspection can be reduced.
【００２６】本発明の半導体パッケージの検査方法につ
いて説明すると、図１１に示すように、半導体パッケー
ジ５０の実装面側Ａと封し面側Ｂの両側から検査用の信
号の入出力を行う。The method of inspecting a semiconductor package according to the present invention will be described. As shown in FIG. 11, signals for inspection are input and output from both sides of the mounting surface A and the sealing surface B of the semiconductor package 50.
【００２７】このように、本発明の半導体パッケージの
検査方法によれば、（実装面側Ａのみに検査用の信号の
入出力を行っていた従来の電気的検査に比べて）、単位
時間当たりに半導体パッケージに送れる検査用の信号が
多くなるので、検査時間が短くてすむ。半導体パッケー
ジの表面積の割に、電気的検査時に用いることができる
端子を多く設けることができるので、電気的検査にかか
る時間が短くて済む。As described above, according to the semiconductor package inspection method of the present invention, (in comparison with the conventional electrical inspection in which input / output of an inspection signal is performed only on the mounting surface A), a unit time Since the number of inspection signals that can be sent to the semiconductor package increases, the inspection time can be shortened. Many terminals that can be used for electrical inspection can be provided for the surface area of the semiconductor package, so that the time required for electrical inspection can be reduced.
【図１】本発明の半導体パッケージの製造方法の一例を
示す図FIG. 1 shows an example of a method for manufacturing a semiconductor package according to the present invention.
【図２】半導体チップの一例を示す図FIG. 2 illustrates an example of a semiconductor chip.
【図３】本発明の半導体パッケージの製造方法の一例を
示す図FIG. 3 is a diagram illustrating an example of a method of manufacturing a semiconductor package according to the present invention.
【図４】本発明の半導体パッケージの製造方法の一例を
示す図FIG. 4 is a diagram showing an example of a method for manufacturing a semiconductor package of the present invention.
【図５】本発明の半導体パッケージの製造方法の一例を
示す図FIG. 5 is a diagram showing an example of a method for manufacturing a semiconductor package according to the present invention.
【図６】本発明の半導体パッケージの製造方法の一例を
示す図FIG. 6 is a diagram showing an example of a method for manufacturing a semiconductor package according to the present invention.
【図７】本発明の半導体パッケージの製造方法の一例を
示す図FIG. 7 is a diagram showing an example of a method for manufacturing a semiconductor package according to the present invention.
【図８】本発明の半導体パッケージの製造方法の一例を
示す図FIG. 8 is a diagram showing an example of a method for manufacturing a semiconductor package according to the present invention.
【図９】本発明の半導体パッケージの製造方法の一例を
示す図FIG. 9 is a diagram illustrating an example of a method of manufacturing a semiconductor package according to the present invention.
【図１０】本発明の半導体パッケージの一例を示す平面
図FIG. 10 is a plan view showing an example of the semiconductor package of the present invention.
【図１１】本発明の半導体パッケージの検査方法を説明
するための図FIG. 11 is a view for explaining a semiconductor package inspection method according to the present invention;
１：基板 １００：上部端子 １０１：実装用端子 １０２：ボンディングワイヤ ２：半導体チップ ２００：電極部 ２００ａ：検査用電極 ２００ｂ：実装用電極 ２０１：金属バンプ ３：型枠 ４：樹脂 ４００：斜線部 ４０１：レジスト層 ４０２：金属パターン ４０３：レジスト層 ４０４：検査パッド ５０：半導体パッケージ Ａ：実装面側 Ｂ：封止面側 1: substrate 100: upper terminal 101: mounting terminal 102: Bonding wire 2: Semiconductor chip 200: Electrode section 200a: Test electrode 200b: mounting electrode 201: Metal bump 3: Formwork 4: Resin 400: shaded area 401: resist layer 402: metal pattern 403: resist layer 404: Inspection pad 50: Semiconductor package A: Mounting side B: Sealing surface side
───────────────────────────────────────────────────── フロントページの続き (72)発明者 上野 正広 東京都八王子市石川町2970番地 コニカ株 式会社内 (72)発明者 橋野 弘義 東京都八王子市石川町2970番地 コニカ株 式会社内 (72)発明者 濱 由香里 東京都八王子市石川町2970番地 コニカ株 式会社内 Ｆターム(参考） 2G003 AA07 AG09 AH00 AH04 4M109 AA01 BA01 BA04 CA21 DA10 DB15 DB17 5F061 AA01 BA01 BA03 CA21 DA06 ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Masahiro Ueno 2970 Ishikawacho, Hachioji-shi, Tokyo Konica share In the formula company (72) Inventor Hiroyoshi Hashino 2970 Ishikawacho, Hachioji-shi, Tokyo Konica share In the formula company (72) Inventor Yukari Hama 2970 Ishikawacho, Hachioji-shi, Tokyo Konica share In the formula company F-term (reference) 2G003 AA07 AG09 AH00 AH04 4M109 AA01 BA01 BA04 CA21 DA10 DB15 DB17 5F061 AA01 BA01 BA03 CA21 DA06
Claims (5)
において、実装用端子と反対側の封止面側に電気的検査
を行える検査パッドを有することを特徴とする半導体パ
ッケージ。1. A semiconductor package in which a semiconductor chip is sealed, the semiconductor package having an inspection pad for performing an electrical inspection on a sealing surface side opposite to a mounting terminal.
極とを有し、前記検査用電極は、前記検査パッドと導通
可能とされ、前記実装用電極は、前記実装用端子と導通
可能とされていることを特徴とする請求項１記載の半導
体パッケージ。2. The semiconductor chip has an electrode for inspection and an electrode for mounting, wherein the electrode for inspection is capable of conducting with the inspection pad, and the electrode for mounting is capable of conducting with the terminal for mounting. The semiconductor package according to claim 1, wherein:
実装用電極を備えた半導体チップを載置する工程と、金
属バンプを検査用電極に導通可能に設けると共に、実装
用電極と実装用端子とを導通可能に接続する工程と、半
導体チップを固定するための樹脂封じを行う工程と、金
属バンプの露出工程と、金属バンプと検査パッドを導通
する金属パターンを形成する工程とを有することを特徴
とする半導体パッケージの製造方法。3. A step of mounting a semiconductor chip provided with an inspection electrode and a mounting electrode on a substrate having a mounting terminal; And a step of performing resin sealing for fixing the semiconductor chip, a step of exposing a metal bump, and a step of forming a metal pattern for conducting the metal bump and the test pad. A method for manufacturing a semiconductor package, comprising:
ンプの部分を漏斗状の傾斜面を有する凹部とすることを
特徴とする請求項３記載の半導体パッケージの製造方
法。4. The method of manufacturing a semiconductor package according to claim 3, wherein in the step of sealing the resin, a portion of the metal bump is formed as a concave portion having a funnel-shaped inclined surface.
検査する方法であって、半導体パッケージの実装面側と
反対面側の両方から検査用の信号を送受することを特徴
とする半導体パッケージの検査方法。5. The method for inspecting a semiconductor package according to claim 1, wherein signals for inspection are transmitted and received from both a mounting surface side and an opposite surface side of the semiconductor package. Inspection method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002153922A JP2003347482A (en) | 2002-05-28 | 2002-05-28 | Semiconductor package, method for manufacturing semiconductor package and method for inspecting semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002153922A JP2003347482A (en) | 2002-05-28 | 2002-05-28 | Semiconductor package, method for manufacturing semiconductor package and method for inspecting semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003347482A true JP2003347482A (en) | 2003-12-05 |
Family
ID=29770839
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002153922A Pending JP2003347482A (en) | 2002-05-28 | 2002-05-28 | Semiconductor package, method for manufacturing semiconductor package and method for inspecting semiconductor package |
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| Country | Link |
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| JP (1) | JP2003347482A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2073262A1 (en) | 2007-12-18 | 2009-06-24 | Micronas GmbH | Semiconductor component |
| US7713764B2 (en) | 2008-07-10 | 2010-05-11 | Nec Electronics Corporation | Method for manufacturing semiconductor device including testing dedicated pad and probe card testing |
-
2002
- 2002-05-28 JP JP2002153922A patent/JP2003347482A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2073262A1 (en) | 2007-12-18 | 2009-06-24 | Micronas GmbH | Semiconductor component |
| US8125070B2 (en) | 2007-12-18 | 2012-02-28 | Micronas Gmbh | Semiconductor component |
| US7713764B2 (en) | 2008-07-10 | 2010-05-11 | Nec Electronics Corporation | Method for manufacturing semiconductor device including testing dedicated pad and probe card testing |
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