JPH06349875A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06349875A JPH06349875A JP5141701A JP14170193A JPH06349875A JP H06349875 A JPH06349875 A JP H06349875A JP 5141701 A JP5141701 A JP 5141701A JP 14170193 A JP14170193 A JP 14170193A JP H06349875 A JPH06349875 A JP H06349875A
- Authority
- JP
- Japan
- Prior art keywords
- inner lead
- bonding
- inner leads
- semiconductor chip
- common
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に、リード・オン・チップ（lead on chip，ＬＯＣと
いう）方式の実装を行う半導体装置に適用して有効な技
術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device for mounting on a lead-on-chip (LOC) system.
【０００２】[0002]
【従来の技術】半導体チップは、外部端子となるリード
と接続された後に、パッケージに封止されて製品とな
る。この封止に先立つ半導体チップとリードとの接続は
種々の方法で行われるが、その一つにリード・オン・チ
ップがある。2. Description of the Related Art A semiconductor chip is sealed as a product after being connected to a lead serving as an external terminal. The connection between the semiconductor chip and the lead prior to this sealing is performed by various methods, one of which is the lead-on-chip.
【０００３】この方法では、半導体チップの回路形成面
上に、絶縁性のフィルムを介して複数のインナーリード
を接着し、このインナーリードと半導体チップのボンデ
ィングパッドとがボンディングワイヤ等で電気的に接続
されている。半導体チップのボンディングパッドの配置
は、入出力の経路を短くすることによって高速化を図る
ため及びパッケージの外表面からボンディングパッドま
での距離をとることによって半導体装置の耐湿性を向上
させるために、半導体チップの中心線に沿って一列に配
置されている。このように配置されたボンディングパッ
ドの両側に、電源用の共用インナーリードが配置され、
その外側に信号用のインナーリードが配置されている。In this method, a plurality of inner leads are bonded to the circuit forming surface of the semiconductor chip via an insulating film, and the inner leads and the bonding pads of the semiconductor chip are electrically connected by bonding wires or the like. Has been done. The layout of the bonding pads of the semiconductor chip is performed by shortening the input / output path to increase the speed and by increasing the distance from the outer surface of the package to the bonding pad to improve the moisture resistance of the semiconductor device. The chips are arranged in a line along the center line of the chip. On both sides of the bonding pad arranged in this way, shared inner leads for power supply are arranged,
Inner leads for signals are arranged on the outside thereof.
【０００４】[0004]
【発明が解決しようとする課題】このようなボンディン
グパッド配置のために、信号用インナーリードに接続す
るボンディングワイヤは共用インナーリードの上を跨ぐ
ようにして、ボンディングされている。従って、ボンデ
ィングパッドから信号用インナーリードまでの距離が長
くなり、ボンディングワイヤの抵抗が高くなる。さら
に、ボンディングワイヤが長くなるために他のボンディ
ングワイヤ或いはリードと接触し、半導体装置が作動不
良或いは作動不能となることがある。Due to such a bonding pad arrangement, the bonding wires connected to the signal inner leads are bonded so as to straddle over the common inner leads. Therefore, the distance from the bonding pad to the signal inner lead becomes long, and the resistance of the bonding wire becomes high. Further, since the bonding wire becomes long, it may come into contact with another bonding wire or lead, and the semiconductor device may malfunction or become inoperable.
【０００５】ボンディングワイヤと共用インナーリード
との接触を防止するためには、ワイヤと共用インナーリ
−ドとのクリアランスを確保する必要があり、ボンディ
ングワイヤと共用インナーリードとの間にはできるだけ
距離をおくことが望ましいが、同時にまたパッケージの
厚さからボンディングワイヤのル−プ高さが制限されて
いる。このため、ボンディングワイヤの許容範囲が小さ
くなり、ル−プコントロ−ルが難しく、ワイヤ変形不良
も起こり易い。また、ワイヤル−プコントロ−ルの条件
出し，ワイヤと共用インナーリ−ドのクリアランス測定
及びル−プ高さ測定に時間がかかるため、ボンディング
に要する時間も長くなり、スル−プットが低下する。In order to prevent contact between the bonding wire and the common inner lead, it is necessary to secure a clearance between the wire and the common inner lead, and the bonding wire and the common inner lead should be separated as much as possible. At the same time, however, the package thickness also limits the bond wire loop height. For this reason, the allowable range of the bonding wire becomes small, loop control is difficult, and defective wire deformation easily occurs. In addition, since it takes time to determine the conditions of the wire loop control, measure the clearance between the wire and the inner lead shared with the wire, and measure the loop height, the time required for bonding becomes long and the throughput decreases.
【０００６】また、信号用リードに接続するボンディン
グワイヤが共用インナーリードを覆うので、共用インナ
ーリ−ドへのボンディング状態の外観検査が困難にな
る。Further, since the bonding wire connected to the signal lead covers the common inner lead, it becomes difficult to visually inspect the bonding state of the common inner lead.
【０００７】本発明の目的は、これらの問題を解決する
ために、ボンディングワイヤの配線長を短縮することが
可能な技術を提供すること、及びボンディング作業を迅
速に行い得る技術を提供することにある。It is an object of the present invention to provide a technique capable of shortening the wiring length of a bonding wire in order to solve these problems, and to provide a technique capable of performing a bonding operation quickly. is there.
【０００８】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【０００９】[0009]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.
【００１０】半導体チップの表面には、中心線に沿って
整列した複数のボンディングパッドを設け、該ボンディ
ングパッドの形成する列に平行してボンディングパッド
の両側に、整列した複数のボンディングパッドを設け、
共用インナーリードを各ボンディングパッドの形成する
列の間に配置する。A plurality of bonding pads aligned along the center line are provided on the surface of the semiconductor chip, and a plurality of aligned bonding pads are provided on both sides of the bonding pad in parallel with a row formed by the bonding pads.
Shared inner leads are placed between the rows formed by each bonding pad.
【００１１】ボンディングパッドの配置として、中心に
設けるボンディングパッドには、電源用の配線を接続
し、両側のボンディングパッドには信号用或いは隣接す
る共用インナーリードに接続する電源用の配線を接続す
る。As for the arrangement of the bonding pads, the wiring for power supply is connected to the bonding pad provided at the center, and the wiring for power supply for connecting to the signal or the adjacent shared inner lead is connected to the bonding pads on both sides.
【００１２】または、共用インナーリードの上を越える
ボンディングワイヤのインナーリードとのクリアランス
を確保するために、共用インナーリードの厚さを信号用
インナーリードの厚さよりも薄くする。Alternatively, the thickness of the shared inner lead is made smaller than the thickness of the signal inner lead in order to secure a clearance between the shared inner lead and the inner lead of the bonding wire.
【００１３】[0013]
【作用】上述した手段によれば、ボンディングパッド
を、接続するインナーリードと隣接させて配置すること
により、最短距離でボンディングすることができるの
で、ボンディングワイヤによる抵抗の増加を防止でき
る。According to the above-mentioned means, since the bonding pad is arranged adjacent to the inner lead to be connected, the bonding can be carried out in the shortest distance, so that the resistance increase due to the bonding wire can be prevented.
【００１４】また、隣接するボンディングパッドとイン
ナーリードとをボンディングするので、共用インナーリ
ードを越えてボンディングを行う必要がなくなる。従っ
て、ボンディングワイヤのループコントロールが容易と
なり、かつワイヤ変形不良を低減できる。Further, since the adjacent bonding pad and the inner lead are bonded, it is not necessary to perform bonding beyond the shared inner lead. Therefore, the loop control of the bonding wire becomes easy, and the wire deformation defect can be reduced.
【００１５】さらに、外観検査工程にて、共用インナー
リードを越えるボンディングワイヤと共用インナーリ−
ドとのクリアランス測定が行う必要がないので、外観検
査工数の低減が図れ、加えてボンディングワイヤのル−
プコントロ−ル条件出しが容易となるので、ボンディン
グ作業を迅速に行い得るという効果がある。Further, in the appearance inspection process, the bonding wire and the common inner lead that exceed the common inner lead are used.
Since it is not necessary to measure the clearance with the cable, the number of appearance inspection steps can be reduced, and the bonding wire routing can be reduced.
Since it becomes easy to determine the condition for the control, there is an effect that the bonding work can be performed quickly.
【００１６】また、共用インナーリードの厚みを薄くす
ることにより、ボンディングワイヤと共用インナーリー
ドとのクリアランスが増加し、ボンディングワイヤのル
ープコントロールが容易となり、加えてワイヤ変形不良
を低減できる。Further, by reducing the thickness of the shared inner lead, the clearance between the bonding wire and the shared inner lead is increased, the loop control of the bonding wire is facilitated, and the wire deformation defect can be reduced.
【００１７】以下、本発明の構成について、実施例とと
もに説明する。The structure of the present invention will be described below together with embodiments.
【００１８】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for explaining the embodiments, parts having the same functions are designated by the same reference numerals, and the repeated description thereof will be omitted.
【００１９】[0019]
【実施例】（実施例１）以下、本発明の実施例を図１に
より説明する。Embodiment 1 Embodiment 1 of the present invention will be described below with reference to FIG.
【００２０】図１は本発明の一実施例である半導体装置
の半導体チップ周辺を示す部分平面図である。FIG. 1 is a partial plan view showing the periphery of a semiconductor chip of a semiconductor device according to an embodiment of the present invention.
【００２１】図中、１は半導体チップ、２は共用インナ
ーリード、３は信号用インナーリードである。In the figure, 1 is a semiconductor chip, 2 is a common inner lead, and 3 is a signal inner lead.
【００２２】半導体チップ１は、単結晶シリコンからな
る半導体基板の回路形成面に複数の半導体素子を形成
し、これらの半導体素子をパターン形成した配線層によ
って結線接続し、回路形成面の表面を絶縁性の最終保護
膜によって覆い、所定の回路システムを構成している。
半導体チップ１の表面には、中心線に沿って整列した複
数のボンディングパッド４を設け、ボンディングパッド
４の形成する列に平行してボンディングパッド４の両側
に、整列した複数のボンディングパッド５，５を設け
る。In the semiconductor chip 1, a plurality of semiconductor elements are formed on a circuit forming surface of a semiconductor substrate made of single crystal silicon, and these semiconductor elements are connected by a wiring layer having a pattern formed thereon to insulate the surface of the circuit forming surface. It is covered with a protective final protective film to form a predetermined circuit system.
A plurality of bonding pads 4 aligned along the center line are provided on the surface of the semiconductor chip 1, and a plurality of bonding pads 5, 5 aligned on both sides of the bonding pad 4 in parallel with the row formed by the bonding pads 4. To provide.
【００２３】共用インナーリード２は、ボンディングパ
ッド４，５の列と平行に、ボンディングパッド４とボン
ディングパッド５との間に延在し、半導体チップ１の端
部近傍にて直角に向きを変えて、中心線に直交して、半
導体チップ１の外方に延在することにより、略コ字状に
形成する。共用インナーリード２は、ボンディングパッ
ド４を挟んで一対形成し、それぞれの共用インナーリー
ド２が電源の供給用及び接地用の配線と接続される。The common inner lead 2 extends between the bonding pad 4 and the bonding pad 5 in parallel with the row of the bonding pads 4 and 5 and turns at right angles in the vicinity of the end of the semiconductor chip 1. , And is formed in a substantially U-shape by extending outside the semiconductor chip 1 at right angles to the center line. A pair of shared inner leads 2 are formed with the bonding pad 4 interposed therebetween, and each shared inner lead 2 is connected to a wiring for power supply and a wiring for grounding.
【００２４】信号用インナーリード３は、ボンディング
パッド５の外側に、一端を臨ませて、他端を半導体チッ
プ１の中心線に直交する方向に半導体チップ１の外方へ
延在させる。複数の信号用インナーリード３を平行配置
するが、信号用インナーリード３及びボンディングパッ
ド５は共用インナーリード２によって囲まれた領域内に
設けてある。The signal inner lead 3 has one end facing the outside of the bonding pad 5 and the other end extending outward of the semiconductor chip 1 in a direction orthogonal to the center line of the semiconductor chip 1. Although a plurality of signal inner leads 3 are arranged in parallel, the signal inner leads 3 and the bonding pads 5 are provided in the area surrounded by the shared inner leads 2.
【００２５】共用インナーリード２及び信号用インナー
リード３は、両面に熱可塑性の接着剤を塗布した絶縁性
のフィルム（図示せず）によって、回路形成面の最終保
護膜上に固定される。この接着によって、半導体チップ
１はインナーリード２，３によって支持されることとな
る。The common inner lead 2 and the signal inner lead 3 are fixed on the final protective film on the circuit forming surface by an insulating film (not shown) whose both surfaces are coated with a thermoplastic adhesive. By this bonding, the semiconductor chip 1 is supported by the inner leads 2 and 3.
【００２６】各インナーリード２，３は、実装時に外部
の装置・配線と接続するために半導体装置のパッケージ
（図示せず）から突出するアウターリード（図示せず）
と一体になっている。Each inner lead 2, 3 is an outer lead (not shown) protruding from a semiconductor device package (not shown) for connecting to an external device / wiring during mounting.
It is integrated with.
【００２７】ボンディングパッド４，５の配置として、
中心に設けるボンディングパッド４には、電源用の配線
を接続し、両側のボンディングパッド５，５には信号用
或いは隣接する共用インナーリード２に接続する電源用
の配線を接続する。As the arrangement of the bonding pads 4 and 5,
Wiring for power supply is connected to the bonding pad 4 provided at the center, and wiring for power supply or to the common inner lead 2 adjacent to the signal is connected to the bonding pads 5 and 5 on both sides.
【００２８】このようにボンディングパッド４，５を配
置することにより、各ボンディングワイヤ６はインナー
リード２，３とそれに隣接するボンディングパッド４，
５とを接続するので、ボンディングを最短距離で行うこ
とができる。従って、ボンディングワイヤ６による抵抗
の増加を防止することが可能になる。また、隣接するボ
ンディングパッド４，５と各インナーリード２，３とを
ボンディングするので、共用インナーリード２を越えて
ボンディングを行う必要がなくなる。By arranging the bonding pads 4 and 5 in this manner, the respective bonding wires 6 are connected to the inner leads 2 and 3 and the bonding pads 4 and 4 adjacent thereto.
Since 5 is connected, bonding can be performed in the shortest distance. Therefore, it becomes possible to prevent an increase in resistance due to the bonding wire 6. In addition, since the adjacent bonding pads 4 and 5 and the inner leads 2 and 3 are bonded, it is not necessary to perform bonding beyond the shared inner lead 2.
【００２９】（実施例２）図２は本発明の他の実施例で
ある半導体装置の半導体チップ周辺を示す部分縦断面図
であり、図３はその部分平面図である。なお、図２中に
てボンディングワイヤは１本のみを表示し他を省略す
る。(Embodiment 2) FIG. 2 is a partial vertical sectional view showing the periphery of a semiconductor chip of a semiconductor device according to another embodiment of the present invention, and FIG. 3 is a partial plan view thereof. In FIG. 2, only one bonding wire is shown and the others are omitted.
【００３０】図中、１は半導体チップ、２は共用インナ
ーリード、３は信号用インナーリードである。In the figure, 1 is a semiconductor chip, 2 is a common inner lead, and 3 is a signal inner lead.
【００３１】半導体チップ１の表面には、中心線に沿っ
て整列した複数のボンディングパッド４を設ける。On the surface of the semiconductor chip 1, a plurality of bonding pads 4 aligned along the center line are provided.
【００３２】共用インナーリード２，２は、ボンディン
グパッド４の列と平行に、ボンディングパッド４を挟ん
で一対形成する。共用インナーリード２はボンディング
パッド４の列に沿って延在し、半導体チップ１の端部近
傍にて直角に向きを変えて、中心線に直交して、半導体
チップ１の外方に延在することにより、略コ字状に形成
する。共用インナーリード２は、それぞれの共用インナ
ーリード２が電源の供給用及び接地用の配線と接続され
る。A pair of common inner leads 2 and 2 are formed in parallel with the row of bonding pads 4 with the bonding pads 4 sandwiched therebetween. The common inner lead 2 extends along the row of the bonding pads 4, turns at right angles in the vicinity of the end of the semiconductor chip 1, and extends outside the semiconductor chip 1 at right angles to the center line. As a result, it is formed into a substantially U shape. The common inner leads 2 are connected to the common inner leads 2 for supplying power and grounding.
【００３３】本実施例では、共用インナーリード２の上
を越えるボンディングワイヤ６のインナーリード２との
クリアランスを確保するために、共用インナーリード２
の厚さを信号用インナーリード３の厚さよりも薄く形成
する。共用インナーリード２は、その全面を薄く形成し
てもよいし、ボンディングパッド４の列に沿って延在す
る部分のみを薄く形成してもよい。共用インナーリード
２を薄くする方法としては、エッチング加工あるいはプ
レス加工等を施せばよい。In this embodiment, in order to secure the clearance between the bonding wire 6 and the inner lead 2 over the common inner lead 2, the common inner lead 2 is used.
Is formed thinner than the thickness of the signal inner lead 3. The common inner lead 2 may be thinly formed on the entire surface, or may be thinly formed only on a portion extending along the row of the bonding pads 4. As a method of thinning the common inner lead 2, etching, pressing, or the like may be performed.
【００３４】信号用インナーリード３は、共用インナー
リード２の外側に、一端を臨ませて、他端を半導体チッ
プ１の中心線に直交する方向に半導体チップ１の外方へ
延在させる。複数の信号用インナーリード３を平行配置
するが、信号用インナーリード３は共用インナーリード
２によって囲まれた領域内に設けてある。The signal inner lead 3 has one end facing the outside of the shared inner lead 2 and the other end extending outward of the semiconductor chip 1 in a direction orthogonal to the center line of the semiconductor chip 1. A plurality of signal inner leads 3 are arranged in parallel, but the signal inner leads 3 are provided within the area surrounded by the shared inner leads 2.
【００３５】共用インナーリード２及び信号用インナー
リード３は、両面に熱可塑性の接着剤を塗布した絶縁性
のフィルム７によって、回路形成面の最終保護膜上に固
定される。この接着によって、半導体チップ１はインナ
ーリード２，３によって支持されることとなる。The common inner lead 2 and the signal inner lead 3 are fixed on the final protective film on the circuit forming surface by an insulating film 7 having thermoplastic adhesive applied on both sides. By this bonding, the semiconductor chip 1 is supported by the inner leads 2 and 3.
【００３６】このように共用インナーリード２のボンデ
ィングパッド５に沿って延在する部分を薄く形成するこ
とにより、共用インナーリード２を越えて信号用インナ
ーリード３に接続するボンディングワイヤ６と共用イン
ナーリード２とのクリアランスが増大するので、共用イ
ンナーリード２を越えるボンディングワイヤ６のワイヤ
ル−プコントロ−ルがを容易になる。By thinly forming the portion of the shared inner lead 2 extending along the bonding pad 5, the bonding wire 6 and the shared inner lead which are connected to the signal inner lead 3 beyond the shared inner lead 2 are formed. Since the clearance between the bonding wire 6 and the common inner lead 2 is increased, the wire loop control of the bonding wire 6 over the shared inner lead 2 is facilitated.
【００３７】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。As described above, the invention made by the present inventor is
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.
【００３８】[0038]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００３９】（１）ボンディングパッドを、接続するイ
ンナーリードと隣接させて配置することにより、最短距
離でボンディングすることができるので、ボンディング
ワイヤによる抵抗の増加を防止できるという効果があ
る。(1) By arranging the bonding pad adjacent to the inner lead to be connected, it is possible to perform bonding in the shortest distance, so that it is possible to prevent an increase in resistance due to the bonding wire.
【００４０】（２）ボンディングパッドを、接続するイ
ンナーリードと隣接させて配置することにより、隣接す
るボンディングパッドとインナーリードとをボンディン
グするので、共用インナーリード２を越えてボンディン
グを行う必要がなくなるという効果がある。(2) By arranging the bonding pad adjacent to the inner lead to be connected, the adjacent bonding pad and the inner lead are bonded, so that it is not necessary to perform bonding beyond the shared inner lead 2. effective.
【００４１】（３）前記効果（２）により、ボンディン
グワイヤのループコントロールが容易となり、ワイヤ変
形不良を低減出来るという効果がある。(3) Due to the effect (2), there is an effect that the loop control of the bonding wire is facilitated and the wire deformation defect can be reduced.
【００４２】（４）前記効果（２）により、外観検査工
程にて、共用インナーリードを越えるボンディングワイ
ヤと共用インナーリ−ドのクリアランス測定を行う必要
がないので、外観検査工数の低減が図れるという効果が
ある。(4) Due to the above effect (2), it is not necessary to measure the clearance between the bonding wire and the common inner lead that crosses the common inner lead in the appearance inspection step, so that the appearance inspection man-hour can be reduced. There is.
【００４３】（５）前記効果（２）により、ボンディン
グワイヤのループコントロール条件出しが容易となると
いう効果がある。(5) The above effect (2) has an effect that the loop control condition of the bonding wire can be easily determined.
【００４４】（６）前記効果（４），（５）により、ボ
ンディング作業を迅速に行い得るという効果がある。(6) Due to the effects (4) and (5), there is an effect that the bonding work can be carried out quickly.
【００４５】（７）共用インナーリードの厚みを薄くす
ることにより、ボンディングワイヤと共用インナーリー
ドとのクリアランスが増加し、ボンディングワイヤのル
ープコントロールが容易となるという効果がある。(7) By reducing the thickness of the shared inner lead, the clearance between the bonding wire and the shared inner lead is increased, and the loop control of the bonding wire is facilitated.
【００４６】（８）前記効果（７）により、ボンディン
グワイヤのループコントロールが容易となり、ワイヤ変
形不良を低減できるという効果がある。(8) Due to the above effect (7), there is an effect that the loop control of the bonding wire is facilitated and defective wire deformation can be reduced.
【００４７】（９）前記効果（７）により、ボンディン
グワイヤのループコントロール条件出しが容易となると
いう効果がある。(9) The effect (7) has an effect that the loop control condition of the bonding wire can be easily set.
【００４８】（１０）前記効果（８），（９）により、
ボンディング作業を迅速に行い得るという効果がある。(10) Due to the effects (8) and (9),
There is an effect that the bonding work can be performed quickly.
【００４９】（１１）共用インナーリードの厚みを薄く
することにより、ボンディングワイヤと共用インナーリ
ードとのクリアランスが増加し、ワイヤ変形不良を低減
できるという効果がある。(11) By reducing the thickness of the shared inner lead, the clearance between the bonding wire and the shared inner lead can be increased, and wire deformation defects can be reduced.
【図１】 本発明の一実施例である半導体装置の半導体
チップ周辺を示す部分平面図、FIG. 1 is a partial plan view showing the periphery of a semiconductor chip of a semiconductor device according to an embodiment of the present invention,
【図２】 本発明の他の実施例である半導体装置の半導
体チップ周辺を示す部分縦断面図、FIG. 2 is a partial vertical cross-sectional view showing the periphery of a semiconductor chip of a semiconductor device according to another embodiment of the present invention,
【図３】 本発明の他の実施例である半導体装置の半導
体チップ周辺を示す部分平面図である。FIG. 3 is a partial plan view showing the periphery of a semiconductor chip of a semiconductor device according to another embodiment of the present invention.
１…半導体チップ、２…共用インナーリード、３…信号
用インナーリード、４，５…ボンディングパッド、６…
ボンディングワイヤ。1 ... Semiconductor chip, 2 ... Common inner lead, 3 ... Signal inner lead, 4, 5 ... Bonding pad, 6 ...
Bonding wire.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 角谷 修 東京都青梅市藤橋３丁目３番地２ 日立東 京エレクトロニクス株式会社内 (72)発明者 牧 浩 東京都青梅市藤橋３丁目３番地２ 日立東 京エレクトロニクス株式会社内 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Osamu Sumiya 3-3, Fujibashi, Ome, Tokyo 2-3 Hitachi Tokyo Electronics Co., Ltd. (72) Inventor Hiroshi Maki 3-3, Fujibashi, Ome, Tokyo 2 Hitachi-Higashi Inside Kyo Electronics Co., Ltd.
Claims (2)
共用インナーリードと複数の信号用インナーリードと
が、絶縁体を介して前記半導体チップと接着され、信号
用インナーリード及び共用インナーリードと半導体チッ
プのボンディングパッドとがボンディングされ、ケース
内に封止される半導体装置であって、ボンディングパッ
ドが信号用インナーリードと共用インナーリードとの間
及び対をなす共用インナーリードの間に設置されている
ことを特徴とする半導体装置。1. A pair of common inner leads and a plurality of signal inner leads are adhered to the semiconductor chip via an insulator on a circuit formation surface of the semiconductor chip to form a signal inner lead and a common inner lead. A semiconductor device in which a bonding pad of a semiconductor chip is bonded and sealed in a case, wherein the bonding pad is installed between a signal inner lead and a common inner lead and between a pair of common inner leads. A semiconductor device characterized in that
共用インナーリードと複数の信号用インナーリードと
が、絶縁体を介して前記半導体チップと接着され、信号
用インナーリード及び共用インナーリードと半導体チッ
プのボンディングパッドとがボンディングされ、ケース
内に封止される半導体装置であって、少なくとも、信号
用インナーリードと直交する方向に延在する部分の共用
インナーリードの厚さを、信号用インナーリードの厚さ
よりも薄くしたことを特徴とする半導体装置。2. A pair of common inner leads and a plurality of signal inner leads are adhered to the semiconductor chip via an insulator on a circuit formation surface of the semiconductor chip to form a signal inner lead and a common inner lead. In a semiconductor device, which is bonded to a bonding pad of a semiconductor chip and sealed in a case, at least a portion of a shared inner lead extending in a direction orthogonal to a signal inner lead is set to a signal inner A semiconductor device characterized by being made thinner than the thickness of the lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5141701A JPH06349875A (en) | 1993-06-14 | 1993-06-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5141701A JPH06349875A (en) | 1993-06-14 | 1993-06-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06349875A true JPH06349875A (en) | 1994-12-22 |
Family
ID=15298195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5141701A Pending JPH06349875A (en) | 1993-06-14 | 1993-06-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06349875A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0677273A (en) * | 1992-07-08 | 1994-03-18 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit device |
| US6054753A (en) * | 1997-08-12 | 2000-04-25 | Nec Corporation | Plastic-encapsulated semiconductor device equipped with LOC package structure |
| US6303948B1 (en) | 1996-02-29 | 2001-10-16 | Kabushiki Kaisha Toshiba | Pad layout and lead layout in semiconductor device |
-
1993
- 1993-06-14 JP JP5141701A patent/JPH06349875A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0677273A (en) * | 1992-07-08 | 1994-03-18 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit device |
| JP3119544B2 (en) * | 1992-07-08 | 2000-12-25 | 日本電気アイシーマイコンシステム株式会社 | Semiconductor integrated circuit device |
| US6303948B1 (en) | 1996-02-29 | 2001-10-16 | Kabushiki Kaisha Toshiba | Pad layout and lead layout in semiconductor device |
| US6617622B2 (en) | 1996-02-29 | 2003-09-09 | Kabushiki Kaisha Toshiba | Pad layout and lead layout in semiconductor device having a center circuit |
| US6054753A (en) * | 1997-08-12 | 2000-04-25 | Nec Corporation | Plastic-encapsulated semiconductor device equipped with LOC package structure |
| KR100325189B1 (en) * | 1997-12-08 | 2002-05-09 | 가네꼬 히사시 | Plastic-encapsulated semiconductor device equipped with loc package structure |
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