KR20010039902A - Semiconductor device of chip·on·chip structure - Google Patents
Semiconductor device of chip·on·chip structure Download PDFInfo
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- KR20010039902A KR20010039902A KR1020000054905A KR20000054905A KR20010039902A KR 20010039902 A KR20010039902 A KR 20010039902A KR 1020000054905 A KR1020000054905 A KR 1020000054905A KR 20000054905 A KR20000054905 A KR 20000054905A KR 20010039902 A KR20010039902 A KR 20010039902A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 239000000523 sample Substances 0.000 abstract description 10
- 238000012790 confirmation Methods 0.000 abstract description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
본 발명은, 칩·온·칩 구조의 반도체장치에 관한 것이다.The present invention relates to a semiconductor device having a chip on chip structure.
종래부터, 반도체 칩(주칩)의 표면에 다른 반도체 칩(부칩)의 표면을 대향시킨 상태로 중첩시켜 접합한 칩·온·칩 구조의 반도체장치가 있다.Background Art Conventionally, there is a semiconductor device having a chip-on-chip structure in which a surface of a semiconductor chip (main chip) is superposed and bonded to each other in a state where the surface of another semiconductor chip (sub-chip) is opposed.
이와 같은 칩·온·칩 구조의 반도체장치에서는, 주칩 및 부칩의 표면에 범프가 형성되어 있다.In such a chip-on-chip semiconductor device, bumps are formed on the surfaces of the main chip and the sub chip.
주칩의 범프에 부칩의 범프를 접합시키는 것에 의해, 부칩이 주칩과 소정의 간격을 둔 상태로 접합되며, 또한 주칩 및 부칩 사이의 전기접속이 달성된다.By bonding the bumps of the sub-chips to the bumps of the main chip, the sub-chips are bonded at a predetermined interval from the main chip, and electrical connection between the main chip and the sub-chips is achieved.
주칩 및 부칩은, 서로 접합되기 이전이라면, 각각의 범프에 테스트 프로브를 대고 동작확인을 위한 테스트를 실시할 수가 있다.Before the main chip and the sub chip are bonded to each other, a test probe can be applied to each bump to test the operation.
또한, 주칩과 부칩이 접합된 후에라도, 주칩의 둘레 테두리부근에 설치된 외부접속용 패드에 테스트 프로브를 대는 것에 의해, 반도체장치 전체의 동작확인을 위한 테스트를 실시할 수는 있다.Further, even after the main chip and the sub chip are joined, the test probe can be tested for the operation check of the entire semiconductor device by applying a test probe to an external connection pad provided near the peripheral edge of the main chip.
그러나, 주칩과 부칩이 접합된 후에는, 주칩 또는 부칩만의 동작을 확인할 수는 없었다.However, after the main chip and the sub chip were joined, the operation of only the main chip or the sub chip could not be confirmed.
또, 주칩과 부칩의 접속상태만을 확인할 수는 없었다.Moreover, only the connection state of the main chip and the sub chip could not be confirmed.
본 발명의 제1의 목적은, 제1의 반도체 칩과 제2의 반도체 칩을 접합시킨 후에 있어서도, 각 반도체 칩 단일체로서의 기능을 확인하기 위한 테스트를 행할 수가 있는 칩·온·칩 구조의 반도체장치를 제공하는 것이다.A first object of the present invention is a chip-on-chip structured semiconductor device which can perform a test for confirming the function of each semiconductor chip unit even after the first semiconductor chip and the second semiconductor chip are bonded together. To provide.
또, 본 발명의 제2의 목적은, 제1의 반도체 칩과 제2의 반도체 칩을 접합시킨 후에 있어서도, 제1의 반도체 칩과 제2의 반도체 칩의 접속상태를 확인하기 위한 테스트를 행할 수 있는 칩·온·칩 구조의 반도체장치를 제공하는 것이다.In addition, the second object of the present invention can be tested to confirm the connection state between the first semiconductor chip and the second semiconductor chip even after the first semiconductor chip and the second semiconductor chip are bonded together. To provide a chip-on-chip semiconductor device.
또한, 본 발명의 제3의 목적은, 상기와 같은 반도체장치의 구성에 적합한 반도체 칩을 제공하는 것이다.Moreover, the 3rd object of this invention is to provide the semiconductor chip suitable for the structure of such a semiconductor device.
도 1은, 본 발명의 일실시형태의 반도체장치의 개략구성을 나타내는 도해적인 단면도.1 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device of one embodiment of the present invention.
도 2는, 상기 반도체장치의 평면도.2 is a plan view of the semiconductor device.
(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
1 : 주칩 2 : 부칩1: main chip 2: sub chip
11 : 주칩의 표면 12 : 접합영역11 surface of main chip 12 junction area
13 : 패드 14 : 연설부(延設部)13: pad 14: speech section
21 : 부칩의 표면 BM : 주칩의 범프21: Surface of sub chip BM: Bump of main chip
BS : 부칩의 범프 P : 테스트프로브BS: Bump of sub chip P: Test probe
본 발명의 반도체장치는, 제1의 반도체 칩과 제2의 반도체 칩이 서로 표면을 대향시킨 상태로 중첩되어 접합된 칩·온·칩 구조의 반도체장치로서, 상기 제1의 반도체 칩의 표면에 있어서 상기 제2의 반도체 칩을 접합시키기 위해 설정된 접합영역 내에 형성되며, 상기 제1의 반도체 칩 및 상기 제2의 반도체 칩을, 예를 들면, 소정의 간격을 둔 상태로 결합시킴과 동시에 상기 제1 및 제2의 반도체 칩 사이의 전기접속을 달성시키기 위한 범프와, 상기 제1의 반도체 칩의 표면에 있어서 상기 범프에 접속되어 형성되며 일단이 상기 접합영역의 바깥쪽으로 인출된 도전성의 연설부(바람직하게는, 범프와 동일한 재료로 이루어지는 것)를 포함한다.The semiconductor device of the present invention is a semiconductor device having a chip-on-chip structure in which a first semiconductor chip and a second semiconductor chip are overlapped and joined in a state where their surfaces are opposed to each other. The second semiconductor chip is formed in a junction region set for bonding the second semiconductor chip, and the first semiconductor chip and the second semiconductor chip are joined to each other at a predetermined interval, for example. A bump for achieving an electrical connection between the first and second semiconductor chips, and a conductive speaker having one end connected to the bump on the surface of the first semiconductor chip and having one end drawn outward of the junction region ( Preferably made of the same material as the bumps).
본 발명에 의하면, 제1의 반도체 칩의 범프에는, 일단이 제2의 반도체 칩의 접합영역 바깥까지 인출된 연설부가 접속되어 있다.According to the present invention, the speaker portion, one end of which is drawn out to the outside of the junction region of the second semiconductor chip, is connected to the bump of the first semiconductor chip.
이에 의해, 제1의 반도체 칩과 제2의 반도체 칩이 접합된 후에 있어서도, 연설부의 접합영역 바깥쪽으로 인출된 부분에 테스트 프로브를 대고, 제1의 반도체 칩 또는 제2의 반도체 칩만의 동작확인을 행할 수가 있다.Thus, even after the first semiconductor chip and the second semiconductor chip are joined together, the test probe is placed on the portion drawn outward from the junction region of the speaker, and the operation confirmation of only the first semiconductor chip or the second semiconductor chip is confirmed. I can do it.
또, 제1의 반도체 칩과 제2의 반도체 칩의 접속확인을 행할 수가 있다.In addition, it is possible to confirm the connection between the first semiconductor chip and the second semiconductor chip.
또한, 상기 연설부는, 상기 범프와 일체로 형성되어 있는 것이 바람직하다.Moreover, it is preferable that the said speech part is formed integrally with the said bump.
이 경우, 상기 범프가, 상기 접합영역의 경계부에 걸쳐있는 상태로 형성되며, 그 범프와 상기 제2의 반도체 칩의 접합부분 이외의 부분을 상기 연설부로 하여도 좋다.In this case, the bumps may be formed so as to extend over the boundary portion of the junction region, and portions other than the junction portions of the bumps and the second semiconductor chip may be the extending portions.
본 발명의 상기한 설명과, 그 밖의 다른 목적, 특징 및 효과는, 첨부도면을 참조한 이하의 실시형태의 설명에 의하여 확실하게 될 것이다.The above description of the present invention and other objects, features, and effects will be ascertained by the following description of the embodiments with reference to the accompanying drawings.
(실시예)(Example)
도 1은 본 발명의 일실시형태에 있어서의 반도체장치의 개략구성을 나타내는 도해적인 단면도이며, 도 2는 그 평면도이다.1 is a schematic sectional view showing a schematic configuration of a semiconductor device in one embodiment of the present invention, and FIG. 2 is a plan view thereof.
이 반도체장치는, 제1의 반도체 칩으로서의 주칩(1)의 표면(11)에 제2의 반도체 칩으로서의 부칩(2)을 중첩시켜 접합한, 이른바 칩·온·칩 구조를 가지고 있다.This semiconductor device has a so-called chip-on-chip structure in which a sub chip 2 serving as a second semiconductor chip is superimposed and bonded to the surface 11 of the main chip 1 serving as a first semiconductor chip.
주칩(1) 및 부칩(2)은, 예를 들면 실리콘 칩으로 이루어져 있다.The main chip 1 and the sub chip 2 consist of silicon chips, for example.
주칩(1)의 표면(11)은, 주칩(1)의 기체를 이루는 반도체기판에 있어서 트랜지스터 등의 기능소자가 형성된 활성표층영역 측의 표면이다.The surface 11 of the main chip 1 is the surface on the side of the active surface region where functional elements such as transistors are formed in the semiconductor substrate forming the base of the main chip 1.
표면(11)의 가장 표면은, 예를 들면 질화실리콘으로 구성되는 표면보호막(도시하지 않음)으로 덮여 있다.The most surface of the surface 11 is covered with the surface protection film (not shown) which consists of silicon nitride, for example.
이 표면보호막 위에는, 예를 들면 중앙부에 부칩(2)의 접합영역(12)이 설정되어 있으며, 이 접합영역(12)에는, 부칩(2)과의 접속을 위한 복수개(본 실시형태에서는 6개)의 범프(BM)가 융기하여 형성되어 있다.On this surface protective film, for example, a junction region 12 of the subchip 2 is set in the center portion, and a plurality of junction regions 12 for connection with the subchip 2 (six in this embodiment) ) Bumps BM are formed to rise.
범프(BM)는, 예를 들면, 금, 백금, 은, 팔라듐 또는 이리듐 등의 내산화성 금속재료로 구성되어 있다.Bump BM is comprised from oxidation resistant metal materials, such as gold, platinum, silver, palladium, or iridium, for example.
또, 표면보호막 위에 있어서 접합영역(12)의 주위에는, 외부접속용의 복수의 패드(13)가 노출되어 배치되어 있다.Moreover, on the surface protection film, the pad 13 for external connection is exposed and arrange | positioned around the junction area | region 12. As shown in FIG.
부칩(2)은, 이 부칩(2)의 표면(21)을 주칩(1)의 표면(11)에 대향시킨, 소위 페이스다운방식으로 주칩(1)에 접합되어 있다.The sub chip 2 is joined to the main chip 1 in a so-called face down manner in which the surface 21 of the sub chip 2 is opposed to the surface 11 of the main chip 1.
부칩(2)의 표면(21)은, 부칩(2)의 기체를 이루는 반도체기판에 있어서 트랜지스터 등의 기능소자가 형성된 활성표층영역 측의 표면이다.The surface 21 of the sub chip 2 is a surface on the side of the active surface region where functional elements such as transistors are formed in the semiconductor substrate forming the base of the sub chip 2.
이 표면(21)의 가장 표면은, 예를 들면 질화실리콘으로 이루어지는 표면보호막(도시하지 않음)으로 덮여있다.The outermost surface of this surface 21 is covered with the surface protection film (not shown) which consists of silicon nitride, for example.
이 표면보호막 위에는, 주칩(1)의 범프(BM)에 대향하는 위치에 각각 범프(BS)가 형성되어 있다.On this surface protective film, bumps BS are formed at positions facing the bumps BM of the main chip 1, respectively.
범프(BS)는, 예를 들면, 금, 백금, 은, 팔라듐 또는 이리듐 등의 내 산화성 금속재료로 구성되어 있다.The bump BS is made of an oxidation resistant metal material such as gold, platinum, silver, palladium or iridium, for example.
부칩(2)은, 범프(BS)가 각각 대향하는 주칩(1)의 범프(BM)에 접속되는 것에 의해, 주칩(1)의 표면(11)과의 사이에 소정의 간격을 유지한 상태로 지지됨과 동시에 주칩(1)과 전기적으로 접속되어 있다.The sub chip 2 is connected to the bumps BM of the main chips 1 to which the bumps BS face each other, so that the sub chip 2 is maintained at a predetermined distance from the surface 11 of the main chips 1. It is supported and electrically connected to the main chip 1.
주칩(1)의 각 범프(BM)에는, 범프(BM)로부터 측방으로 뻗어서 접합영역(12)의 바깥쪽까지 인출된 연설부(14)가 일체로 형성되어 있다.Each bump BM of the main chip 1 is integrally formed with an uneven portion 14 extending laterally from the bump BM and drawn out to the outside of the junction region 12.
바꾸어 말하면, 주칩(1)의 범프(BM)는, 접합영역(12)의 경계부에 걸쳐진 상태로 길게 형성되어 있다.In other words, the bump BM of the main chip 1 is formed long in a state spanning the boundary of the junction region 12.
이에 의해, 주칩(1)과 부칩(2)이 접합된 후에 있어서도, 도 1에 나타내는 바와 같이, 연설부(14)의 접합영역(12) 바깥쪽으로 인출된 부분에 테스트 프로브(P)를 대고 주칩(1) 또는 부칩(2)만의 동작확인을 행할 수가 있다.As a result, even after the main chip 1 and the sub chip 2 are bonded together, as shown in FIG. 1, the main probe chip is placed on the portion drawn out of the bonding area 12 of the speaker 14. (1) Or the operation check of only the sub chip 2 can be performed.
또, 주칩(1)과 부칩(2)의 접속확인을 행할 수가 있다.In addition, the connection confirmation between the main chip 1 and the sub chip 2 can be performed.
또한, 주칩(1)의 외부접속용 패드(13)에 테스트 와이어를 접속시키거나, 또는 테스트 프로브를 대고, 이 반도체장치 전체의 동작확인을 행할 수도 있다.In addition, a test wire can be connected to the pad 13 for external connection of the main chip 1, or a test probe can be placed to check the operation of the entire semiconductor device.
또, 외부접속용 패드(13)는 범프(BM)와 직접적으로는 접속되어 있지 않아, 이 외부접속용 패드(13)에 테스트 프로브(P)를 대고 부칩(2)의 동작확인을 행할 수는 없다.In addition, the pad 13 for external connection is not directly connected to the bump BM. Therefore, the operation of the sub-chip 2 can be confirmed by applying the test probe P to the pad 13 for external connection. none.
또한, 이 반도체장치의 완성품에 있어서는, 예를 들면, 주칩(1)이 리드프레임의 아일랜드에 장착되며, 외부접속용 패드(13)가 본딩와이어에 의해 리드단자에 접속된다.In the finished product of the semiconductor device, for example, the main chip 1 is mounted on an island of the lead frame, and the external connection pad 13 is connected to the lead terminal by a bonding wire.
이상, 본 발명의 일실시형태에 대하여 설명하였으나, 본 발명은, 다른 형태로도 실시할 수 있다.As mentioned above, although one Embodiment of this invention was described, this invention can also be implemented with other aspects.
예를 들면, 주칩(1) 및 부칩(2)은, 모두 실리콘으로 이루어지는 칩인 것으로 하였으나, 실리콘 이외에도, 화합물 반도체(예를 들면, 갈륨비소 반도체 등)나 게르마늄 반도체 등의 다른 임의의 반도체재료를 사용한 반도체 칩이라도 좋다.For example, the main chip 1 and the sub chip 2 are all made of silicon, but in addition to silicon, other arbitrary semiconductor materials such as compound semiconductors (for example, gallium arsenide semiconductors) and germanium semiconductors are used. It may be a semiconductor chip.
이 경우에, 주칩(1)의 반도체재료와 부칩(2)의 반도체재료는, 동일하여도 좋고 상이하여도 좋다.In this case, the semiconductor material of the main chip 1 and the semiconductor material of the sub chip 2 may be the same or different.
이상, 본 발명의 실시형태에 대하여 상세히 설명하였으나, 이들은 본 발명의 기술적 내용을 밝히기 위해 사용된 구체적인 예에 불과하며, 본 발명은 이들 구체적인 예에 한정하여 해석될 수 없으며, 본 발명의 정신 및 범위는 첨부하는 청구범위에 의해서만 한정된다.As mentioned above, although embodiment of this invention was described in detail, these are only the specific examples used for illuminating the technical content of this invention, This invention cannot be interpreted limited to these specific examples, and the spirit and scope of this invention. Is only limited by the appended claims.
본 발명에 의하면, 제1의 반도체 칩의 범프에는, 일단이 제2의 반도체 칩의 접합영역 바깥까지 인출된 연설부가 접속되어 있다.According to the present invention, the speaker portion, one end of which is drawn out to the outside of the junction region of the second semiconductor chip, is connected to the bump of the first semiconductor chip.
이에 의해, 제1의 반도체 칩과 제2의 반도체 칩이 접합된 후에도, 연설부의 접합영역 바깥쪽으로 인출된 부분에 테스트 프로브를 대고, 제1의 반도체 칩 또는 제2의 반도체 칩만의 동작확인을 행할 수가 있다.Thus, even after the first semiconductor chip and the second semiconductor chip are joined, the test probe is placed on the portion drawn outward from the junction region of the speaker, and the operation confirmation of only the first semiconductor chip or the second semiconductor chip can be performed. There is a number.
또, 제1의 반도체 칩과 제2의 반도체 칩의 접속을 확인할 수가 있다.Moreover, the connection of a 1st semiconductor chip and a 2nd semiconductor chip can be confirmed.
Claims (7)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11-265741 | 1999-09-20 | ||
| JP26574199A JP3255896B2 (en) | 1999-09-20 | 1999-09-20 | Semiconductor device with chip-on-chip structure |
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| Publication Number | Publication Date |
|---|---|
| KR20010039902A true KR20010039902A (en) | 2001-05-15 |
| KR100752884B1 KR100752884B1 (en) | 2007-08-28 |
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| KR1020000054905A KR100752884B1 (en) | 1999-09-20 | 2000-09-19 | Semiconductor device of chip·on·chip structure |
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| JP (1) | JP3255896B2 (en) |
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| JP2007266078A (en) * | 2006-03-27 | 2007-10-11 | Fujitsu Ltd | Semiconductor device, semiconductor device of chip-on-chip structure, and process for manufacturing the semiconductor device |
| JP4910512B2 (en) * | 2006-06-30 | 2012-04-04 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| KR102190382B1 (en) | 2012-12-20 | 2020-12-11 | 삼성전자주식회사 | Semiconductor package |
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| JP2001094037A (en) | 2001-04-06 |
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