五、發明說明（1 ) 【發明所屬技術領域】 本發明係有關一種雙重晶片構造之半導體裝置。 【習知之技術】 以往之雙重晶片構造之半導體裝置，係於半導體晶片 (母晶片）表面與其他半導體晶片（子晶片）表面相對向之 狀態下予以重疊並接合。在這種雙$晶片構造之半導體裝 f中，於母晶片以及子晶片的表面形成有凸塊。藉由將子 曰曰片的凸塊接合至母晶片的凸塊，可使子晶片在與母晶片 隔有特疋間隔的狀您下接合，並達成母晶片以及子晶片間 的電性連接。 母晶片以及子晶片在相互接合之前，可分別在凸塊抵 接測試探針來進行用以確認動作之測試。此外，即使在母 日曰片以及子晶片相互接合後，仍可藉由在母晶片周圍附近 所叹置之外部連接用連接片抵接測試探針，來進行半導體 裝置全體動作確認的測試。然而，在母晶片以及子晶片相 互接合後，便無法只確認母晶片或是子晶片的動作。此外， 亦無法只確認母晶片.以及子晶片相互連接的狀態。 【發明所欲解決之問題】 本發明之第1目的在於提供一種雙重晶片構造之半導 體裝置，該裝置係即使在第1半導體晶片以及第2半導體 晶片相互接合後，仍可進行用以確認各半導體晶片單體之 功能的測試。 一此外，本發明之第2目的在於提供一種雙重晶片構造 之半導體裝置’該裝置係即使在第1半導體晶片以及第2 本紙張尺度適財國ii^cNS)A4 ⑽,ι™---—— 哪789 A7 ^-------— B7 ____ 五、發明說明（2 ) 半導體晶片相互接合後，仍可進行用以確認第丨半導體晶 片與第2半導體晶片相互連接的狀態之測試。 (請先閱讀背面之注意事項再填寫本頁) 本發明之第3目的在於提供一種適用於上述半導體裝 置之構造的半導體晶片。 本發明之半導體裝置係以第丨半導體晶片與第2半導 體晶片彼此表面相對向的狀態下重疊並接合之雙重晶片構 造的半導體裝置。該裝置包含：形成於上述第丨半導體晶 片表面上用以接合第2半導體晶片而設定之接合領域内， 且在隔有特定間隔狀態下將上述第丨半導體晶片以及第2 半導體晶片結合並達成上述第j半導體晶片以及第2半導 體晶片間之電性連接的凸塊；以及連接於上述第丨半導體 晶片表面之上述凸塊，且將一端拉出至上述接合領域外之 導電性延設部（最好與凸塊的材質相同）。 經濟部智慧財產局員工消費合作社印製 根據本發明，在第1半導體晶片的凸塊上連接有延設 部’其一端係拉出至第2半導體晶片的接合領域外。如此， 即使在第1半導體晶片以及第2半導體晶片相互接合後， 仍可於延設部之拉出至接合領域外之部分抵接測試探針， 以進行第丨半導體晶片或第2半導體晶片的動作確認。此 外，也可確認第1半導體晶片與第2半導體晶片相互連接 的狀態。 另外’上述延設部最好與上述凸塊一體成形。在此情 況下，上述凸塊亦可在橫跨上述接合領域邊界部的狀態下 形成，並將該凸塊與上述第2半導體晶片相接合之以外部 分作為上述延設部。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚） 2 311821 A7 五、發明說明（3 ) 本發明中之上述、或再其他目的、特徵以及效果可 參照所添付之圖面並透過以下實施型態的說明即可明瞭。 【發明之實施型態】 第！圖係本發明一實施型態之半導體裝置概略構造的 圖解剖視圖，而第2圖係其俯視圖。本發明之半導體裝置 係具有在作為第i半導體晶片之母晶片i的表面D上將 >作為第2半導體晶片之子晶片2相互重疊並接合之所謂雙 重晶片構造。 母晶片1以及子晶片2係由石夕晶片所構成。母晶片1 的表面11係於構成母晶片k基體的半導體基板上形成有 電:曰體等功能元件之活性表層領域侧的表面。在表面η 的取表面，覆蓋著例如氮化石夕所構成之表面保護膜（未圖 不）。在該表面保護膜上，例如於中央部設定有子晶片2 的接合領域12,在該接合領域12則隆起形成有複數個凸 塊腿（本實施型態中有6個）以連接子晶片2。凸塊隨 係由例如金、鉑、銀、鈀或銥等耐氧化性金屬材質所構成。 此外’在表面保護膜上之接合領域的周圍，露出複數個與 外部連接用之晶片架1 3。 子晶片2係以子晶片2的表面21與母晶片j的表面 11相對向之所謂面朝下之方式接合於母晶片〗。子晶片： 的表面21係於構成子晶片2之基體的半導體基板上形成有 電：體等功能元件之活性表層領域側的表面。在該表面Η 的取表面，覆蓋著例如氮化矽所構成之表面保護膜（未圖 二。在該表^於母晶片丨之凸塊_的相對位 ‘張尺叹· r關冢標準（CNS)A4規格（2ig χ挪公髮)---^ (請先閱讀背面之注音？事項再填寫本頁) ;裝--------訂· 線· 經 濟 部 智 慧 財 產 局 員 消 費 合 社 印 Μ 311821 490789 A7 B7 五、發明說明（4 ) 置分別形成有凸塊BS。凸堍 〇视BS係由金、鉑、銀、鈀或銥 等耐氧化性金屬材質所構成。V. Description of the Invention (1) [Technical Field of the Invention] The present invention relates to a semiconductor device having a dual wafer structure. [Known technology] Conventional semiconductor devices with dual wafer structures are superimposed and bonded in a state where the surface of the semiconductor wafer (mother wafer) and the surface of other semiconductor wafers (sub wafers) face each other. In such a semiconductor device having a dual wafer structure, bumps are formed on the surfaces of the mother wafer and the daughter wafer. By bonding the bumps of the daughter wafer to the bumps of the mother wafer, the daughter wafers can be bonded with a special distance from the mother wafer, and the electrical connection between the mother wafer and the daughter wafer can be achieved. Before the mother wafer and the daughter wafer are bonded to each other, a test can be performed by abutting the test probes on the bumps to confirm the operation. In addition, even after the mother day chip and the daughter chip are bonded to each other, the test of the overall operation of the semiconductor device can be performed by abutting the test probes on the external connection tabs near the mother chip. However, after the mother wafer and the daughter wafer are bonded to each other, it is not possible to confirm only the operation of the mother wafer or the daughter wafer. In addition, it is not possible to confirm only the state of the mother chip and the daughter chip connected to each other. [Problems to be Solved by the Invention] A first object of the present invention is to provide a semiconductor device having a dual wafer structure. The device can be used to confirm each semiconductor even after the first semiconductor wafer and the second semiconductor wafer are bonded to each other. Test of the function of the chip. In addition, a second object of the present invention is to provide a semiconductor device having a dual wafer structure. The device is a semiconductor device having a dual wafer structure. — Which 789 A7 ^ -------— B7 ____ 5. Description of the invention (2) After the semiconductor wafers are bonded to each other, a test for confirming the state of the interconnection between the first semiconductor wafer and the second semiconductor wafer can still be performed. (Please read the precautions on the back before filling this page.) The third object of the present invention is to provide a semiconductor wafer having a structure suitable for the above-mentioned semiconductor device. The semiconductor device of the present invention is a semiconductor device having a dual wafer structure in which the first semiconductor wafer and the second semiconductor wafer face each other with their surfaces facing each other. The device includes: forming a bonding area set on the surface of the second semiconductor wafer for bonding the second semiconductor wafer; and combining the second semiconductor wafer and the second semiconductor wafer under a certain interval to achieve the above A bump for electrical connection between the j-th semiconductor wafer and the second semiconductor wafer; and a conductive extension (most It's the same material as the bump). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs According to the present invention, an extension portion is connected to the bump of the first semiconductor wafer, and one end thereof is pulled out of the bonding area of the second semiconductor wafer. In this way, even after the first semiconductor wafer and the second semiconductor wafer are bonded to each other, the test probe can still be abutted on the portion of the extension portion that is out of the bonding area to perform the first semiconductor wafer or the second semiconductor wafer. Action confirmation. In addition, the state where the first semiconductor wafer and the second semiconductor wafer are connected to each other can also be confirmed. It is preferable that the extension portion is formed integrally with the bump. In this case, the bump may be formed in a state that crosses the boundary portion of the bonding area, and an external portion where the bump is bonded to the second semiconductor wafer may be used as the extension portion. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 Gongchu) 2 311821 A7 V. Description of the invention (3) For the above, or other purposes, features and effects in the present invention, please refer to the attached drawings It will be clear through the description of the following implementation types. [Implementation Mode of Invention] No.! The figure is an exploded view of a schematic structure of a semiconductor device according to an embodiment of the present invention, and the second figure is a plan view thereof. The semiconductor device of the present invention has a so-called double-wafer structure in which > sub-wafers 2 as second semiconductor wafers are superimposed on each other on the surface D of the mother wafer i as the i-th semiconductor wafer. The mother wafer 1 and the daughter wafer 2 are composed of Shi Xi wafers. The surface 11 of the mother wafer 1 is a surface of the active surface layer side of a functional element such as a body formed on a semiconductor substrate constituting the mother substrate k base. The surface η is covered with a surface protective film (not shown) made of, for example, a nitride stone. On this surface protection film, for example, a bonding region 12 of the sub wafer 2 is set at the center, and a plurality of bump legs (six in this embodiment) are formed in the bonding region 12 to connect the sub wafer 2. . The bumps are made of an oxidation-resistant metal material such as gold, platinum, silver, palladium, or iridium. In addition, a plurality of wafer holders 13 for external connection are exposed around the bonding area on the surface protective film. The daughter wafer 2 is bonded to the mother wafer in a so-called face-down manner in which the surface 21 of the daughter wafer 2 and the surface 11 of the mother wafer j face each other. The surface 21 of the sub-wafer: is the surface on the active surface layer side of the semiconductor substrate constituting the base of the sub-wafer 2 on which functional elements such as electricity: bodies are formed. The surface of this surface Η is covered with a surface protection film made of, for example, silicon nitride (not shown in Figure 2. In this table, the relative position of the bump _ on the mother wafer 丨 Zhang Zhitan · r Guanzui standard ( CNS) A4 specification (2ig χ Norwegian public hair) --- ^ (Please read the phonetic on the back? Matters and then fill out this page); install -------- order · line · the Intellectual Property Bureau of the Ministry of Economic Affairs consumer spending Press M 311821 490789 A7 B7 V. Description of the invention (4) Bumps BS are formed respectively. The bump BS 0 is made of oxidation resistant metal materials such as gold, platinum, silver, palladium or iridium.
再風子日日片2係错由將凸塊BS 分別連接至相對向的母晶Η (請先閱讀背面之注意事項再填寫本頁) J刃甘日日片1的凸塊BM，而可在與母晶 片1的表面11之間以維持特定間隔的狀態下支撐，並與母 晶片1電性連接。 在母晶片1的各個凸塊BM 一體形成有延設部14，以 延伸於凸塊BM的側方並拉出至接合領域12外。換言之， 母晶片1之凸塊BM係以橫跨接合領域12邊界部的狀態形 成長條形。如此，如第！圖所示’即使在母晶片丄以及子 晶片2相互接合後，也可在延設部14之拉出至接合領域 12外的部分上抵接測試探針p，以進行母晶片〗或子晶片 2的動作確認’而且可進行母晶片i以及子晶片2彼此連 接之確認。 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 再者’亦可在母晶片i的外部連接用晶片架13連接測 試引線’或是抵接測試探針以進行半導體裝置全體的動作 確〜另外，外部連接用晶片架13並不直接與凸塊BM連 接，故無法在外部連接用晶片架13抵接測試探針來進行子 晶片2的動作確認。此外，半導體裝置的成品中，例如係 母晶片1固定於導架的島狀物，而外部連接用晶片架13 則利用引線搭接而連接於導線端子。 雖然已經說明本發明之一實施型態，但本發明也可以 其他型態實施。例如，母晶片丨以及子晷片2均是由矽所 構成的晶片，但除了矽之外，也可以係使用化合物半導體 _(例如砰化嫁半導體等）或是鍺半導體等其他任意半導體 311821 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）'------- 49Q789 A7 B7 五、發明說明（5 ) 材料之半導體晶片。在此情況下，母晶片1的半導體材料 和子晶片2的半導體材料可相同，也可相異。 雖然已經詳細說明本發明之實施型態，但這只不過係 為了說明本發明之技術性内容所提出的具體實施例，本發 明並不限於這些具體實施例，本發明的精神以及範圍僅由 所添附之申請專利範圍所限定。 I 本申請案係與1999年9月20日在日本國特許廳所提 出之特願平11-265741號相對應，本申請案之所有揭示皆 係從當中引用來歸納形成。 【圖面之簡單說明】 第1圖為本發明一實施型態之半導體裝置概略構造的 圖解剖視圖。 第2圖為上述半導體裝置的俯視圖。 【符號之說明】 (請先閱讀背面之注意事項再填寫本頁) ί 言· r 經濟部智慧財產局員工消費合作社印製 1 母晶片 2 子晶片 11 表面 12 接合領域 13 外部連接用晶片架 14 延設部 21 表面 BM 凸塊 BS 凸塊 P 測試探針 311821 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Zaifengzi Rizhi Pian 2 is made by connecting the bump BS to the opposite mother crystal. (Please read the precautions on the back before filling this page.) It is supported with a certain distance from the surface 11 of the mother wafer 1 and is electrically connected to the mother wafer 1. An extension portion 14 is integrally formed on each bump BM of the mother wafer 1 so as to extend to the side of the bump BM and is pulled out of the bonding area 12. In other words, the bumps BM of the mother wafer 1 are formed in a strip shape in a state of crossing the boundary portion of the bonding region 12. So, as first! As shown in the figure, even after the mother wafer 丄 and the daughter wafer 2 are bonded to each other, the test probe p can be abutted on the portion of the extension portion 14 that is pulled out of the bonding area 12 to perform the mother wafer or the daughter wafer. 2 Operation Confirmation 'Furthermore, it is possible to confirm that the mother wafer i and the daughter wafer 2 are connected to each other. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs.“ Also, test leads can be connected to the chip holder 13 for external connection of the mother chip i ”or contact the test probes to confirm the operation of the entire semiconductor device. Since the wafer holder 13 is not directly connected to the bump BM, the wafer holder 13 for external connection cannot contact the test probes to confirm the operation of the sub wafer 2. In the finished semiconductor device, for example, the mother wafer 1 is fixed to an island of a guide frame, and the external connection wafer holder 13 is connected to a lead terminal by wire bonding. Although one embodiment of the present invention has been described, the present invention may be implemented in other forms. For example, both the mother wafer and daughter wafer 2 are wafers made of silicon, but in addition to silicon, compound semiconductors (such as semiconductors) or germanium semiconductors can also be used. Paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) '------- 49Q789 A7 B7 V. Description of the invention (5) Semiconductor wafer of material. In this case, the semiconductor material of the mother wafer 1 and the semiconductor material of the daughter wafer 2 may be the same or different. Although the implementation mode of the present invention has been described in detail, this is only a specific embodiment proposed for explaining the technical content of the present invention, and the present invention is not limited to these specific embodiments. The spirit and scope of the present invention are only limited by The scope of the attached patent application is limited. I This application corresponds to Japanese Patent Application No. 11-265741, filed at the Japan Patent Office on September 20, 1999. All the disclosures in this application are incorporated by reference. [Brief Description of Drawings] FIG. 1 is an exploded view of a schematic structure of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a plan view of the semiconductor device. [Explanation of Symbols] (Please read the precautions on the back before filling out this page) ί Words r Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 Mother wafer 2 Daughter wafer 11 Surface 12 Joint area 13 Wafer holder for external connection 14 Extension 21 Surface BM Bump BS Bump P Test Probe 311821 The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm)