JPH07211758A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH07211758A JPH07211758A JP6002506A JP250694A JPH07211758A JP H07211758 A JPH07211758 A JP H07211758A JP 6002506 A JP6002506 A JP 6002506A JP 250694 A JP250694 A JP 250694A JP H07211758 A JPH07211758 A JP H07211758A
- Authority
- JP
- Japan
- Prior art keywords
- elements
- bump
- bonding
- semiconductor device
- control layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01077—Iridium [Ir]
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
係り, 特に, 半導体チップのバンプ接合の際のチップの
良否選別方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of selecting a chip quality in bump bonding of a semiconductor chip.
【０００２】具体的には，本発明はIRFPA (Infra-Red F
ocal Plane Array) において，シリコン(Si)チップ上に
赤外センサ部の化合物半導体素子をバンプ接合する際の
チップの良否選別方法に利用できる。Specifically, the present invention is based on the IRFPA (Infra-Red F
In the ocal plane array, it can be used as a chip pass / fail selection method when bump-bonding the compound semiconductor element of the infrared sensor section onto the silicon (Si) chip.
【０００３】[0003]
【従来の技術】赤外センサ部の化合物素子とその信号処
理回路が形成されたSiチップとのバンプ間の接合は通常
フリップチップボンディングにより行われている。2. Description of the Related Art Bonding between a bump of a compound element of an infrared sensor part and a Si chip having a signal processing circuit thereof is usually performed by flip chip bonding.
【０００４】まず, Siウエハ上に形成された信号処理回
路チップのプロービング検査を行い, 良品チップのバン
プ上に赤外センサ部の化合物半導体素子をフリップチッ
プボンディングによりバンプ接合している。First, a probing test of a signal processing circuit chip formed on a Si wafer is performed, and a compound semiconductor element of an infrared sensor section is bump-bonded to a bump of a non-defective chip by flip chip bonding.
【０００５】[0005]
【発明が解決しようとする課題】従来例では，素子間が
バンプ接合により完全に接合されているため，赤外セン
サ部の化合物半導体素子が不良の場合にはSi素子が良品
であっても素子全体が不良となってしまい, 歩留が著し
く低下する。In the conventional example, since the elements are completely bonded by bump bonding, if the compound semiconductor element of the infrared sensor part is defective, the element can be a good element even if the Si element is a good product. The whole becomes defective and the yield decreases significantly.
【０００６】このため, 赤外センサ部の化合物半導体素
子の電子ビームによる診断が試みられているが，その評
価設備が高価であり, また, まだその技術は確立されて
いない。For this reason, the diagnosis of the compound semiconductor element of the infrared sensor section by an electron beam has been attempted, but its evaluation equipment is expensive and its technique has not been established yet.
【０００７】本発明は，２つの素子をバンプ接合する際
に，高価な評価装置を必要としないで素子選別をできに
ようにし，良品素子の回収により製造歩留を向上するこ
とを目的とする。It is an object of the present invention to improve the production yield by recovering non-defective elements by enabling element selection without the need for an expensive evaluation device when bump-joining two elements. .
【０００８】[0008]
上記課題の解決は (図１参照） １）２つの素子間(1),(2) をフリップチップボンディン
グによりバンプ接合する際に，該２つの素子の少なくと
も一方に接合前の該バンプの高さより小さく且つ接合後
の該バンプの高さより大きい厚さを有するバンプ接合圧
の制御層(3）を設け，該制御層に接するまで該２つの素
子間を加圧して特性チェックを行って素子全体の良否を
選別し，該制御層を除去後に該２つの素子間を再加圧し
てバンプの接合力を強化する半導体装置の製造方法，あ
るいは ２）前記制御層は前記バンプより硬度が高いことを特徴
とする前記１）記載の半導体装置の製造方法，あるい
は， ３）前記特性チェック後に良品の素子同士を再加圧する
ことを特徴とする前記１）記載記載の半導体装置の製造
方法，あるいは ４）前記２つの素子はセンサと信号処理回路であること
を特徴とする前記１）記載の半導体装置の製造方法，あ
るいは ５）前記バンプはインジウムからなり，前記制御層はポ
リイミド膜からなることを特徴とする前記１）記載の半
導体装置の製造方法により達成される。The solution to the above problems is (see Fig. 1). 1) When two elements (1) and (2) are bump-bonded by flip-chip bonding, the height of the bump before bonding to at least one of the two elements A bump bonding pressure control layer (3) having a small size and a thickness larger than the height of the bump after bonding is provided, and a characteristic check is performed by pressurizing between the two elements until contacting the control layer. A method of manufacturing a semiconductor device in which good or bad is selected, and after the control layer is removed, the pressure between the two elements is re-pressed to enhance the bonding force of the bump, or 2) the control layer has a hardness higher than that of the bump. 1) The method for manufacturing a semiconductor device according to 1), or 3) The method for manufacturing a semiconductor device according to 1), wherein the non-defective elements are repressurized after the characteristic check, or 4) Two elements Is a sensor and a signal processing circuit, or 5) the method for manufacturing a semiconductor device according to 1), or 5) the bump is made of indium and the control layer is made of a polyimide film. This is achieved by the semiconductor device manufacturing method described.
【０００９】[0009]
【作用】図１(A) 〜(D) は本発明の原理説明図である。
図１(A) において， 1は化合物半導体素子, 1Aは化合物
半導体素子のバンプ,2は信号処理回路チップを形成した
Siウエハ, 2Aは信号処理回路チップのバンプ, 3はバン
プ接合圧制御層でポリイミド層, 4は特性測定のための
信号の取り出し電極である。1 (A) to 1 (D) are explanatory views of the principle of the present invention.
In FIG. 1 (A), 1 is a compound semiconductor device, 1A is a bump of the compound semiconductor device, and 2 is a signal processing circuit chip.
Si wafer, 2A is a bump of a signal processing circuit chip, 3 is a bump bonding pressure control layer and a polyimide layer, and 4 is a signal extraction electrode for characteristic measurement.
【００１０】図１(B) において，化合物半導体素子 1を
Siウエハ 2上に載せ, バンプ接合圧制御層 3に当たるま
でバンプ同士を押しつけて (仮ボンディング) ，プロー
ブ 5により化合物半導体素子の特性を測り, その良否を
選別する。In FIG. 1B, the compound semiconductor device 1 is
It is placed on a Si wafer 2, the bumps are pressed against each other until they reach the bump bonding pressure control layer 3 (temporary bonding), the characteristics of the compound semiconductor element are measured by the probe 5, and the quality is selected.
【００１１】図１(C) において，バンプ接合圧制御層 3
を除去し，不良の化合物半導体素子を剥離する。剥離後
の良品のSiチップ上には新しい化合物半導体素子 1を仮
ボンディングして特性チェックして選別を繰り返す。In FIG. 1C, the bump bonding pressure control layer 3
Are removed, and the defective compound semiconductor element is peeled off. A new compound semiconductor element 1 is provisionally bonded on the non-defective Si chip after peeling, characteristics are checked, and selection is repeated.
【００１２】図１(D) において，良品の化合物半導体素
子 1の再加圧を行いバンプ接合を完成させる。本発明で
は，バンプ接合の強度をコントロールして素子の剥離を
可能とすることにより, 両方の素子の回収を行ってい
る。特にIRFPA の場合には，良品のSi素子上に赤外セン
サ部の化合物半導体素子を, 剥離を可能とする程度に弱
く接合して検査を行い, 検査結果が不良の場合は赤外素
子を剥離して良品のSi素子を回収している。In FIG. 1D, the non-defective compound semiconductor element 1 is repressurized to complete bump bonding. In the present invention, both elements are collected by controlling the strength of bump bonding to enable the elements to be separated. Particularly in the case of IRFPA, the compound semiconductor element of the infrared sensor is weakly bonded to a non-defective Si element to the extent that peeling is possible, and the inspection is performed. If the inspection result is poor, the infrared element is peeled off. Then, the good Si elements are collected.
【００１３】バンプ接合の強度をコントロールする方法
として，チップ間に接合前のバンプ高さより薄く, 接合
後のバンプ高さより厚く, 且つバンプより硬い材料から
なるバンプ接合圧制御層を設ける。制御層の材質と厚さ
をこのようにすることにより, ２つの素子間にバンプを
介してオーミック接触が得られ, しかも該２つの素子が
剥離可能な接合力が得られるようにコントロールでき
る。As a method of controlling the strength of bump bonding, a bump bonding pressure control layer made of a material that is thinner than the bump height before bonding, thicker than the bump height after bonding, and harder than the bump is provided between the chips. By controlling the material and thickness of the control layer as described above, ohmic contact can be obtained between the two elements via the bumps, and further, the bonding force can be controlled so that the two elements can be separated.
【００１４】ボンディングの際に両素子が接近するとこ
のバンプ接合圧制御層により両素子の接近は止まること
によりバンプ押圧をコントロールでき, その結果バンプ
接触部はオーミック接触が得られ且つ剥離が容易な接触
圧になる。When both elements come close to each other during bonding, the bump bonding pressure control layer stops the approach of both elements, so that the bump pressing can be controlled, and as a result, the bump contact portion can obtain ohmic contact and can be easily peeled off. It becomes pressure.
【００１５】[0015]
【実施例】図２(A) 〜(F) は本発明の実施例の説明図で
ある。図２(A) において，信号処理回路のチップを形成
したSiウエハ 2上に, また図２(C) に示される化合物半
導体素子 1上に各々高さ10μｍのインジウム(In)バンプ
2A, 1Aを形成する。EXAMPLE FIGS. 2A to 2F are explanatory views of an example of the present invention. In FIG. 2 (A), indium (In) bumps each having a height of 10 μm are formed on the Si wafer 2 on which the chip of the signal processing circuit is formed and on the compound semiconductor device 1 shown in FIG. 2 (C).
Form 2A, 1A.
【００１６】図２(B) において，信号処理回路のチップ
を形成したSiウエハ 2上にポリイミド膜を厚さ19μｍ塗
布して, バンプ間の空洞部にバンプ接合圧制御層 3をパ
ターン化して形成する。In FIG. 2 (B), a polyimide film is applied on a Si wafer 2 on which a chip for a signal processing circuit is formed with a thickness of 19 μm, and a bump bonding pressure control layer 3 is patterned in a cavity between bumps. To do.
【００１７】図２(C) において，フリップチップボンダ
の赤外透過により，化合物半導体素子 1と信号処理回路
のチップを形成したSiウエハ 2との位置合わせを行い,
化合物半導体素子 1がバンプ接合圧制御層 3に接触する
まで加圧して仮ボンディングを行う。In FIG. 2C, the compound semiconductor element 1 and the Si wafer 2 on which the chip of the signal processing circuit is formed are aligned by infrared transmission of a flip chip bonder,
Temporary bonding is performed by pressing until the compound semiconductor device 1 contacts the bump bonding pressure control layer 3.
【００１８】この場合前記のように, Siウエハにおいて
は, 良品の信号処理回路のチップ上にのみ化合物半導体
素子を接合する。次いで，プローバ 5を取り出し電極 4
に接触させて，両素子ボンディング後の特性を測り, 化
合物半導体素子 1の良否の選択を行う。前記のIRFPA に
おいては低温状態での二次元の映像チェックにより，化
合物半導体素子 1の出力や駆動電源の接続等をチェック
する。In this case, as described above, in the Si wafer, the compound semiconductor element is bonded only on the chip of the non-defective signal processing circuit. Then take out the prober 5 and remove the electrode 4
Then, the characteristics after bonding both elements are measured and the quality of the compound semiconductor element 1 is selected. In the above-mentioned IRFPA, the output of the compound semiconductor device 1 and the connection of the driving power supply are checked by a two-dimensional image check at low temperature.
【００１９】図２(D) において，バンプ接合圧制御層 3
のポリイミド樹脂を除去液に浸漬して除去する。除去液
は，例えば, PIQ エッチャント (日立化成) を用いる。In FIG. 2D, the bump bonding pressure control layer 3
The polyimide resin of is immersed in a removing solution and removed. For example, PIQ etchant (Hitachi Kasei) is used as the removing liquid.
【００２０】図２(E) において，信号処理回路のチップ
を形成したSiウエハ上の不良箇所の化合物半導体素子 1
を真空吸引して剥離除去する。図２(F) において，Siウ
エハ上の良品箇所の化合物半導体素子 1を再加圧して接
合力を強化する。In FIG. 2 (E), the compound semiconductor device 1 at the defective portion on the Si wafer on which the chip of the signal processing circuit is formed 1
Is vacuum-sucked and removed. In Fig. 2 (F), the compound semiconductor device 1 at the non-defective part on the Si wafer is repressurized to strengthen the bonding force.
【００２１】なお，不良箇所には別の化合物半導体素子
を仮ボンディングして特性チェックを行い, 良品であれ
ば再加圧して接合力を強化する。上記の過程を終了し
て，ウエハ上に良品の化合物半導体素子が多数存在した
状態になる。このウエハをダイシングしてチップに分割
する。Incidentally, another compound semiconductor element is temporarily bonded to the defective portion to check the characteristics, and if it is a non-defective portion, it is re-pressed to strengthen the bonding force. After the above process is completed, a large number of non-defective compound semiconductor devices are present on the wafer. This wafer is diced and divided into chips.
【００２２】実施例では，バンプ接合圧制御層としてパ
ターン化されたポリイミド層を用いたが，チップの四隅
等に独立して制御層を設けてもよい。また，バンプ接合
圧制御層としてポリイミド層を用いたが，バンプより硬
度が高く且つ剥離が容易な他の樹脂等を用いてもよい。Although the patterned polyimide layer is used as the bump bonding pressure control layer in the embodiment, the control layer may be provided independently at the four corners of the chip. Further, although the polyimide layer is used as the bump bonding pressure control layer, another resin or the like having a higher hardness than the bump and being easily peeled may be used.
【００２３】[0023]
【発明の効果】本発明によれば, 次のような効果が得ら
れる。 (1) 高価な評価装置を必要としないで，素子選別ができ
る。 (2) 素子の回収により，製造歩留が向上する。 (3）IRFPA においては，Siウエハ上に良品の化合物半導
体素子を大量に接合することができ, 量産化とコストダ
ウンが可能となる。According to the present invention, the following effects can be obtained. (1) It is possible to select devices without the need for expensive evaluation equipment. (2) The production yield is improved by collecting the elements. (3) In IRFPA, a large number of non-defective compound semiconductor elements can be bonded on a Si wafer, which enables mass production and cost reduction.
【図１】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.
【図２】 本発明の実施例の説明図FIG. 2 is an explanatory diagram of an embodiment of the present invention.
1 化合物半導体素子 1A 化合物半導体素子のバンプ 2 信号処理回路のチップを形成したSiウエハ 2A 信号処理回路のチップのバンプ 3 バンプ接合圧制御層でポリイミド層 4 特性測定のための信号の取り出し電極 5 プローブ 1 Compound semiconductor device 1A Compound semiconductor device bump 2 Si wafer on which signal processing circuit chip is formed 2A Signal processing circuit chip bump 3 Polyimide layer at bump bonding pressure control layer 4 Signal extraction electrode for characteristics measurement 5 Probe
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 25/18 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication H01L 25/18
Claims (5)
ボンディングによりバンプ接合する際に，該２つの素子
の少なくとも一方に接合前の該バンプの高さより小さく
且つ接合後の該バンプの高さより大きい厚さを有するバ
ンプ接合圧の制御層(3）を設け，該制御層に接するまで
該２つの素子間を加圧して特性チェックを行って素子全
体の良否を選別し，該制御層を除去後に該２つの素子間
を再加圧してバンプの接合力を強化することを特徴とす
る半導体装置の製造方法。1. When bump bonding between two elements (1), (2) by flip chip bonding, the bump is smaller than the height of the bump before bonding to at least one of the two elements and the bump after bonding. A bump bonding pressure control layer (3) having a thickness larger than the height of the device is provided, and a pressure is applied between the two devices until the control layer is contacted to perform a characteristic check to select whether the entire device is good or bad. A method of manufacturing a semiconductor device, characterized in that after the layer is removed, the bonding force of the bump is strengthened by re-pressurizing between the two elements.
ことを特徴とする請求項１記載の半導体装置の製造方
法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the control layer has a hardness higher than that of the bump.
再加圧することを特徴とする請求項１記載の半導体装置
の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein non-defective devices are repressurized after the characteristic check.
であることを特徴とする請求項１記載の半導体装置の製
造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein the two elements are a sensor and a signal processing circuit.
制御層はポリイミド膜からなることを特徴とする請求項
１記載の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 1, wherein the bump is made of indium and the control layer is made of a polyimide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6002506A JPH07211758A (en) | 1994-01-14 | 1994-01-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6002506A JPH07211758A (en) | 1994-01-14 | 1994-01-14 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07211758A true JPH07211758A (en) | 1995-08-11 |
Family
ID=11531259
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6002506A Withdrawn JPH07211758A (en) | 1994-01-14 | 1994-01-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07211758A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6483190B1 (en) | 1999-10-20 | 2002-11-19 | Fujitsu Limited | Semiconductor chip element, semiconductor chip element mounting structure, semiconductor chip element mounting device and mounting method |
| US7112468B2 (en) | 1998-09-25 | 2006-09-26 | Stmicroelectronics, Inc. | Stacked multi-component integrated circuit microprocessor |
| JP2007173637A (en) * | 2005-12-22 | 2007-07-05 | Matsushita Electric Works Ltd | Sensor module |
| KR100752884B1 (en) * | 1999-09-20 | 2007-08-28 | 로무 가부시키가이샤 | Semiconductor device of chip·on·chip structure |
| CN109877479A (en) * | 2019-03-29 | 2019-06-14 | 中国科学院上海技术物理研究所 | A kind of two step inverse bonding process of focus planar detector |
-
1994
- 1994-01-14 JP JP6002506A patent/JPH07211758A/en not_active Withdrawn
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7112468B2 (en) | 1998-09-25 | 2006-09-26 | Stmicroelectronics, Inc. | Stacked multi-component integrated circuit microprocessor |
| KR100752884B1 (en) * | 1999-09-20 | 2007-08-28 | 로무 가부시키가이샤 | Semiconductor device of chip·on·chip structure |
| US6483190B1 (en) | 1999-10-20 | 2002-11-19 | Fujitsu Limited | Semiconductor chip element, semiconductor chip element mounting structure, semiconductor chip element mounting device and mounting method |
| US7436062B2 (en) | 1999-10-20 | 2008-10-14 | Fujitsu Limited | Semiconductor chip element, semiconductor chip element mounting structure, semiconductor chip element mounting device and mounting method |
| JP2007173637A (en) * | 2005-12-22 | 2007-07-05 | Matsushita Electric Works Ltd | Sensor module |
| JP4715503B2 (en) * | 2005-12-22 | 2011-07-06 | パナソニック電工株式会社 | Manufacturing method of sensor module |
| CN109877479A (en) * | 2019-03-29 | 2019-06-14 | 中国科学院上海技术物理研究所 | A kind of two step inverse bonding process of focus planar detector |
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