JPH06151701A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH06151701A
JPH06151701A JP29851592A JP29851592A JPH06151701A JP H06151701 A JPH06151701 A JP H06151701A JP 29851592 A JP29851592 A JP 29851592A JP 29851592 A JP29851592 A JP 29851592A JP H06151701 A JPH06151701 A JP H06151701A
Authority
JP
Japan
Prior art keywords
chip
semiconductor
semiconductor substrate
wafer
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29851592A
Other languages
Japanese (ja)
Inventor
Akiteru Rai
明照 頼
Original Assignee
Sharp Corp
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp, シャープ株式会社 filed Critical Sharp Corp
Priority to JP29851592A priority Critical patent/JPH06151701A/en
Publication of JPH06151701A publication Critical patent/JPH06151701A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

Abstract

(57) [Summary] [Object] To provide a method for manufacturing a semiconductor device, which has excellent mass productivity and can reduce the manufacturing cost of a chip-on-chip device. [Structure] A semiconductor chip 1 is mounted on a plurality of semiconductor substrates 2 in a wafer state before being individually cut, and then the semiconductor substrate 2 is individually cut.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a semiconductor chip mounted on a semiconductor substrate.

[0002]

2. Description of the Related Art In recent years, development of a chip-on-chip mounting technique for manufacturing a chip-on-chip device which is a semiconductor device in which semiconductor chips 21 and 31 are mounted on semiconductor substrates 22 and 32 as shown in FIGS. Is being actively conducted.

The chip-on-chip device shown in FIG.
This is a chip-on-chip device in which the semiconductor chip 21 is connected to the semiconductor substrate 22 via the solder bumps 23 using the flip chip bonding technique.

Further, the chip-on-chip device shown in FIG. 3 uses the wire bonding technique to form the wire 35.
It is a chip-on-chip device in which the semiconductor chip 31 is connected to the semiconductor substrate 32 via the.

This chip-on-chip mounting technique has features that it is easy to mount a large-sized chip, has excellent reliability, and is easy to have multiple functions, large capacity, and high density. , Is highly expected as a next-generation high-density mounting technology.

The fabrication and packaging of the chip-on-chip device shown in FIG. 2 are generally performed in the order shown in (i) to (v) below. (i) The bumped semiconductor chip 21 is manufactured. (ii) Semiconductor substrate 22 having bonding pad 24
To make. (iii) The semiconductor chips 21 are flip-chip bonded onto the individual semiconductor substrates 22 after dicing. (iv) An electrical test is performed, and if the semiconductor chip 21 is defective, the semiconductor chip 21 is repaired. If necessary, resin is injected into the interface between the semiconductor chip 21 and the semiconductor substrate 22 to complete the production of the chip-on-chip device. (v) Packaging chip-on-chip devices.

[0007]

[Problems to be Solved by the Invention]
When the chip-on-chip device is manufactured by the method as described above, the flux coating, the temporary bonding of the semiconductor chips 21, and the reflow are applied to each semiconductor substrate 22.
Since it is necessary to carry out steps such as flux cleaning and testing, there is a problem that mass productivity is poor and the cost increases in total.

Also, in the wire bonding method, the die bonding step and the test step must be carried out for each semiconductor substrate 32, and there is a problem in mass productivity.

Therefore, an object of the present invention is to have excellent mass productivity,
It is an object of the present invention to provide a semiconductor device manufacturing method capable of reducing the manufacturing cost of a chip-on-chip device.

[0010]

In order to achieve the above object, the present invention is a method of manufacturing a semiconductor device including a semiconductor substrate and a semiconductor chip mounted on the semiconductor substrate. The semiconductor chip is mounted on a plurality of semiconductor substrates in the wafer state, and then the semiconductor substrates are individually cut.

[0011]

According to the present invention, since semiconductor chips are mounted on a plurality of semiconductor substrates in a wafer state, a flux applying step, a reflow step, a flux cleaning step, a test step, etc., which are conventionally performed for each individual semiconductor substrate. Can be performed on a wafer-by-wafer basis, so that the number of steps required for one semiconductor substrate can be significantly reduced.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on the illustrated embodiments.

FIG. 1 shows an embodiment of a method of manufacturing a semiconductor device according to the present invention. The above embodiment will be described with reference to FIGS. 1A, 1B, 1C, 1D and 1E in order.

The wafer 6 shown in FIG. 1A includes a large number of semiconductor substrates 2. The semiconductor substrate 2 includes a bonding pad portion 4. The bonding pad section 4 is
It contains a metal layer which is wetted by solder, such as Cu or Au.

As shown in FIG. 1B, the flux 7 is applied to the bonding pad portion 4 of the wafer 6 by, for example, transfer, stamping, dispenser or the like. Next, as shown in FIG. 1C, the semiconductor chip 1 including the solder bumps 3 is placed on each semiconductor substrate 2 included in the wafer 6 by using a flip chip bonder. At this time, the solder bumps 3 are temporarily adhered to the bonding pad portion 4 of the semiconductor substrate 2 by the adhesive force of the flux.

Next, the wafer 6 and the semiconductor chip 1 described above.
Is passed through a reflow furnace whose maximum temperature is higher than the melting point of solder to melt the solder bumps 3 and connect the semiconductor chip 1 and the wafer 6. After that, the flux residue is removed by solvent cleaning (see FIG. 1D). Finally, each formed semiconductor chip 1 is electrically tested, and if the chip 1 is defective, the defective chip is removed, and the steps from flux coating to the step are repeated again. If there is no defect, the chip-on-chip devices including the semiconductor chip 1 and the semiconductor substrate 2 are individually diced (see FIG. 1E), and the process is completed.

As described above, in the above embodiment, when the semiconductor substrate 2 of the chip-on-chip device is in the wafer state,
By flip-chip bonding the semiconductor chip 1 to the semiconductor substrate 2, a plurality of chip-on-chip devices are produced at one time, and finally dicing is performed to divide the chip-on-chip devices into individual ones.

Therefore, according to this embodiment, a chip-on-chip device can be manufactured at a wafer level, and a flux applying step, a reflow step, a flux cleaning step, a test step, etc. which have been conventionally performed for each individual semiconductor substrate. Since it can be performed on a wafer-by-wafer basis, the number of steps required for manufacturing one device can be significantly reduced, and the device manufacturing cost can be significantly reduced.

In this embodiment, the case where the semiconductor chip 1 is mounted on the semiconductor substrate 2 by flip chip bonding has been described, but the present invention is not limited to flip chip bonding, and a wire bonding method or It goes without saying that it can be applied to other chip mounting methods. In this case, the die bonding process and the test process can be performed at the wafer level, and the number of chip-on-chip device manufacturing steps can be significantly reduced.

Further, although the case where the number of the semiconductor chips 1 mounted on one semiconductor substrate 2 is one has been described in the present embodiment, the present invention has a plurality of semiconductor chips 1 mounted on one semiconductor substrate. It goes without saying that the present invention is also applicable when mounting a semiconductor chip.

[0021]

As is apparent from the above description, the semiconductor device manufacturing method of the present invention mounts semiconductor chips on a plurality of semiconductor substrates in a wafer state. Therefore, according to the present invention, a chip-on-chip device can be manufactured at the wafer level, and one device can be manufactured as compared with the conventional example in which the chip-on-chip device is manufactured at the level of individual semiconductor substrates that have been diced. The number of steps required for manufacturing can be significantly reduced. Therefore, it can greatly contribute to the reduction of the device manufacturing cost.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a process of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view of a chip on chip device manufactured by a flip chip bonding method.

FIG. 3 is a sectional view of a chip-on-chip device manufactured by a wire bonding method.

[Explanation of symbols]

1 semiconductor chip 2 semiconductor substrate 3 solder bump 4 bonding pad 5 wire 6 wafer 7 flux

Claims (1)

[Claims]
1. A method of manufacturing a semiconductor device including a semiconductor substrate and a semiconductor chip mounted on the semiconductor substrate, wherein the semiconductor chip is mounted on a plurality of semiconductor substrates in a wafer state before being individually cut. Then, a method of manufacturing a semiconductor device, characterized in that the semiconductor substrate is individually cut thereafter.
JP29851592A 1992-11-09 1992-11-09 Manufacture of semiconductor device Pending JPH06151701A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29851592A JPH06151701A (en) 1992-11-09 1992-11-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29851592A JPH06151701A (en) 1992-11-09 1992-11-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH06151701A true JPH06151701A (en) 1994-05-31

Family

ID=17860722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29851592A Pending JPH06151701A (en) 1992-11-09 1992-11-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH06151701A (en)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5726500A (en) * 1994-04-08 1998-03-10 Thomson-Csf Semiconductor hybrid component
US5773896A (en) * 1996-02-19 1998-06-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device having offsetchips
EP0715348A3 (en) * 1994-11-29 1998-07-15 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices
US6054371A (en) * 1997-09-29 2000-04-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device by detachably mounting substrates to a holder board
US6420787B1 (en) 1999-06-21 2002-07-16 Shinko Electric Industries Co., Ltd. Semiconductor device and process of producing same
JP2003110084A (en) * 2001-09-28 2003-04-11 Rohm Co Ltd Semiconductor device
EP1111676A3 (en) * 1999-12-22 2003-10-01 Shinko Electric Industries Co. Ltd. Unit interconnection substrate for electronic parts
FR2849533A1 (en) * 2002-12-27 2004-07-02 St Microelectronics Sa Semiconductor component assembly, incorporates a vertical component formed across a silicon slice, for use in power circuits with reduced risk of short circuit
US6784021B2 (en) 2001-09-10 2004-08-31 Renesas Technology Corp. Semiconductor device, method of fabricating the same and semiconductor device fabricating apparatus
US7129110B1 (en) * 1999-08-23 2006-10-31 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
JP2007305714A (en) * 2006-05-10 2007-11-22 Sharp Corp Semiconductor device, and manufacturing method thereof
US7528005B2 (en) 2000-03-09 2009-05-05 Oki Semiconductor Co., Ltd. Method of manufacturing chip size package semiconductor device without intermediate substrate
JP2010056404A (en) * 2008-08-29 2010-03-11 Canon Machinery Inc Manufacturing apparatus of semiconductor device and manufacturing method of semiconductor device
JP2010245289A (en) * 2009-04-06 2010-10-28 Canon Inc Method of manufacturing semiconductor device
JP2010245290A (en) * 2009-04-06 2010-10-28 Canon Inc Method of manufacturing semiconductor device
JP2012142572A (en) * 2010-12-31 2012-07-26 Samsung Electronics Co Ltd Semiconductor package and manufacturing method thereof

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5726500A (en) * 1994-04-08 1998-03-10 Thomson-Csf Semiconductor hybrid component
EP0715348A3 (en) * 1994-11-29 1998-07-15 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices
US5773896A (en) * 1996-02-19 1998-06-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device having offsetchips
US6054371A (en) * 1997-09-29 2000-04-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device by detachably mounting substrates to a holder board
US6548326B2 (en) 1999-06-21 2003-04-15 Shinko Electronic Industries Co., Ltd. Semiconductor device and process of producing same
US6420787B1 (en) 1999-06-21 2002-07-16 Shinko Electric Industries Co., Ltd. Semiconductor device and process of producing same
US7129110B1 (en) * 1999-08-23 2006-10-31 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
EP1111676A3 (en) * 1999-12-22 2003-10-01 Shinko Electric Industries Co. Ltd. Unit interconnection substrate for electronic parts
US7528005B2 (en) 2000-03-09 2009-05-05 Oki Semiconductor Co., Ltd. Method of manufacturing chip size package semiconductor device without intermediate substrate
US6995468B2 (en) 2001-09-10 2006-02-07 Renesas Technology Corp. Semiconductor apparatus utilizing a preparatory stage for a chip assembly
US6784021B2 (en) 2001-09-10 2004-08-31 Renesas Technology Corp. Semiconductor device, method of fabricating the same and semiconductor device fabricating apparatus
JP2003110084A (en) * 2001-09-28 2003-04-11 Rohm Co Ltd Semiconductor device
FR2849533A1 (en) * 2002-12-27 2004-07-02 St Microelectronics Sa Semiconductor component assembly, incorporates a vertical component formed across a silicon slice, for use in power circuits with reduced risk of short circuit
JP2007305714A (en) * 2006-05-10 2007-11-22 Sharp Corp Semiconductor device, and manufacturing method thereof
JP2010056404A (en) * 2008-08-29 2010-03-11 Canon Machinery Inc Manufacturing apparatus of semiconductor device and manufacturing method of semiconductor device
JP2010245289A (en) * 2009-04-06 2010-10-28 Canon Inc Method of manufacturing semiconductor device
JP2010245290A (en) * 2009-04-06 2010-10-28 Canon Inc Method of manufacturing semiconductor device
JP2012142572A (en) * 2010-12-31 2012-07-26 Samsung Electronics Co Ltd Semiconductor package and manufacturing method thereof

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