JPH06151701A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH06151701A
JPH06151701A JP4298515A JP29851592A JPH06151701A JP H06151701 A JPH06151701 A JP H06151701A JP 4298515 A JP4298515 A JP 4298515A JP 29851592 A JP29851592 A JP 29851592A JP H06151701 A JPH06151701 A JP H06151701A
Authority
JP
Japan
Prior art keywords
chip
semiconductor
semiconductor substrate
wafer
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4298515A
Other languages
Japanese (ja)
Inventor
Akiteru Rai
明照 頼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP4298515A priority Critical patent/JPH06151701A/en
Publication of JPH06151701A publication Critical patent/JPH06151701A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To cut down the manufacturing cost of a chip-on-chip device which is excellent in productivity by a method wherein a semiconductor chip is mounted on a plurality of semiconductor substrates in the state of wafer before they ar individually cut, and then the semiconductor substrates are cut into pieces. CONSTITUTION:A wafer 6 contains a number of semiconductor substrates 2. Each semiconductor substrate 2 contains a bonding pad part 4. The bonding pad part 4 contains the solder wetting metal layer such as Cu and Au, for example. When the semiconductor substrate 2 of a chip-on-chip device is in a wafer state, a semiconductor chip 1 is flip-chip bonded on the abovementioned semiconductor substrate 2. As a result, a plurality of chip-on-chip devices are manufactured simultaneously, and lastly, the chip-on-chip devices are separated into individual pieces. Accordingly, the man-hours for the manufacture of the chip-on-chip devices can be reduced and the manufacturing cost can also be cut down.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に半導体基板上に半導体チップを実装した半導
体装置の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a semiconductor chip mounted on a semiconductor substrate.

【0002】[0002]

【従来技術】近年、図2および図3に示すように半導体
基板22,32上に半導体チップ21,31を搭載した半
導体装置であるチップオンチップデバイスを作製するた
めのチップオンチップ実装技術の開発が盛んに行われて
いる。
2. Description of the Related Art In recent years, development of a chip-on-chip mounting technique for manufacturing a chip-on-chip device which is a semiconductor device in which semiconductor chips 21 and 31 are mounted on semiconductor substrates 22 and 32 as shown in FIGS. Is being actively conducted.

【0003】図2に示すチップオンチップデバイスは、
フリップチップボンディング技術を用いて、ハンダバン
プ23を介して半導体基板22に半導体チップ21を接
続したチップオンチップデバイスである。
The chip-on-chip device shown in FIG.
This is a chip-on-chip device in which the semiconductor chip 21 is connected to the semiconductor substrate 22 via the solder bumps 23 using the flip chip bonding technique.

【0004】また、図3に示すチップオンチップデバイ
スは、ワイヤーボンディング技術を用いてワイヤー35
を介して半導体基板32に半導体チップ31を接続した
チップオンチップデバイスである。
Further, the chip-on-chip device shown in FIG. 3 uses the wire bonding technique to form the wire 35.
It is a chip-on-chip device in which the semiconductor chip 31 is connected to the semiconductor substrate 32 via the.

【0005】このチップオンチップ実装技術は、大きな
サイズのチップの搭載が容易であり、信頼性に優れ、多
機能化・大容量化・高密度化が容易である等の特長を有
しており、次世代の高密度実装技術として大きく期待さ
れている。
This chip-on-chip mounting technique has features that it is easy to mount a large-sized chip, has excellent reliability, and is easy to have multiple functions, large capacity, and high density. , Is highly expected as a next-generation high-density mounting technology.

【0006】図2に示すチップオンチップデバイスの作
製およびパッケージングは、一般に、以下の(i)〜(v)に
示すような順に行う。 (i) バンプ付半導体チップ21を作製する。 (ii) ボンディングパッド24を有する半導体基板22
を作製する。 (iii) ダイシング後の個々の半導体基板22上に半導体
チップ21をフリップチップボンディングする。 (iv) 電気テストを行い、半導体チップ21に不良があ
れば、半導体チップ21のリペアーを行う。必要に応じ
て半導体チップ21と半導体基板22の界面にレジンを
注入し、チップオンチップデバイスの作製を完了する。 (v) チップオンチップデバイスをパッケージングす
る。
The fabrication and packaging of the chip-on-chip device shown in FIG. 2 are generally performed in the order shown in (i) to (v) below. (i) The bumped semiconductor chip 21 is manufactured. (ii) Semiconductor substrate 22 having bonding pad 24
To make. (iii) The semiconductor chips 21 are flip-chip bonded onto the individual semiconductor substrates 22 after dicing. (iv) An electrical test is performed, and if the semiconductor chip 21 is defective, the semiconductor chip 21 is repaired. If necessary, resin is injected into the interface between the semiconductor chip 21 and the semiconductor substrate 22 to complete the production of the chip-on-chip device. (v) Packaging chip-on-chip devices.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、従来、
上述のような方法でチップオンチップデバイスを作製す
る場合には、一枚毎の半導体基板22に対してフラック
ス塗布と、半導体チップ21の仮接着と、リフローと、
フラックス洗浄と、テスト等の工程を行う必要があるの
で、量産性が悪く、トータル的に見てコストアップにな
るという問題がある。
[Problems to be Solved by the Invention]
When the chip-on-chip device is manufactured by the method as described above, the flux coating, the temporary bonding of the semiconductor chips 21, and the reflow are applied to each semiconductor substrate 22.
Since it is necessary to carry out steps such as flux cleaning and testing, there is a problem that mass productivity is poor and the cost increases in total.

【0008】また、ワイヤーボンディング方式による作
製方法においてもダイボンディング工程やテスト工程
を、個々の半導体基板32について実施しなければなら
ず量産性に問題があった。
Also, in the wire bonding method, the die bonding step and the test step must be carried out for each semiconductor substrate 32, and there is a problem in mass productivity.

【0009】そこで、本発明の目的は、量産性に優れ、
チップオンチップデバイスの製造コストを低減できる半
導体装置の製造方法を提供することにある。
Therefore, an object of the present invention is to have excellent mass productivity,
It is an object of the present invention to provide a semiconductor device manufacturing method capable of reducing the manufacturing cost of a chip-on-chip device.

【0010】[0010]

【問題を解決するための手段】上記目的を達成するため
に、本発明は、半導体基板と上記半導体基板上に実装さ
れた半導体チップとを含む半導体装置の製造方法におい
て、個別に切断される前のウェハ状態の複数個の半導体
基板上に半導体チップを実装し、その後、上記半導体基
板を個別に切断することを特徴としている。
In order to achieve the above object, the present invention is a method of manufacturing a semiconductor device including a semiconductor substrate and a semiconductor chip mounted on the semiconductor substrate. The semiconductor chip is mounted on a plurality of semiconductor substrates in the wafer state, and then the semiconductor substrates are individually cut.

【0011】[0011]

【作用】本発明によれば、ウェハ状態の複数個の半導体
基板上に半導体チップを実装するので、従来個々の半導
体基板毎に行っていたフラックス塗布工程およびリフロ
ー工程およびフラックス洗浄工程およびテスト工程等
を、ウェハ単位で行うことができるので、1つの半導体
基板当たりに必要な工程数を大幅に低減することが可能
になる。
According to the present invention, since semiconductor chips are mounted on a plurality of semiconductor substrates in a wafer state, a flux applying step, a reflow step, a flux cleaning step, a test step, etc., which are conventionally performed for each individual semiconductor substrate. Can be performed on a wafer-by-wafer basis, so that the number of steps required for one semiconductor substrate can be significantly reduced.

【0012】[0012]

【実施例】以下、本発明を図示の実施例に基づいて詳細
に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on the illustrated embodiments.

【0013】図1に、本発明の半導体装置の製造方法の
実施例を示す。図1(A),(B),(C),(D),(E)を順に参
照して、上記実施例を説明する。
FIG. 1 shows an embodiment of a method of manufacturing a semiconductor device according to the present invention. The above embodiment will be described with reference to FIGS. 1A, 1B, 1C, 1D and 1E in order.

【0014】図1(A)に示すウェハ6は、多数の半導体
基板2を含んでいる。半導体基板2はボンディングパッ
ド部4を含んでいる。このボンディングパッド部4は、
例えばCuやAuのようなハンダが濡れる金属層を含んで
いる。
The wafer 6 shown in FIG. 1A includes a large number of semiconductor substrates 2. The semiconductor substrate 2 includes a bonding pad portion 4. The bonding pad section 4 is
It contains a metal layer which is wetted by solder, such as Cu or Au.

【0015】図1(B)に示すように、上記ウェハ6のボ
ンディングパッド部4に、例えば、転写またはスタンピ
ングまたはディスペンサー等によってフラックス7を塗
布する。次に、図1(C)に示すように、上記ウェハ6が
含む各半導体基板2上に、ハンダバンプ3を含む半導体
チップ1を、フリップチップボンダーを用いてプレース
メントする。この時、ハンダバンプ3はフラックスの粘
着力によって半導体基板2のボンディングパッド部4に
仮接着される。
As shown in FIG. 1B, the flux 7 is applied to the bonding pad portion 4 of the wafer 6 by, for example, transfer, stamping, dispenser or the like. Next, as shown in FIG. 1C, the semiconductor chip 1 including the solder bumps 3 is placed on each semiconductor substrate 2 included in the wafer 6 by using a flip chip bonder. At this time, the solder bumps 3 are temporarily adhered to the bonding pad portion 4 of the semiconductor substrate 2 by the adhesive force of the flux.

【0016】次に、上記ウェハ6および半導体チップ1
を、最大温度がハンダの融点より高いリフロー炉に通
し、ハンダバンプ3を溶融して、上記半導体チップ1と
ウェハ6とを接続する。その後、フラックス残渣を溶剤
洗浄によって除去する(図1(D)参照)。最後に、形成さ
れた各半導体チップ1を電気テストし、チップ1に不良
があれば、不良チップを除去し、再度フラックス塗布か
ら工程を繰り返す。不良が無ければ、上記半導体チップ
1と上記半導体基板2とを含む各チップオンチップデバ
イスをダイシングによって個別化し(図1(E)参照)、工
程を完了する。
Next, the wafer 6 and the semiconductor chip 1 described above.
Is passed through a reflow furnace whose maximum temperature is higher than the melting point of solder to melt the solder bumps 3 and connect the semiconductor chip 1 and the wafer 6. After that, the flux residue is removed by solvent cleaning (see FIG. 1D). Finally, each formed semiconductor chip 1 is electrically tested, and if the chip 1 is defective, the defective chip is removed, and the steps from flux coating to the step are repeated again. If there is no defect, the chip-on-chip devices including the semiconductor chip 1 and the semiconductor substrate 2 are individually diced (see FIG. 1E), and the process is completed.

【0017】このように、上記実施例は、チップオンチ
ップデバイスの半導体基板2がウェーハ状態のときに、
この半導体基板2に半導体チップ1をフリップチップボ
ンディングすることによって、複数個のチップオンチッ
プデバイスを一度に作製し、最後にダイシングを行って
チップオンチップデバイスを個々に分割するものであ
る。
As described above, in the above embodiment, when the semiconductor substrate 2 of the chip-on-chip device is in the wafer state,
By flip-chip bonding the semiconductor chip 1 to the semiconductor substrate 2, a plurality of chip-on-chip devices are produced at one time, and finally dicing is performed to divide the chip-on-chip devices into individual ones.

【0018】したがって、この実施例によれば、ウェハ
レベルでチップオンチップデバイスを作製することがで
き、従来個々の半導体基板毎に行っていたフラックス塗
布工程およびリフロー工程およびフラックス洗浄工程お
よびテスト工程等をウェハ単位で行うことができるの
で、デバイス1個作製するに当たって必要となる工程数
を大幅に減少させることができ、デバイス作製コストを
大幅に削減できる。
Therefore, according to this embodiment, a chip-on-chip device can be manufactured at a wafer level, and a flux applying step, a reflow step, a flux cleaning step, a test step, etc. which have been conventionally performed for each individual semiconductor substrate. Since it can be performed on a wafer-by-wafer basis, the number of steps required for manufacturing one device can be significantly reduced, and the device manufacturing cost can be significantly reduced.

【0019】尚、本実施例では半導体基板2上への半導
体チップ1の搭載をフリップチップボンディングによっ
て行う場合について説明したが、本発明はフリップチッ
プボンディングだけに限られるものではなく、ワイヤー
ボンディング方式やその他のチップ実装方式においても
適用できることは言うまでもない。この場合、ウェハレ
ベルでダイボンディング工程やテスト工程が行えるよう
になって、チップオンチップデバイスの製造工数を大幅
に削減できる。
In this embodiment, the case where the semiconductor chip 1 is mounted on the semiconductor substrate 2 by flip chip bonding has been described, but the present invention is not limited to flip chip bonding, and a wire bonding method or It goes without saying that it can be applied to other chip mounting methods. In this case, the die bonding process and the test process can be performed at the wafer level, and the number of chip-on-chip device manufacturing steps can be significantly reduced.

【0020】また、本実施例では1個の半導体基板2上
へ搭載する半導体チップ1の個数が1つである場合につ
いて説明を行ったが、本発明は1個の半導体基板上へ複
数個の半導体チップを搭載する場合においても適用可能
であることは言うまでもない。
Further, although the case where the number of the semiconductor chips 1 mounted on one semiconductor substrate 2 is one has been described in the present embodiment, the present invention has a plurality of semiconductor chips 1 mounted on one semiconductor substrate. It goes without saying that the present invention is also applicable when mounting a semiconductor chip.

【0021】[0021]

【発明の効果】以上の説明より明らかなように、本発明
の半導体装置の製造方法は、ウェハ状態の複数個の半導
体基板上に半導体チップを実装するものである。したが
って、この発明によれば、ウェハレベルでチップオンチ
ップデバイスを作製することができ、ダイシング済みの
個々の半導体基板のレベルでチップオンチップデバイス
を作製していた従来例に比べて、デバイス1個作製する
に当たって必要となる工程数を大幅に減少させることが
できる。したがって、デバイス作製コストの削減に大き
く寄与することができる。
As is apparent from the above description, the semiconductor device manufacturing method of the present invention mounts semiconductor chips on a plurality of semiconductor substrates in a wafer state. Therefore, according to the present invention, a chip-on-chip device can be manufactured at the wafer level, and one device can be manufactured as compared with the conventional example in which the chip-on-chip device is manufactured at the level of individual semiconductor substrates that have been diced. The number of steps required for manufacturing can be significantly reduced. Therefore, it can greatly contribute to the reduction of the device manufacturing cost.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の半導体装置の製造方法の実施例の工
程を示す断面図である。
FIG. 1 is a cross-sectional view showing a process of an embodiment of a method for manufacturing a semiconductor device of the present invention.

【図2】 フリップチップボンディング方式によって製
造したチップオンチップデバイスの断面図である。
FIG. 2 is a cross-sectional view of a chip on chip device manufactured by a flip chip bonding method.

【図3】 ワイヤーボンディング方式によって製造した
チップオンチップデバイスの断面図である。
FIG. 3 is a sectional view of a chip-on-chip device manufactured by a wire bonding method.

【符号の説明】[Explanation of symbols]

1 半導体チップ 2 半導体基板 3 ハンダバンプ 4 ボンディン
グパッド 5 ワイヤー 6 ウェハ 7 フラックス
1 semiconductor chip 2 semiconductor substrate 3 solder bump 4 bonding pad 5 wire 6 wafer 7 flux

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板と上記半導体基板上に実装さ
れた半導体チップとを含む半導体装置の製造方法におい
て、 個別に切断される前のウェハ状態の複数個の半導体基板
上に半導体チップを実装し、 その後、上記半導体基板を個別に切断することを特徴と
する半導体装置の製造方法。
1. A method of manufacturing a semiconductor device including a semiconductor substrate and a semiconductor chip mounted on the semiconductor substrate, wherein the semiconductor chip is mounted on a plurality of semiconductor substrates in a wafer state before being individually cut. Then, a method of manufacturing a semiconductor device, characterized in that the semiconductor substrate is individually cut thereafter.
JP4298515A 1992-11-09 1992-11-09 Manufacture of semiconductor device Pending JPH06151701A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4298515A JPH06151701A (en) 1992-11-09 1992-11-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4298515A JPH06151701A (en) 1992-11-09 1992-11-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH06151701A true JPH06151701A (en) 1994-05-31

Family

ID=17860722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4298515A Pending JPH06151701A (en) 1992-11-09 1992-11-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH06151701A (en)

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5726500A (en) * 1994-04-08 1998-03-10 Thomson-Csf Semiconductor hybrid component
US5773896A (en) * 1996-02-19 1998-06-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device having offsetchips
EP0715348A3 (en) * 1994-11-29 1998-07-15 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices
US6054371A (en) * 1997-09-29 2000-04-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device by detachably mounting substrates to a holder board
US6420787B1 (en) 1999-06-21 2002-07-16 Shinko Electric Industries Co., Ltd. Semiconductor device and process of producing same
JP2003110084A (en) * 2001-09-28 2003-04-11 Rohm Co Ltd Semiconductor device
EP1111676A3 (en) * 1999-12-22 2003-10-01 Shinko Electric Industries Co. Ltd. Unit interconnection substrate for electronic parts
JP2004128523A (en) * 2004-01-08 2004-04-22 Oki Electric Ind Co Ltd Semiconductor device and method of manufacturing semiconductor device
FR2849533A1 (en) * 2002-12-27 2004-07-02 St Microelectronics Sa Semiconductor component assembly, incorporates a vertical component formed across a silicon slice, for use in power circuits with reduced risk of short circuit
US6784021B2 (en) 2001-09-10 2004-08-31 Renesas Technology Corp. Semiconductor device, method of fabricating the same and semiconductor device fabricating apparatus
US7129110B1 (en) * 1999-08-23 2006-10-31 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
JP2007305714A (en) * 2006-05-10 2007-11-22 Sharp Corp Semiconductor device, and manufacturing method thereof
US7528005B2 (en) 2000-03-09 2009-05-05 Oki Semiconductor Co., Ltd. Method of manufacturing chip size package semiconductor device without intermediate substrate
JP2010056404A (en) * 2008-08-29 2010-03-11 Canon Machinery Inc Manufacturing apparatus of semiconductor device and manufacturing method of semiconductor device
JP2010245289A (en) * 2009-04-06 2010-10-28 Canon Inc Method of manufacturing semiconductor device
JP2010245290A (en) * 2009-04-06 2010-10-28 Canon Inc Method of manufacturing semiconductor device
JP2012142572A (en) * 2010-12-31 2012-07-26 Samsung Electronics Co Ltd Semiconductor package and manufacturing method thereof

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5726500A (en) * 1994-04-08 1998-03-10 Thomson-Csf Semiconductor hybrid component
EP0715348A3 (en) * 1994-11-29 1998-07-15 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices
US5773896A (en) * 1996-02-19 1998-06-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device having offsetchips
US6054371A (en) * 1997-09-29 2000-04-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device by detachably mounting substrates to a holder board
US6548326B2 (en) 1999-06-21 2003-04-15 Shinko Electronic Industries Co., Ltd. Semiconductor device and process of producing same
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