JP2004128523A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, with which a CSP (chip size package) having no built-in interposer can be made into a MCP (multi-chip package), and also to provide a method of manufacturing the semiconductor device. <P>SOLUTION: A first IC chip 101 having a main surface having a first pad 102 formed thereon, a protective film 103 covering the main surface of the first IC chip 101 so as to expose a part of the first pad 102, and a first face having a second pad 112 formed thereon and a second face facing the first face are provided. Further provided are a second IC chip 111 provided on the first protective film 103 so that the second face and the protective film 103 face each other, a second protective film 113 covering the first face of the second IC chip 111 so as to expose a part of the second pad 112, a conductor 115 provided on the second pad 112 and the second protective film 113 so as to be electrically connected to the second pad 112, a columnar conductor 116 provided on the conductor 115 and electrically connected to the conductor 115, a resin 130 covering the first and second protective films 103 and 113, the conductor 115, and the side face of the second IC chip 111 so as to expose an end of the columnar conductor 116. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a multi-chip semiconductor device using a chip size package and a method for manufacturing the semiconductor device.

伴 い With the recent miniaturization of electronic devices, various methods for mounting semiconductor devices at high density are being studied. Among them, there is a method of promoting a reduction in the size of a semiconductor device and an increase in the density of a plurality of component mountings. As for the miniaturization of semiconductor devices, miniaturization of a semiconductor package containing an IC chip has been studied, and there is a semiconductor package called a chip size package (hereinafter abbreviated as CSP) having substantially the same size as the IC chip. To increase the density of mounting of a plurality of components, a multi-chip module (hereinafter abbreviated as MCM) or a multi-chip package (hereinafter abbreviated as MCP) in which a plurality of IC chips and other components are incorporated in a single module or package. ).

FIG. 17 shows an example of the structure of a conventional CSP. An aluminum electrode pad 2 is formed on the IC chip 1. Aluminum electrode pad 2 is electrically connected to the internal integrated circuit of IC chip 1. Connected to the aluminum electrode pad 2, a copper post 5 which is a columnar conductor is formed thereon. The resin 30 seals the conductor and at least the integrated circuit forming surface of the IC chip 1.

(4) At predetermined positions on the copper post 5 and the resin 30, a plurality of rewiring patterns 6 each having a surface plated with gold, tin, or the like are formed at intervals. On the rewiring pattern 6, solder balls 7 for external connection terminals are formed. The aluminum electrode pad 2, the copper post 5, the rewiring pattern 6, and the solder ball 7 are electrically connected. Thereby, the internal integrated circuit of the IC chip 1 can be electrically connected to the external substrate. Thus, a package having substantially the same size as the IC chip 1 is formed.

However, among the CSPs described above, a CSP that does not include an intermediate substrate, particularly called an interposer, cannot incorporate a plurality of IC chips due to its outer size and structure, and is difficult to be MCP. Therefore, when a plurality of semiconductor packages on a mounting board are electrically wired, the wiring length becomes long, which is an obstacle not only in high-density mounting but also in speeding up of final electronic devices.

On the other hand, in a semiconductor package having a built-in interposer, a plurality of IC chips can be mounted on the interposer, but the package size is larger than that of the IC chip, and the cost of the package becomes higher because the interposer is built in. There was a problem.

The present invention has been made in view of such a problem, and it is an object of the present invention to provide a semiconductor device capable of MCP in a CSP without a built-in interposer and a method of manufacturing the semiconductor device.

In order to solve the above problem, according to one aspect of the present invention, a first IC chip having a main surface on which a first pad is formed, and a part of the first pad are exposed. A first protective film that covers a main surface of the first IC chip; a first surface on which a second pad is formed; and a second surface facing the first surface, wherein the second surface is A second IC chip provided on the first protection film so as to face the first protection film; and a second IC chip provided so as to expose a part of the second pad. A second protective film covering the first surface, a conductor provided on the second pad and the second protective film, electrically connected to the second pad, and provided on the conductor; A columnar conductor electrically connected to the conductor, and the first and second protective films so as to expose one end of the columnar conductor. Wherein a is constituted by a resin covering the serial conductor and the side surface of the second IC chip is provided.

According to another aspect of the present invention, there is provided a first IC chip having a main surface on which a pad is formed, and the first IC chip being configured to expose a part of the pad. A protective film covering the main surface of the chip, a conductor provided on the pad and the protective film and electrically connected to the pad, and a columnar shape provided on the conductor and electrically connected to the conductor. A conductor, a second IC chip provided on the conductor, and a resin covering the protective film, the conductor, and the second IC chip such that one end of the columnar conductor is exposed. A semiconductor device is provided.

According to another embodiment of the present invention, there is provided a first IC chip having a main surface on which a first pad is formed, and a method for exposing a part of the first pad. A first protective film covering a main surface of the first IC chip, a first surface on which a second pad is formed, and a second surface facing the first surface; A second IC chip provided on the first protection film so as to face the first protection film, and a second IC chip provided so as to expose a part of the second pad. A second protective film covering the first surface of the first and second pads and the first and second protective films, and electrically connected to the first and second pads. And a columnar conductor provided on the conductor and electrically connected to the conductor, and a front end exposed to expose one end of the columnar conductor. Wherein a is constituted by a resin the first and second protective film covers a side surface of the conductor and the second IC chip is provided.

According to another embodiment of the present invention, there is provided a first IC chip having a main surface on which a first pad is formed, and a method for exposing a part of the first pad. A protective film covering a main surface of the first IC chip, a first surface on which a second pad is formed, and a second surface facing the first surface; A second IC chip having the first surface and the second surface covered with the protective film except for a portion, and the first and second pads provided on the first and second pads and the protective film; A conductor electrically connected to the second pad, a columnar conductor provided on the conductor and electrically connected to the conductor, and the protective film and the conductor so as to expose one end of the columnar conductor. And a resin for covering the semiconductor device.

According to another aspect of the present invention, there is provided a first IC chip having a main surface on which a first pad is formed, and a first IC chip provided on the first pad. A first columnar conductor electrically connected thereto, a first surface on which a second pad is formed, and a second surface facing the first surface, wherein the second surface is the first IC A second IC chip provided on the main surface of the first IC chip so as to face the main surface of the chip; and a second IC chip provided on the second pad and electrically connected to the pad. And a resin covering the main surface of the first IC chip and the first surface and side surfaces of the second IC chip so as to expose one ends of the first and second columnar conductors. And a semiconductor device characterized by comprising:

According to another embodiment of the present invention, there is provided a semiconductor device including a first IC chip and a second IC chip mounted on a main surface of the first chip. The second IC chip has a first surface on which an integrated circuit is formed and a second surface facing the first surface, and the second surface is in contact with a main surface of the first IC chip. The main surface of the first IC chip and the second surface are mounted on the main surface so as to face each other, leaving a part of the columnar conductor formed on the first surface of the second IC chip. A semiconductor device comprising: a resin that covers the first surface and the side surface of the IC chip.

According to another aspect of the present invention, a plurality of IC chips each having a semiconductor integrated circuit formed therein are incorporated in one package, and the size of the package is reduced by the plurality of embedded IC chips. What is claimed is: 1. A method of manufacturing a semiconductor device having a size equal to the size of the largest IC chip among the IC chips, wherein a step of preparing a wafer on which an IC serving as the largest IC chip is formed, Preparing the built-in IC chip, forming a surface protection film on the wafer, forming a hole having the same size as the built-in IC chip in the surface protection film, Mounting the built-in IC chip in a portion, and simultaneously forming and patterning a conductor on the surface of the wafer and the mounted IC chip. The method of manufacturing a semiconductor device according to claim is provided.

According to the present invention as described in detail above, it is possible to provide a semiconductor device and a method of manufacturing a semiconductor device that can be MCP-formed in a CSP that does not include an interposer.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the specification and the drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.

FIG. 1 is a structural sectional view showing a first embodiment of the present invention. Another IC chip 111 is die-bonded on the IC chip 101 serving as a support substrate and is incorporated in a package. The size of the IC chip 101 serving as a support substrate is equal to the size of the package.

(4) A pad 102 and two layers of surface protection films 103 and 104 are formed on the IC chip 101. The pad 102 is electrically connected to the internal integrated circuit of the IC chip 101. The surface protection films 103 and 104 are for protecting the surface of the integrated circuit, and have openings on the pads 102. Further, a conductor 105 is formed on the surface protective film 104 by connecting to the pad 102, a columnar conductor 106 is formed by connecting to the conductor 105, and a connection material 107 is formed on the conductor 106.

The conductors 105 and 106 enable electrical connection from the pad 102 to external terminals of the package, and the connection material 107 allows the package to be connected to an external substrate (not shown). That is, the internal integrated circuit of the IC chip 101 and the external substrate can be electrically connected by the series of connected pads 102, conductors 105 and 106, and connection material 107.

ＩＣ An IC chip 111 is die-bonded on the surface protection film 104 via a die bonding material 108. The IC chip 111 is a separate chip from the IC chip 101 serving as a support substrate, and is ground smaller than the IC chip 101 and thin enough to be built in the same package.

A pad 112 and two layers of surface protection films 113 and 114 are formed on the IC chip 111. The pad 112 is electrically connected to the internal integrated circuit of the IC chip 111. The surface protection films 113 and 114 are for protecting the surface of the integrated circuit, and have openings on the pads 112. Further, a conductor 115 is formed on the surface protective film 114 and connected to the pad 112, a columnar conductor 116 is formed and connected to the conductor 115, and a connection material 117 is formed on the conductor 116. The resin 130 seals at least the integrated circuit forming surface of all the IC chips.

The conductors 115 and 116 enable the pad 112 to be electrically connected to the external terminals of the package, and the connection material 117 allows the package to be connected to an external substrate. That is, the internal integrated circuit of the IC chip 111 and the external substrate of the package can be electrically connected by the series of connected pads 112, conductors 115 and 116, and connection material 117.

The surface protection films 103, 104 and 113, 114 are the surface protection films of the IC chips 101 and 111, respectively. Here, the surface protection films 103 and 113 are silicon oxide films or silicon nitride films, and the surface protection films 104 and 114 are films made of a polymer resin such as polyimide. These surface protective films may have a single-layer structure, but by using a composite layer structure, they are integrated due to the effects of processing such as conductor formation and die bonding on the IC chip, and the effects of thermal stress after the package is connected to the substrate. The circuit can be more protected.

The conductors 105 and 115 are conductor wiring connecting the pad 102 and the conductor 106 and connecting the pad 112 and the conductor 116, respectively. Here, a metal material having a composite layer structure made of titanium and copper is used. In this case, the titanium layer is formed for adhesion to the pad and the surface protective film and for preventing diffusion, and the copper layer is formed mainly for the function as an electrical connection material. Needless to say, a single-layer structure or a material structure may be used. Various examples of the material configuration in the case of the composite layer configuration include chromium-copper, chromium-gold, nickel-copper, nickel-gold, titanium / tungsten-copper, and titanium / tungsten-gold.

The conductors 106 and 116 are conductors for electrically connecting the conductors 105 and 115 to the outside of the package, respectively, and at least a part of the conductors needs to be exposed from the resin 130. As the material, a material having low electric resistance is preferable, and copper, gold, aluminum and the like can be mentioned.

In FIG. 1, only one IC chip 111 is shown as the built-in IC chip other than the IC chip serving as the support substrate, but a plurality of IC chips may be used. This is the same for the embodiments described below. Here, if the IC chip 101 serving as a support substrate is a logic chip and the built-in IC chip 111 is a memory chip, a logic system and a memory system can be mixedly mounted. The combination of IC chips is not limited to the above, and it is also possible to use memory semiconductor elements or logic semiconductor elements.

FIG. 8 is a view in which the semiconductor package having the structure shown in FIG. 1 is mounted on a mounting board. The semiconductor device 100 including the IC chips 101 and 111 is mounted on the mounting substrate 150 by the wiring 151 on the mounting substrate. In FIG. 8, the upper and lower sides of the semiconductor device 100 are opposite to those in FIG. By mounting the semiconductor device 100 on the mounting substrate 150, the IC chips 101 and 111 are electrically connected to the wiring 151 on the mounting substrate. In the state of the semiconductor device 100 alone, the IC chips 101 and 111 are not electrically connected directly, but when mounted on the mounting substrate 150, the IC chip 101 and the IC chip 111 are connected via the wiring 151 on the mounting substrate. It is connected.

Hereinafter, a method of mounting the IC chip 111 on the IC chip 101 will be described with reference to FIG. First, in the IC chip 101, the pad 102, the surface protection films 103 and 104, and the conductors 105 and 106 are formed. In the IC chip 111, the pad 112, the surface protection films 113 and 114, and the conductors 115 and 116 are formed. Prepare what has been done. Here, the IC chip 101 may be a dice that has already been diced and singulated, or a wafer state before dicing.

When the IC chip 111 is die-bonded to the IC chip 101, if the IC chip 101 is an individualized IC chip, the individualized IC chip 199 is individualized as shown in FIG. The die bonding material 108 is used for bonding on the IC chip 191 thus completed. If the IC chip 101 is in a wafer state before dicing, the singulated IC chip 199 is bonded to the wafer 181 with the die bonding material 108 as shown in FIG.

(4) Since the semiconductor package is required to be as small as possible, it is desired that the IC chip 101 and the IC chip 111 are die-bonded in parallel as thinly as possible. Therefore, it is preferable that the die bonding material 108 be thin and have a uniform thickness. As the die bonding material 108, various materials such as a conductive paste containing silver as a main material, a liquid polyimide, and a sheet adhesive can be considered.

(4) When the singulated IC chip is mounted on an IC chip serving as a support substrate, there is no fear that the two IC chips are damaged. On the other hand, when the singulated IC chip is mounted on an IC in a wafer state before being singulated, there is an advantage that the subsequent steps can be collectively processed on a wafer basis, thereby facilitating the manufacture.

Next, a method of exposing the columnar conductors 106 and 116 for making electrical connection to the outside of the semiconductor package on the same surface of the package will be described with reference to FIG. When the IC chip 111 is mounted on the above-described IC chip 101, the conductors 106 and 116 formed thereon generally have irregular heights as shown in FIG. The columnar conductors 106 and 116 are formed by forming a pattern with a thick film resist and plating, or by bonding and fixing an existing fine columnar component. However, it is difficult to adjust the heights of the conductors 106 and 116 in advance so that the top surfaces of the conductors 106 and 116 are uniformly exposed on the same surface when the IC chip 111 is mounted on the IC chip 101. It is.

Therefore, the IC chip 111 is mounted on the IC chip 101, and the conductors 106 and 116 are sealed with the resin 130 up to a surface 1001 higher than the uppermost surface thereof in a state where the conductors 106 and 116 are not uniform. Next, the resin 130 is polished or etched to the surface 1002. At this time, the conductors 106 and 116 are simultaneously polished or etched. Thus, the columnar conductors 106 and 116 formed on each IC can be exposed on the same surface of the package.

Next, an electrical test method for an MCP semiconductor device provided by the present invention will be described. For this, there are two methods depending on the state of the semiconductor device. One is a method in which the MCP semiconductor device is singulated, and a test is performed for each singulated package. Another method is a test method in which an IC serving as a supporting substrate is in a wafer state, and a built-in IC chip is mounted, resin-sealed and a columnar conductor is exposed.

(4) The former test method can be tested individually, so the test is performed reliably, and defective products can be separated from good products when they are found. A so-called blowing method can be applied to the latter test method, and it is not necessary to prepare a special jig such as a special test socket as compared with the former test method. In any case, not only are the built-in ICs individually tested and then combined, but also by performing an electrical test on the MCP-formed semiconductor device, the electrical connection between the built-in ICs and the combination Only the functions that can be confirmed can be tested.

As described above, according to the present embodiment, a number of effects described below can be obtained. An MCP that can incorporate multiple IC chips without using an interposer, and its package size can be the same as the largest of the built-in IC chips. Will be possible. In addition, since a plurality of IC chips are built in the semiconductor package and are all sealed with resin, the reliability such as moisture resistance is higher than that in which another IC chip is mounted outside the package. Since a plurality of IC chips can be mounted at the same time, the number of mounting processing steps on the mounting substrate is reduced, and the cost can be reduced. By mounting one MCP on a mounting board, a plurality of built-in IC chips can be electrically connected simultaneously.

In the case where the IC serving as the support substrate is singulated, another singulated IC chip is mounted on the singulated IC chip. This eliminates problems such as scratching the IC chip. When the IC serving as a support substrate is in a wafer state, a plurality of singulated IC chips are mounted on the wafer, and subsequent processes such as resin sealing, conductor exposure, and terminal processing can be performed collectively on a wafer basis. , Making it easier to manufacture.

A plurality of singulated IC chips are mounted on an IC serving as a support substrate, and after sealing with a resin, the columnar conductor formed on each IC is polished or etched with a resin, thereby easily forming a semiconductor package. The columnar conductor can be uniformly exposed on the same surface.

By adopting a test method in which an electrical inspection is performed in a state in which a plurality of IC chips are built in one semiconductor package, the test can be performed reliably and defective products can be separated from non-defective products at that time. is there. A test method in which an IC serving as a supporting substrate is in a wafer state, another singulated IC chip is mounted, resin sealing is performed, and an electrical inspection is performed before singulating the IC serving as a supporting substrate. In this case, a so-called blowing method can be applied, and special preparation of a jig such as a test socket is not required as compared with the former test method. By performing an electrical test on a semiconductor device formed into an MCP, it becomes possible to perform an electrical connection between a plurality of built-in ICs and a test of a function that can be confirmed only when combined.

FIG. 2 is a structural cross-sectional view showing a second embodiment of the present invention. In the present embodiment, one of the conductors 105 is replaced with a conductor 205. The conductor 205 extends to the die bonding area of the IC chip 111, and the IC chip 111 is bonded thereon with the die bonding material 208. The die bonding material 208 has conductivity.

With such a structure, the back surface of the IC chip 111 is electrically connected to the connection material 107 and the internal integrated circuit of the IC chip 101 via the die bonding material 208 and the conductor 205. Therefore, when the semiconductor device shown in FIG. 2 is connected to the mounting substrate, the back potential of the IC chip 111 can be fixed via the connection material 107, the conductor 205, and the die bonding material 208.

According to the present embodiment, in addition to the effects of the first embodiment, the back potential of the IC chip built in the semiconductor package can be fixed, and a stable function of the semiconductor device can be obtained.

FIG. 3 is a structural sectional view showing a third embodiment of the present invention. In the present embodiment, conductors 305 and 315 are provided instead of the conductors 105 and 115 in the first embodiment, and an insulating material 309 is newly provided on the side surface of the IC chip 111. The conductors 305 and 315 are extended and connected via the surface of the insulating material 309.

(4) By connecting the conductors 305 and 315, the IC chip 101 serving as a support substrate and the built-in IC chip 111 are electrically connected inside the package. Also, when a plurality of IC chips are die-bonded on the IC chip 101, conductors similar to the conductors 305 and 315 are provided on these IC chips, and the IC chips are disposed as appropriate, so that a plurality of built-in ICs other than the support substrate are provided. The chips can be electrically connected. Note that in the present embodiment, the conductor 116 and the connection material 117 are not necessarily required.

According to the present embodiment, in addition to the effects of the first embodiment, it is possible to make an electrical connection between a plurality of IC chips built in the semiconductor package inside the semiconductor package. Accordingly, it is not necessary to form a wiring in consideration of the electrical connection between the built-in IC chips on the connection substrate for connecting the semiconductor device. Further, since the electrical connection between the plurality of IC chips built in the semiconductor package can be made using shorter wiring, the speed of the semiconductor device can be increased.

FIG. 4 is a structural sectional view showing a fourth embodiment of the present invention. In this embodiment, a surface protective film 404 having a thickness greater than that of the surface protective film 104 is further provided instead of the surface protective film 104. The surface protective film 404 has a hole having the same size as the IC chip 111 and an opening provided on the pad 102. The IC chip 111 is embedded in the hole and die-bonded. After being connected to the pad 102, the conductor 405 extends on the surface of the surface protection film 404 and is connected to the conductor 415. Here, a polymer resin such as polyimide is used as a material of the surface protective film 404.

(4) By connecting the conductors 405 and 415, the IC chip 101 serving as a support substrate and the built-in IC chip 111 are electrically connected inside the package. In the case where a plurality of IC chips are die-bonded on the IC chip 101, the plurality of built-in IC chips are also electrically connected via conductors formed on the surface of the IC chip serving as a support substrate. . Further, by providing a hole in the surface protection film 404 having an increased thickness and embedding the IC chip 111 therein, a step caused by the thickness of the IC chip 111 die-bonded to the IC chip 101 serving as a support substrate is provided. Can be improved at least as compared with the third embodiment.

(4) Such a structure is advantageous when selecting a manufacturing method for mounting the singulated IC chips on ICs in a wafer state before singulation. This is because conductors can be formed and patterned on the surface of the wafer and the IC chip 111 at the same time, and a structure for electrically connecting the conductors 405 and 415 can be formed at a time. Further, since the surface of the semiconductor package to be sealed with resin is flattened, sealing with the resin 130 is also facilitated. Note that in the present embodiment, the conductor 116 and the connection material 117 are not necessarily required.

According to the present embodiment, in addition to the effects of the third embodiment, the step caused by the thickness of the IC chip that is die-bonded to the IC chip serving as the support substrate is improved, so that the structure becomes the support substrate. This facilitates formation of a structure for electrically connecting the conductors on the IC chip and the conductors on the other IC chips to be incorporated. Also, resin sealing is facilitated.

FIG. 5 is a structural sectional view showing a fifth embodiment of the present invention. The present embodiment is significantly different from the above-described embodiment in that another IC chip 511 is face-down bonded on an IC chip 101 serving as a support substrate and is incorporated in a package. The IC chip 511 is a different chip from the IC chip 101 serving as a support substrate, and is ground smaller than the IC chip 101 and thin enough to be built in the same package.

パ ッ ド A pad 512 and a surface protection film 513 are formed on the IC chip 511. The pad 512 is electrically connected to the internal integrated circuit of the IC chip 511. The surface protection film 513 is for protecting the surface of the integrated circuit, covers the surface of the IC chip 512, and has an opening on the pad 512. Further, an electrode connection material 518 is formed outside the surface protection film 513 so as to be connected to the pad 512. As the electrode connection material 518, for example, a conductive resin formed by a bump electrode, printing, or the like can be used. The conductor 505 connected to the pad 102 of the IC chip 101 is formed to be longer than the conductor 105 of the first embodiment, and is electrically connected to the electrode connection material 518.

By connecting the conductor 505 and the electrode connection material 518, the IC chip 101 serving as a support substrate and the built-in IC chip 511 are electrically connected inside the package. Also, a plurality of built-in chips other than the IC chip 101 serving as the support substrate are electrically connected via conductors formed on the surface of the IC chip serving as the support substrate. Further, since the IC chip 511 is connected to an external terminal by the electrode connection material 518, the conductors 115 and 116, the connection material 117, and the like used in the above-described embodiment are not required. Further, since there are no conductors 115 and 116, only one layer of the surface protective film 513 is sufficient, and the surface protective film 114 is not required.

According to the present embodiment, in addition to the effects of the first embodiment, it is possible to make an electrical connection between a plurality of IC chips built in the semiconductor package inside the semiconductor package. Accordingly, it is not necessary to form a wiring in consideration of the electrical connection between the built-in IC chips on the connection substrate for connecting the semiconductor device. Further, since electrical connection between a plurality of IC chips built in the semiconductor package can be performed with shorter wiring, the speed of the semiconductor device can be increased. Further, as compared with the above-described embodiment, the processing for the IC chip other than the IC chip serving as the support substrate, which is built in the semiconductor package, can be simplified.

FIG. 6 is a structural sectional view showing a sixth embodiment of the present invention. In the present embodiment, similarly to the fifth embodiment, another IC chip 511 is face-down bonded onto an IC chip 101 serving as a support substrate and is incorporated in a package. However, in the present embodiment, a pad 602 is newly formed on the IC chip 101, and a conductor 605 is formed on the surface protective film 104 so as to be connected to the pad 602. The pad 602 is electrically connected to the internal integrated circuit of the IC chip 101. The surface protection films 103 and 104 have openings on the pads 602. Here, the conductor 605 is formed between the IC chip 101 and the IC chip 511, and is electrically connected to the electrode connection material 518 of the IC chip 511. Unlike the conductor 105, the conductor 605 is not connected to the conductor 106 and the connection material 107 that can be connected to external terminals. The pad 602 is arranged at a position suitable for connecting the conductor 605 and the electrode connection material 518.

(4) Since the pad 602 and the conductor 605 are provided and the conductor 605 and the electrode connection material 518 are connected, the IC chip 101 serving as a support substrate and the built-in IC chip 511 are electrically connected inside the package. Further, when bonding a plurality of IC chips on the IC chip 101, the plurality of built-in IC chips can be electrically connected via the conductor 605.

According to the present embodiment, in addition to the effects of the fifth embodiment, the electrical connection of each internal integrated circuit between an IC chip serving as a support substrate and an IC chip built in another semiconductor package is achieved. Is possible, the degree of freedom of wiring is increased, and a higher-density internal wiring structure can be provided.

FIG. 7 is a structural sectional view showing a seventh embodiment of the present invention. In this embodiment, as in the fifth and sixth embodiments, another IC chip 711 is face-down bonded onto the IC chip 101 serving as a support substrate and is incorporated in a package. However, in this embodiment, a through electrode 719 is newly provided inside the IC chip 711 in addition to the structure of the fifth embodiment. The penetrating electrode 719 penetrates the IC chip 711 and has a conductor 720 inside. The conductor 720 is insulated from the semiconductor substrate of the IC chip 711. Here, the through electrode 719 is illustrated as being composed of the through hole and the conductor 720 provided on the side wall of the through hole, but may have a structure other than the above. For example, a columnar conductor penetrating the IC chip 711 may be provided so as to be insulated from the semiconductor substrate of the IC chip 711.

(4) A pad 712, a surface protection film 513, and an electrode connection material 518 are formed on the surface of the IC chip 711 facing the IC chip 101. The pad 712 is connected to the through electrode 719 and is electrically connected to the internal integrated circuit of the IC chip 101. The surface protection film 513 covers the surface of the IC chip 711 and has an opening on the pad 712. The electrode connection material 518 is connected to the pad 712 and also to the conductor 505 on the IC chip 101.

{Circle around (2)} On the back surface of the IC chip 711, a back electrode 722 and two layers of surface protection films 713 and 714 are formed. The back surface electrode 722 is electrically connected to the through electrode 719. The surface protection films 713 and 714 are for protecting the surface of the wiring formed on the back surface of the IC chip 711 and have openings on the back surface electrodes 722. Further, a conductor 715 is connected to the back surface electrode 722 and connected to the conductor 715 on the surface protection film 714, a columnar conductor 116 is connected to the conductor 715, and a connection material 117 is formed on the conductor 116.

With the above configuration, one end of the through electrode 719 is connected to the IC chip 101 via the electrode connection material 518 and the conductor 505, and the other end is connected to a conductor to the outside of the package. Thus, the electrical connection from the IC chip 711 to the outside of the package directly through the through electrode 719 becomes possible.

According to this embodiment, in addition to the effects of the fifth embodiment, each IC can be electrically connected between an IC chip serving as a support substrate and an IC chip built in another semiconductor package. It is. In addition, it is possible to make an electrical connection directly from the built-in IC chip other than the support substrate to the outside of the semiconductor package. Thus, a semiconductor package having a larger number of pins can be provided, and the degree of freedom in wiring can be increased.

Although the example in which the connection materials 107 and 117 are provided has been described above, since the surfaces of the conductors 106 and 116 are exposed on the surface of the resin 130, even when the connection materials 107 and 117 are omitted, the electrical connection with the outside is made. Connection is possible. The effects of the present invention can be obtained. When the connection materials 107 and 117 are omitted, there is an advantage that a lower-cost semiconductor device can be provided.

FIG. 11 is a structural sectional view showing an eighth embodiment of the present invention. This is one example in which the present invention is applied to the conventional CSP shown in FIG. Another IC chip 811 is die-bonded on an IC chip 801 serving as a support substrate and is incorporated in a package. The size of the IC chip 801 serving as a support substrate is equal to the size of the package.

ア ル ミ An aluminum electrode pad 802 is formed on the IC chip 801. The aluminum electrode pad 802 is electrically connected to the internal integrated circuit of the IC chip 801. A copper post 805, which is a columnar conductor, is formed so as to be connected to the aluminum electrode pad 802. Further, an IC chip 811 is fixed on the IC chip 801 via an adhesive sheet 808. The IC chip 811 is a different chip from the IC chip 801 serving as a support substrate, and is ground smaller than the IC chip 801 and thin enough to be built in the same package. An aluminum electrode pad 812 is formed on the IC chip 811. The aluminum electrode pad 812 is electrically connected to the internal integrated circuit of the IC chip 811. A gold bump 815 is formed in connection with the aluminum electrode pad 812.

The resin 830 seals at least the integrated circuit forming surface of all the IC chips. A plurality of rewiring patterns 806 having a surface plated with gold, tin, or the like are formed at predetermined positions on the resin 830, on the copper posts 805, and on the gold hair bumps 815 at intervals. On the rewiring pattern 806, solder balls 807 for external connection terminals are formed.

(4) The copper post 805 enables electrical connection from the aluminum electrode pad 802 to the external terminal of the package, and the solder ball 807 allows the package to be connected to the external substrate. That is, a series of connected aluminum electrode pads 802, copper posts 805, rewiring patterns 806, and solder balls 807 can electrically connect an internal integrated circuit of the IC chip 801 to an external substrate of the package.

Similarly, the gold bumps 815 can electrically connect the aluminum electrode pads 812 to external terminals of the package, and the solder balls 807 can connect the package to an external substrate. That is, a series of connected aluminum electrode pads 812, gold bumps 815, rewiring patterns 806, and solder balls 807 can electrically connect the internal integrated circuit of the IC chip 811 to the external substrate of the package. Further, the IC chip 801 and the IC chip 811 can be connected by the rewiring pattern 806 and the solder balls 807. As described above, according to the present embodiment, the same effects as those of the first embodiment can be obtained.

Hereinafter, an example of the manufacturing method according to the eighth embodiment will be described with reference to FIG. First, the IC chip 801 is prepared with the aluminum electrode pad 802 formed thereon, and the IC chip 811 is prepared with the aluminum electrode pad 812 and the gold bump 815 formed thereon. Here, the case of the IC chip 801 in a wafer state before being singulated will be described. In FIG. 15A, a wafer 881 is a wafer on which semiconductor elements to be IC chips 801 are formed, and an aluminum electrode pad 802 is formed thereon.

Next, as shown in FIG. 15B, a copper post 805 is formed on the aluminum electrode pad 802. The formation of the copper post 805 can be obtained by sequentially performing the steps of vapor deposition of a metal film on the entire surface of the wafer 881, application of a photosensitive resist, patterning, copper plating, removal of the photosensitive resist, and removal of an unnecessary metal film. Next, as shown in FIG. 15C, the IC chip 811 on which the aluminum electrode pads 812 and the gold bumps 815 are formed is mounted on the wafer 881 using the adhesive sheet 808.

(5) Thereafter, as shown in FIG. 15D, the entire surface of the wafer 881 is sealed with a resin 830 to be protected. In this state, both the copper post 805 and the gold bump 815 are buried in the resin 830. Next, as shown in FIG. 15E, the upper surface of the resin 830 is shaved until the copper posts 805 and the gold bumps 815 are exposed.

Next, as shown in FIG. 15F, a rewiring pattern 806 is formed on the resin 830, the copper posts 805, and the gold bumps 815. The rewiring pattern 806 is formed by depositing a metal film on the entire surface of the resin 830, applying a photosensitive resist, patterning, copper plating, removing the photosensitive resist, removing an extra metal film, and electroless tin (or gold) plating. It is obtained by performing the steps in order.

(5) Next, as shown in FIG. 15G, a solder ball 807 is formed on the rewiring pattern 806. Finally, the wafer is diced and singulated as shown in FIG. 15H to complete the CSP of the eighth embodiment.

FIG. 12 is a structural sectional view showing a ninth embodiment of the present invention. This is also one example in which the present invention is applied to the conventional CSP shown in FIG. A major difference from the eighth embodiment is that another IC chip 911 is face-down bonded on an IC chip 801 serving as a support substrate and is incorporated in a package. The size of the IC chip 801 serving as a support substrate is equal to the size of the package. The IC chip 911 is a different chip from the IC chip 801 serving as a support substrate, and is ground smaller than the IC chip 801 and thin enough to be built in the same package.

In the present embodiment, as compared with the eighth embodiment, in addition to the aluminum electrode pad 802, an aluminum electrode pad 902 is formed on the IC chip 801 at a position facing the IC chip 911. Then, instead of the aluminum electrode pad 812, an aluminum electrode pad 912 is formed on the surface of the IC chip 911 facing the IC chip 801. A gold bump 915 is formed between the aluminum electrode pad 902 and the aluminum electrode pad 912 so as to be connected to both. In this manner, the bonding of the IC chip 911 does not use the adhesive sheet 808. Further, there is no conductor directly connecting the IC chip 911 and the rewiring pattern 806. Other configurations are the same as those of the eighth embodiment.

(5) The aluminum electrode pads 802 and 902 are electrically connected to the internal integrated circuit of the IC chip 801. The aluminum electrode pad 912 is electrically connected to the internal integrated circuit of the IC chip 911. Therefore, the IC chips 801 and 911 are electrically connected inside the package. When it is desired to connect the IC chip 911 to an external substrate, the connection can be made via the IC chip 801, the rewiring pattern 806, and the solder balls 807. In this embodiment mode, an inexpensive CSP can be provided because the adhesive sheet 808 is not used. As described above, according to the present embodiment, the same effects as in the fifth embodiment can be obtained.

Hereinafter, an example of the manufacturing method according to the ninth embodiment will be described with reference to FIG. First, the IC chip 801 is prepared in a state where aluminum electrode pads 802 and 902 are formed, and the IC chip 911 is prepared in a state where an aluminum electrode pad 912 and a gold bump 915 are formed thereon. Here, the case of the IC chip 801 in a wafer state before being singulated will be described. In FIG. 16A, a wafer 881 is a wafer on which semiconductor elements to be IC chips 801 are formed, on which aluminum electrode pads 802 and 902 are formed.

Next, as shown in FIG. 16B, a copper post 805 is formed on the aluminum electrode pad 802. The formation of the copper post 805 is performed in the same manner as described with reference to FIG. Next, as shown in FIG. 16C, the IC chip 911 on which the aluminum electrode pads 912 and the gold bumps 915 are formed is mounted on the wafer 881 by face-down bonding. Thereafter, as shown in FIG. 16D, the entire surface of the wafer 881 is sealed with a resin 830. Next, as shown in FIG. 16E, the upper surface of the resin 830 is shaved until the copper posts 805 are exposed.

Next, as shown in FIG. 16F, a rewiring pattern 806 is formed on the resin 830 and the copper posts 805. The formation of the rewiring pattern 806 is performed in the same manner as described with reference to FIG. The subsequent steps shown in FIGS. 16 (g) and 16 (h) are the same as those described with reference to FIGS. 15 (g) and 15 (h). As described above, the CSP according to the ninth embodiment is completed.

FIG. 13 is a structural sectional view showing a tenth embodiment of the present invention. This is different from the ninth embodiment in that the solder balls 807 are eliminated. Other configurations are the same as in the ninth embodiment. By omitting the solder ball 807, a further low-cost CSP can be provided.

FIG. 14 is a structural sectional view showing an eleventh embodiment of the present invention. In this case, the number of IC chips incorporated by face-down bonding is reduced to two. Other configurations are the same as in the ninth embodiment. The built-in IC chips 921 and 931 may be the same or different. The number of built-in IC chips is not limited to two, but may be three or more. By increasing the number of built-in IC chips, a more sophisticated CSP can be provided.

Although the preferred embodiment according to the present invention has been described with reference to the accompanying drawings, it goes without saying that the present invention is not limited to such an example. It is clear that those skilled in the art can conceive various changes or modifications within the scope of the technical idea described in the claims. It is understood that it belongs to.

FIG. 1 is a structural cross-sectional view illustrating a first embodiment of the present invention. FIG. 4 is a structural sectional view showing a second embodiment of the present invention. It is a structural sectional view showing a third embodiment of the present invention. FIG. 9 is a structural sectional view showing a fourth embodiment of the present invention. FIG. 13 is a structural sectional view showing a fifth embodiment of the present invention. FIG. 14 is a structural sectional view showing a sixth embodiment of the present invention. It is a structural sectional view showing a seventh embodiment of the present invention. FIG. 2 is a diagram in which the semiconductor package according to the first embodiment of the present invention is mounted on a mounting board. FIG. 4 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. It is a structural sectional view showing an eighth embodiment of the present invention. It is a structure sectional view showing a 9th embodiment of the present invention. It is a structure sectional view showing a 10th embodiment of the present invention. It is a structural sectional view showing an eleventh embodiment of the present invention. FIG. 21 is a diagram illustrating a method for manufacturing the semiconductor device according to the eighth embodiment of the present invention. FIG. 21 is a diagram illustrating the method for manufacturing the semiconductor device according to the ninth embodiment of the present invention. FIG. 11 is a structural sectional view showing a conventional semiconductor device.

Explanation of reference numerals

REFERENCE SIGNS LIST 100 Semiconductor device 101, 111 IC chip 102, 112 Pad 103, 104, 113, 114 Surface protective film 105, 106, 115, 116 Conductor 107, 117 Connection material 108 Die bonding material 130 Resin

Claims (37)

A first IC chip having a main surface on which a first pad is formed; a first protective film covering a main surface of the first IC chip so as to expose a part of the first pad; ,
A first surface on which a second pad is formed; and a second surface facing the first surface, wherein the first protective film is formed such that the second surface faces the first protective film. A second IC chip provided above,
A second protective film covering a first surface of the second IC chip so as to expose a part of the second pad;
A conductor provided on the second pad and the second protective film and electrically connected to the second pad;
A columnar conductor provided on the conductor and electrically connected to the conductor;
A semiconductor device, comprising: a first and a second protective films; and a resin covering the conductor and a side surface of the second IC chip so that one end of the columnar conductor is exposed. 4. The semiconductor device according to claim 1, wherein a connection material is provided at one end of the columnar conductor exposed from the resin. 2. The semiconductor according to claim 1, wherein a distance from an outer edge of said second IC chip to said second pad is shorter than a distance from an outer edge of said second IC chip to said columnar conductor. apparatus. A second conductor provided on the first pad and the first protective film and electrically connected to the first pad;
4. The semiconductor device according to claim 1, further comprising: a second columnar conductor provided on the second conductor such that one end is exposed from the resin, and a second columnar conductor electrically connected to the second conductor. 5. A semiconductor device according to one of the above. 5. The semiconductor device according to claim 4, wherein a second connection material is provided at one end of the second columnar conductor exposed from the resin. The distance from the outer edge of the first IC chip to the first pad is shorter than the distance from the outer edge of the first IC chip to the second columnar conductor. 13. The semiconductor device according to claim 1. 4. The semiconductor device according to claim 1, wherein a cut surface cut by dicing is formed on a side surface of the first IC chip and a side surface of the resin. A first IC chip having a main surface on which pads are formed;
A protective film covering a main surface of the first IC chip so as to expose a part of the pad;
A conductor provided on the pad and the protective film and electrically connected to the pad;
A columnar conductor provided on the conductor and electrically connected to the conductor;
A second IC chip provided on the conductor,
A semiconductor device comprising a resin covering the protective film, the conductor, and the second IC chip such that one end of the columnar conductor is exposed. 9. The semiconductor device according to claim 8, wherein a connection material is provided at one end of the columnar conductor exposed from the resin. 9. The semiconductor device according to claim 8, wherein a distance from an outer edge of the first IC chip to the pad is shorter than a distance from an outer edge of the first IC chip to the columnar conductor. The second IC chip has a first surface on which a second pad is formed and a second surface facing the conductor,
A second protective film covering a first surface of the second IC chip so as to expose a part of the second pad;
A second conductor provided on the second pad and the second protective film and electrically connected to the second pad;
11. The semiconductor device according to claim 8, further comprising: a second columnar conductor provided on the second conductor such that one end is exposed from the resin, and a second columnar conductor electrically connected to the second conductor. A semiconductor device according to one of the above. 12. The semiconductor device according to claim 11, wherein a second connection material is provided at one end of the second columnar conductor exposed from the resin. The distance from the outer edge of the second IC chip to the second pad is shorter than the distance from the outer edge of the second IC chip to the second columnar conductor. 13. The semiconductor device according to claim 1. 9. The semiconductor device according to claim 8, wherein cut surfaces cut by dicing are formed on a side surface of the first IC chip and a side surface of the resin. A first IC chip having a main surface on which a first pad is formed; a first protective film covering a main surface of the first IC chip so as to expose a part of the first pad; ,
A first surface on which a second pad is formed; and a second surface facing the first surface, wherein the first protective film is formed such that the second surface faces the first protective film. A second IC chip provided thereon, a second protective film covering a first surface of the second IC chip so as to expose a part of the second pad,
A conductor provided on the first and second pads and the first and second protective films and electrically connected to the first and second pads;
A columnar conductor provided on the conductor and electrically connected to the conductor;
A semiconductor device, comprising: a first and a second protective films; and a resin covering the conductor and a side surface of the second IC chip so that one end of the columnar conductor is exposed. 16. The semiconductor device according to claim 15, wherein a connection material is provided at one end of the columnar conductor exposed from the resin. 16. The semiconductor device according to claim 15, wherein the columnar conductor is formed on the conductor formed on a main surface of the first IC chip. 18. The semiconductor according to claim 17, wherein a distance from an outer edge of the first IC chip to the first pad is shorter than a distance from an outer edge of the first IC chip to the columnar conductor. apparatus. 16. The semiconductor device according to claim 15, wherein the columnar conductor is formed on the conductor formed on a main surface of the second IC chip. 20. The semiconductor according to claim 19, wherein a distance from an outer edge of the second IC chip to the second pad is shorter than a distance from an outer edge of the second IC chip to the columnar conductor. apparatus. 17. The semiconductor device according to claim 15, wherein the first IC chip is a logic chip, and the second IC chip is a memory chip. 17. The semiconductor device according to claim 15, wherein both the first and second IC chips are logic chips. 17. The semiconductor device according to claim 15, wherein both the first and second IC chips are memory chips. 16. The semiconductor device according to claim 15, wherein a cut surface cut by dicing is formed on a side surface of the first IC chip and a side surface of the resin. A first IC chip having a main surface on which a first pad is formed;
A protective film covering a main surface of the first IC chip so as to expose a part of the first pad;
It has a first surface on which a second pad is formed, and a second surface facing the first surface, and the first surface and the second surface are the protective film except for a part of the second pad. A second IC chip covered by
A conductor provided on the first and second pads and the protective film, and electrically connected to the first and second pads;
A columnar conductor provided on the conductor and electrically connected to the conductor;
A semiconductor device comprising a resin covering the protective film and the conductor so as to expose one end of the columnar conductor. 26. The semiconductor device according to claim 25, wherein a connection material is provided at one end of the columnar conductor exposed from the resin. 26. The semiconductor according to claim 25, wherein a distance from an outer edge of the first IC chip to the first pad is shorter than a distance from an outer edge of the first IC chip to the columnar conductor. apparatus. The column-shaped conductor is provided on the conductor on the second IC chip, and a distance from an outer edge of the second IC chip to the second pad is equal to a distance from an outer edge of the second IC chip. 26. The semiconductor device according to claim 25, wherein the distance is shorter than a distance to the columnar conductor. 26. The semiconductor device according to claim 25, wherein a cut surface cut by dicing is formed on a side surface of the first IC chip and a side surface of the resin. A first IC chip having a main surface on which a first pad is formed;
A first columnar conductor provided on the first pad and electrically connected to the pad;
A first surface on which a second pad is formed; and a second surface facing the first surface, wherein the first surface is arranged such that the second surface faces a main surface of the first IC chip. A second IC chip provided on a main surface of the IC chip,
A second columnar conductor provided on the second pad and electrically connected to the pad;
The first and second pillar-shaped conductors are formed of a resin covering the main surface of the first IC chip and the first and side surfaces of the second IC chip so as to expose one ends of the first and second columnar conductors. Characteristic semiconductor device. 31. The semiconductor device according to claim 30, wherein a connection material is provided at one end of the first columnar conductor exposed from the resin. 31. The semiconductor device according to claim 30, wherein a second connection material is provided at one end of the second columnar conductor exposed from the resin. 31. The semiconductor device according to claim 30, wherein a cut surface cut by dicing is formed on a side surface of the first IC chip and a side surface of the resin. A semiconductor device comprising a first IC chip and a second IC chip mounted on a main surface of the first chip,
The second IC chip has a first surface on which an integrated circuit is formed, and a second surface facing the first surface, and the second surface faces a main surface of the first IC chip. Mounted on the main surface as
Resin that covers the main surface of the first IC chip and the first surface and side surfaces of the second IC chip, leaving a part of the columnar conductor formed on the first surface of the second IC chip A semiconductor device comprising: 35. The semiconductor device according to claim 34, wherein cut surfaces cut by dicing are formed on a side surface of the first IC chip and a side surface of the resin. The first IC chip and the second IC chip are built in one package, and the size of the package is equal to the larger size of the first IC chip and the second IC chip. 35. The semiconductor device according to claim 34, wherein: A semiconductor device in which a plurality of IC chips on which a semiconductor integrated circuit is formed are built in one package, and the size of the package is equal to the size of the largest IC chip among the plurality of built-in IC chips. A manufacturing method,
Preparing a wafer on which an IC to be the largest IC chip is formed;
Preparing the built-in IC chip other than the largest IC chip;
Forming a surface protective film on the wafer,
Forming a hole of the same size as the built-in IC chip in the surface protective film;
Mounting the built-in IC chip in the hole;
Forming a conductor and patterning the conductor on the surface of the wafer and the mounted IC chip at the same time.

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