JP3923944B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a multi-chip semiconductor device using a chip size package and a method for manufacturing the semiconductor device.

  With the recent miniaturization of electronic devices, various methods enabling high-density mounting are being studied when mounting semiconductor devices. Among these methods, there are methods for reducing the size of a semiconductor device and increasing the density of mounting a plurality of components. As for miniaturization of a semiconductor device, miniaturization of a semiconductor package containing an IC chip has been studied, and there is a semiconductor package called a chip size package (hereinafter abbreviated as CSP) having almost the same size as the IC chip. To increase the mounting density of a plurality of components, a multichip module (hereinafter abbreviated as MCM) or a multichip package (hereinafter abbreviated as MCP) in which a plurality of IC chips and other components are incorporated in a single module or package. )

  An example of the structure of a conventional CSP is shown in FIG. An aluminum electrode pad 2 is formed on the IC chip 1. The aluminum electrode pad 2 is electrically connected to the internal integrated circuit of the IC chip 1. Connected to the aluminum electrode pad 2, a copper post 5 as a columnar conductor is formed thereon. The resin 30 seals at least the integrated circuit formation surface of the conductor and the IC chip 1.

  A plurality of rewiring patterns 6 whose surfaces are plated with gold, tin or the like are formed at predetermined positions on the copper posts 5 and the resin 30 at intervals. On the rewiring pattern 6, solder balls 7 for external connection terminals are formed. The aluminum electrode pad 2, the copper post 5, the rewiring pattern 6, and the solder ball 7 are electrically connected. As a result, the internal integrated circuit of the IC chip 1 can be electrically connected to the external substrate. In this way, a package of almost the same size as the IC chip 1 is configured.

  However, among the CSPs described above, a CSP that does not incorporate an intermediate substrate, particularly called an interposer, cannot incorporate a plurality of IC chips due to its outer size and structure, and is difficult to be converted into an MCP. Therefore, when a plurality of semiconductor packages on a mounting substrate are electrically wired, the wiring length becomes long, which is an obstacle not only in high-density mounting but also in speeding up the final electronic device.

  On the other hand, in a semiconductor package with a built-in interposer, a plurality of IC chips can be mounted on the interposer, but the package size is larger than that of the IC chip, and the package cost is high because the interposer is built-in. There was a problem.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a semiconductor device capable of MCP in a CSP that does not incorporate an interposer and a method for manufacturing the semiconductor device.

  In order to solve the above-described problem, according to one aspect of the present invention, a first IC chip having a main surface on which a first pad is formed and a part of the first pad are exposed. A first protective film covering a main surface of the first IC chip; a first surface on which a second pad is formed; and a second surface opposite to the first surface, wherein the second surface is The second IC chip provided on the first protective film so as to face the first protective film, and the second IC chip so as to expose a part of the second pad. A second protective film covering the first surface; and a conductor provided on the second pad and the second protective film and electrically connected to the second pad; and provided on the conductor. A columnar conductor electrically connected to the conductor, and the first and second protective films so as to expose one end of the columnar conductor. Wherein a is constituted by a resin covering the conductor with the side surface of the second IC chip is provided.

  In order to solve the above problems, according to another aspect of the present invention, a first IC chip having a main surface on which a pad is formed, and the first IC so as to expose a part of the pad. A protective film covering the main surface of the chip, a conductor provided on the pad and the protective film, electrically connected to the pad, and a columnar shape provided on the conductor and electrically connected to the conductor A conductor, a second IC chip provided on the conductor, and a resin that covers the protective film, the conductor, and the second IC chip so as to expose one end of the columnar conductor. A semiconductor device is provided.

  In order to solve the above-described problem, according to another aspect of the present invention, a first IC chip having a main surface on which a first pad is formed and a part of the first pad are exposed. A first protective film covering a main surface of the first IC chip, a first surface on which a second pad is formed, and a second surface facing the first surface, the second surface A second IC chip provided on the first protective film so as to face the first protective film, and the second IC chip so as to expose a part of the second pad Provided on the first and second pads and the first and second protective films, and electrically connected to the first and second pads. A conductor provided on the conductor and electrically connected to the conductor, and one end of the pillar conductor is exposed. Wherein a is constituted by a resin covering the first and second protective film and the conductor and the side surface of the second IC chip is provided.

  In order to solve the above-described problem, according to another aspect of the present invention, a first IC chip having a main surface on which a first pad is formed and a part of the first pad are exposed. A protective film that covers the main surface of the first IC chip, a first surface on which a second pad is formed, and a second surface that faces the first surface. Except for the first portion, the first surface and the second surface are provided on the first IC chip, the second IC chip covered with the protective film, the first pad, the second pad, and the protective film. A conductor electrically connected to the two pads, a columnar conductor provided on the conductor and electrically connected to the conductor, and the protective film and the conductor so as to expose one end of the columnar conductor A semiconductor device is provided that is made of a resin that covers the substrate.

  In order to solve the above-described problem, according to another aspect of the present invention, a first IC chip having a main surface on which a first pad is formed, and the pad provided on the first pad, A first columnar conductor electrically connected; a first surface on which a second pad is formed; and a second surface opposite to the first surface, wherein the second surface is the first IC. A second IC chip provided on the main surface of the first IC chip so as to face the main surface of the chip; and a second IC chip provided on the second pad and electrically connected to the pad. Two columnar conductors, and a resin that covers the main surface of the first IC chip and the first and side surfaces of the second IC chip so as to expose one end of the first and second columnar conductors. The semiconductor device characterized by comprising is provided.

  In order to solve the above problems, according to another aspect of the present invention, there is provided a semiconductor device including a first IC chip and a second IC chip mounted on the main surface of the first chip. The second IC chip has a first surface on which an integrated circuit is formed and a second surface facing the first surface, and the second surface is a main surface of the first IC chip. The main surface of the first IC chip and the second surface are mounted on the main surface so as to face each other, leaving a part of the columnar conductor formed on the first surface of the second IC chip. There is provided a semiconductor device comprising a resin that covers a first surface and a side surface of an IC chip.

  In order to solve the above-described problems, according to another aspect of the present invention, a plurality of IC chips on which semiconductor integrated circuits are formed are built in one package, and the size of the package is the plurality of built-in plurality of chips. A method of manufacturing a semiconductor device having a size equivalent to the largest IC chip among the IC chips, comprising: preparing a wafer on which an IC to be the largest IC chip is formed; Preparing the built-in IC chip, forming a surface protective film on the wafer, forming a hole of the same size as the built-in IC chip in the surface protective film, and the hole A step of mounting the built-in IC chip on a portion, and a step of simultaneously forming a conductor and patterning the wafer and the surface of the mounted IC chip. The method of manufacturing a semiconductor device according to symptoms is provided.

  As described above in detail, according to the present invention, it is possible to provide a semiconductor device and a method for manufacturing the semiconductor device that can be made MCP in a CSP that does not incorporate an interposer.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

  FIG. 1 is a structural cross-sectional view showing a first embodiment of the present invention. Another IC chip 111 is die-bonded on the IC chip 101 serving as a support substrate and incorporated in the package. The size of the package is the same as that of the IC chip 101 as the support substrate.

  On the IC chip 101, a pad 102 and two layers of surface protective films 103 and 104 are formed. The pad 102 is electrically connected to the internal integrated circuit of the IC chip 101. The surface protective films 103 and 104 are for protecting the surface of the integrated circuit, and have an opening on the pad 102. Further, a conductor 105 is connected to the pad 102, a columnar conductor 106 is connected to the conductor 105, and a connection material 107 is formed on the conductor 106.

  The conductors 105 and 106 can be electrically connected from the pad 102 to the external terminals of the package, and the connection material 107 can connect the package to an external substrate (not shown). That is, the internal integrated circuit of the IC chip 101 and the external substrate can be electrically connected by the series of connected pads 102, conductors 105 and 106, and connection material 107.

  An IC chip 111 is die-bonded on the surface protective film 104 via a die bonding material 108. The IC chip 111 is a chip different from the IC chip 101 serving as a support substrate, and is ground to be smaller than the IC chip 101 and thin enough to be incorporated in the same package.

  A pad 112 and two layers of surface protective films 113 and 114 are formed on the IC chip 111. The pad 112 is electrically connected to the internal integrated circuit of the IC chip 111. The surface protection films 113 and 114 are for protecting the surface of the integrated circuit, and have openings on the pads 112. Further, a conductor 115 connected to the pad 112 and a columnar conductor 116 connected to the conductor 115 and a connecting material 117 formed on the conductor 116 are formed on the surface protective film 114. The resin 130 seals at least the integrated circuit formation surface of all IC chips.

  The conductors 115 and 116 can be electrically connected from the pad 112 to the external terminal of the package, and the connection material 117 can connect the package to the external substrate. That is, the internal integrated circuit of the IC chip 111 and the external substrate of the package can be electrically connected by the series of connected pads 112, conductors 115 and 116, and the connection material 117.

  The surface protective films 103, 104 and 113, 114 are surface protective films of the IC chips 101 and 111, respectively. Here, the surface protective films 103 and 113 are silicon oxide films or silicon nitride films, and the surface protective films 104 and 114 are films made of a polymer resin such as polyimide. These surface protective films may have a single layer structure, but by using a composite layer structure, they are integrated from the effects of processing such as conductor formation on the IC chip and die bonding, and the effects of thermal stress after the package is connected to the substrate. The circuit can be further protected.

  The conductors 105 and 115 are conductor wirings connecting the pad 102 and the conductor 106 and the pad 112 and the conductor 116, respectively. Here, it is assumed to be a metal material having a composite layer structure composed of titanium and copper. In this case, the titanium layer is formed for adhesion to the pad and the surface protective film and the function of preventing diffusion, and the copper layer is formed mainly for the function as an electrical connection material. Of course, a single layer structure may be used, and the material structure is not questioned. Various examples of the material structure in the case of the composite layer structure include chrome-copper, chrome-gold, nickel-copper, nickel-gold, titanium / tungsten-copper, and titanium / tungsten-gold.

  The conductors 106 and 116 are conductors for making an electrical connection from the conductors 105 and 115 to the outside of the package, respectively, and at least a part thereof needs to be exposed from the resin 130. The material is preferably a material with low electrical resistance, and examples thereof include copper, gold, and aluminum.

  In FIG. 1, only one IC chip 111 is shown as the built-in IC chip other than the IC chip serving as the support substrate, but a plurality of IC chips may be used. This also applies to the embodiments described below. Here, if the IC chip 101 serving as a support substrate is a logic chip and the built-in IC chip 111 is a memory chip, the logic system and the memory system can be mixedly mounted. Further, the combination of the IC chips is not limited to the above, and may be memory-based semiconductor elements or logic-based semiconductor elements.

  FIG. 8 is a diagram in which the semiconductor package having the structure shown in FIG. 1 is mounted on a mounting substrate. The semiconductor device 100 incorporating the IC chips 101 and 111 is mounted on the mounting substrate 150 by the wiring 151 on the mounting substrate. In FIG. 8, the upper and lower sides of the semiconductor device 100 are opposite to those in FIG. By mounting the semiconductor device 100 on the mounting substrate 150, the IC chips 101 and 111 are electrically connected to the wiring 151 on the mounting substrate. In the state of the semiconductor device 100 alone, the IC chips 101 and 111 are not electrically connected directly, but when mounted on the mounting substrate 150, the IC chip 101 and the IC chip 111 are connected via the mounting substrate wiring 151. It is connected.

  Hereinafter, a method of mounting the IC chip 111 on the IC chip 101 will be described with reference to FIG. First, in the IC chip 101, the pad 102, the surface protective films 103 and 104, and the conductors 105 and 106 are formed. In the IC chip 111, the pad 112, the surface protective films 113 and 114, and the conductors 115 and 116 are formed. Prepare the ones that have been released. Here, the IC chip 101 may be either diced and separated or a wafer state before dicing.

  When the IC chip 111 is die-bonded to the IC chip 101, if the IC chip 101 is an individualized IC chip, the individualized IC chip 199 is separated into individual pieces as shown in FIG. Bonding is performed on the formed IC chip 191 with the die bonding material 108. If the IC chip 101 is in a wafer state before dicing, the separated IC chip 199 is bonded to the wafer 181 with a die bonding material 108 as shown in FIG.

  Since the semiconductor package is required to be miniaturized to the limit possible, it is desired that the IC chip 101 and the IC chip 111 be as thin as possible and die-bonded in parallel. Therefore, it is preferable that the die bonding material 108 be thin and have a uniform thickness. As the die bonding material 108, various materials such as a conductive paste mainly composed of silver, a liquid polyimide, and a sheet-like adhesive can be considered.

  When the separated IC chip is mounted on the IC chip serving as the support substrate, there is no concern that the two IC chips are damaged. On the other hand, when an individualized IC chip is mounted on an IC in a wafer state before being singulated, there is an advantage that the subsequent processes can be collectively processed in units of wafers, thereby facilitating manufacturing.

  Next, a method of exposing the conductors on the same surface of the package in the columnar conductors 106 and 116 for electrical connection to the outside of the semiconductor package will be described with reference to FIG. When the IC chip 111 is mounted on the IC chip 101 described above, the conductors 106 and 116 formed on the IC chip 111 generally have uneven heights as shown in FIG. The columnar conductors 106 and 116 are formed by forming a pattern with a thick film resist and performing plating, or by bonding and fixing existing fine columnar parts. However, it is difficult to adjust the heights of the conductors 106 and 116 in advance when forming the conductors so that the uppermost surfaces of the conductors 106 and 116 are uniformly exposed on the same surface when the IC chip 111 is mounted on the IC chip 101. It is.

  Therefore, the IC chip 111 is mounted on the IC chip 101, and the conductors 106 and 116 are sealed with the resin 130 up to the surface 1001 higher than the uppermost surface of the conductors 106 and 116 in an uneven state. Next, the resin 130 is polished or etched to the surface 1002. At this time, the conductors 106 and 116 are simultaneously polished or etched. Thereby, the columnar conductors 106 and 116 formed on each IC can be exposed on the same surface of the package.

  Next, an electrical test method for an MCP semiconductor device provided in the present invention will be described. There are two methods for this depending on the state of the semiconductor device. One is a state in which an MCP semiconductor device is singulated, and a test is performed for each singulated package. The other method is a test method in which an IC serving as a support substrate is in a wafer state, and a built-in IC chip is mounted, resin-sealed, and a columnar conductor is exposed.

  Since the former test method can be individually tested, the test is surely performed, and defective products can be separated from non-defective products when they are found. The latter test method can be applied to a so-called blowing method, and it is not necessary to prepare a special jig such as a special test socket as compared with the former test method. In any case, it is not only combined after individually testing each built-in IC, but also an electrical connection between a plurality of built-in ICs and combinations by conducting an electrical test on the MCP-made semiconductor device. It is possible to test functions that can be confirmed for the first time.

  As described above, according to the present embodiment, a number of effects described below can be obtained. Since it is an MCP that can incorporate multiple IC chips without using an interposer, and the package size may be the same as the largest IC chip built-in, high-density mounting is possible on the mounting substrate. It becomes possible. In addition, since a plurality of IC chips are incorporated in a semiconductor package and all are sealed with resin, reliability in moisture resistance and the like is higher than that in which another IC chip is mounted outside the package. Since a plurality of IC chips can be mounted simultaneously, the number of mounting processing steps for the mounting substrate is reduced, and the cost can be reduced. By mounting one MCP on the mounting substrate, a plurality of built-in IC chips can be electrically connected simultaneously.

  In addition, when the IC as the support substrate is separated, another IC chip is mounted on the separated IC chip, so that the adjacent IC chip is separated before being separated. This eliminates problems such as scratching the IC chip. When the IC to be the support substrate is in a wafer state, a plurality of individual IC chips are mounted on the wafer, and the resin sealing, conductor exposure, and terminal processing, which will be performed in the subsequent steps, can be processed in batches for each wafer. Easy to manufacture.

A plurality of individual IC chips are mounted on an IC serving as a support substrate, and after sealing the resin, the columnar conductor formed on each IC is polished or etched together with the resin, so that the semiconductor package can be easily Columnar conductors can be uniformly exposed on the same surface.

  By adopting a test method that conducts an electrical inspection with multiple IC chips built into a single semiconductor package, it is possible to ensure that the test is performed and that defective products can be separated from non-defective products at that time. is there. A test method in which an IC serving as a support substrate is in a wafer state, and another individual IC chip is mounted, resin-sealed, and an electrical inspection is performed before the IC serving as a support substrate is separated into individual pieces. In this case, a so-called blowing method can be applied, and it is not necessary to prepare a special jig such as a test socket as compared with the former test method. By conducting an electrical test using an MCP-made semiconductor device, it is possible to test electrical functions between a plurality of built-in ICs and a function that can be confirmed only in combination.

  FIG. 2 is a structural cross-sectional view showing a second embodiment of the present invention. In the present embodiment, one of the conductors 105 is replaced with a conductor 205. The conductor 205 is extended to the die bonding area of the IC chip 111, and the IC chip 111 is bonded thereon by a die bonding material 208. The die bonding material 208 is conductive.

  With such a structure, the back surface of the IC chip 111 is electrically connected to the connection material 107 and the internal integrated circuit of the IC chip 101 via the die bonding material 208 and the conductor 205. Therefore, when the semiconductor device shown in FIG. 2 is connected to the mounting substrate, the back surface potential of the IC chip 111 can be fixed through the connection material 107, the conductor 205, and the die bonding material 208.

  According to the present embodiment, in addition to the effects of the first embodiment, the back surface potential of the IC chip incorporated in the semiconductor package can be fixed, and a stable function of the semiconductor device can be obtained.

  FIG. 3 is a structural cross-sectional view showing a third embodiment of the present invention. In this embodiment, conductors 305 and 315 are provided instead of the conductors 105 and 115 in the first embodiment, and an insulating material 309 is newly provided on the side surface of the IC chip 111. Conductors 305 and 315 are extended and connected through the surface of insulating material 309.

  By connecting the conductors 305 and 315, the IC chip 101 serving as a support substrate and the built-in IC chip 111 are electrically connected inside the package. In addition, when a plurality of IC chips are die-bonded on the IC chip 101, a plurality of ICs other than the supporting substrate are provided by providing conductors similar to the conductors 305 and 315 and arranging them appropriately. Chips can be electrically connected. In the present embodiment, the conductor 116 and the connection material 117 are not necessarily required.

  According to the present embodiment, in addition to the effects of the first embodiment, electrical connection between a plurality of IC chips built in the semiconductor package can be made inside the semiconductor package. This eliminates the need to form wiring on the connection substrate to which the semiconductor device is connected in consideration of electrical connection between the built-in IC chips. In addition, since the electrical connection between the plurality of IC chips incorporated in the semiconductor package can be performed using a shorter wiring, the speed of the semiconductor device can be increased.

  FIG. 4 is a structural cross-sectional view showing a fourth embodiment of the present invention. In this embodiment, a surface protective film 404 having a thickness larger than that of the surface protective film 104 is provided instead of the surface protective film 104. The surface protective film 404 has a hole having the same size as the IC chip 111 and an opening provided on the pad 102. The IC chip 111 is embedded in the hole and die bonded. After the conductor 405 is connected to the pad 102, the conductor 405 extends on the surface of the surface protective film 404 and is connected to the conductor 415. Here, a polymer resin such as polyimide is used as the material of the surface protective film 404.

  By connecting the conductors 405 and 415, the IC chip 101 serving as a support substrate and the built-in IC chip 111 are electrically connected inside the package. In addition, when a plurality of IC chips are die-bonded on the IC chip 101, the plurality of built-in IC chips are also electrically connected via a conductor formed on the surface of the IC chip serving as a support substrate. . Further, by providing a hole in the increased thickness of the surface protective film 404 and embedding the IC chip 111 therein, a step caused by the thickness of the IC chip 111 that is die-bonded to the IC chip 101 serving as a support substrate. Can be improved compared to at least the third embodiment.

  Such a structure is advantageous when selecting a manufacturing method in which an individualized IC chip is mounted on an IC in a wafer state before being individualized. This is because conductor formation and patterning can be performed simultaneously on the wafer and the surface of the IC chip 111, and a structure for electrically connecting the conductors 405 and 415 can be collectively formed. In addition, since the resin-sealed surface inside the semiconductor package is flattened, sealing with the resin 130 is facilitated. In the present embodiment, the conductor 116 and the connection material 117 are not necessarily required.

  According to the present embodiment, in addition to the effects of the third embodiment, the level difference caused by the thickness of the IC chip die-bonded to the IC chip to be the support substrate is improved, so that the support substrate is obtained. It is easy to form a structure for electrically connecting the conductor on the IC chip and the conductor on the other IC chip to be built therein. Also, resin sealing becomes easy.

  FIG. 5 is a structural cross-sectional view showing a fifth embodiment of the present invention. This embodiment differs greatly from the above-described embodiment in that another IC chip 511 is face-down bonded on the IC chip 101 serving as a support substrate and incorporated in the package. The IC chip 511 is a chip different from the IC chip 101 serving as a support substrate, and is smaller than the IC chip 101 and ground so as to be embedded in the same package.

  A pad 512 and a surface protective film 513 are formed on the IC chip 511. The pad 512 is electrically connected to the internal integrated circuit of the IC chip 511. The surface protective film 513 is for protecting the surface of the integrated circuit, covers the surface of the IC chip 512, and has an opening on the pad 512. Further, an electrode connecting material 518 is formed outside the surface protective film 513 connected to the pad 512. As the electrode connection material 518, for example, a conductive resin formed by a bump electrode or printing can be used. The conductor 505 connected to the pad 102 of the IC chip 101 is formed to be extended as compared with the conductor 105 of the first embodiment, and is electrically connected to the electrode connection material 518.

  By connecting the conductor 505 and the electrode connecting material 518, the IC chip 101 serving as the support substrate and the built-in IC chip 511 are electrically connected inside the package. Further, a plurality of built-in chips other than the IC chip 101 serving as the support substrate are also electrically connected via a conductor formed on the surface of the IC chip serving as the support substrate. Further, since the IC chip 511 is connected to the external terminal by the electrode connection material 518, the conductors 115 and 116, the connection material 117, and the like used in the above embodiment are not necessary. Further, since there are no conductors 115 and 116, only one surface protective film 513 is sufficient, and the surface protective film 114 is also unnecessary.

  According to the present embodiment, in addition to the effects of the first embodiment, electrical connection between a plurality of IC chips built in the semiconductor package can be made inside the semiconductor package. This eliminates the need to form wiring on the connection substrate to which the semiconductor device is connected in consideration of electrical connection between the built-in IC chips. Further, since the electrical connection between the plurality of IC chips incorporated in the semiconductor package can be performed with shorter wiring, the speed of the semiconductor device can be increased. Furthermore, as compared with the above-described embodiment, it is possible to simplify the processing for an IC chip other than the IC chip that is built in the semiconductor package and becomes the support substrate.

  FIG. 6 is a structural cross-sectional view showing a sixth embodiment of the present invention. Similarly to the fifth embodiment, in this embodiment, another IC chip 511 is face-down bonded on the IC chip 101 serving as a support substrate and incorporated in the package. However, in the present embodiment, a pad 602 and a conductor 605 are formed on the surface protective film 104 so as to be connected to the pad 602 on the IC chip 101. The pad 602 is electrically connected to the internal integrated circuit of the IC chip 101. The surface protective films 103 and 104 have openings on the pads 602. Here, the conductor 605 is formed between the IC chip 101 and the IC chip 511, and is electrically connected to the electrode connection material 518 of the IC chip 511. Unlike the conductor 105, the conductor 605 is not connected to the conductor 106 and the connection material 107 that can be connected to the external terminal. The pad 602 is disposed at a position suitable for connecting the conductor 605 and the electrode connecting material 518.

  By providing the pad 602 and the conductor 605 and connecting the conductor 605 and the electrode connecting material 518, the IC chip 101 serving as the support substrate and the built-in IC chip 511 are electrically connected inside the package. Further, when bonding a plurality of IC chips on the IC chip 101, the plurality of built-in IC chips can be electrically connected via the conductor 605.

  According to the present embodiment, in addition to the effects of the fifth embodiment, electrical connection of each internal integrated circuit between the IC chip serving as the support substrate and the IC chip incorporated in the other semiconductor package. Therefore, the degree of freedom of wiring is increased, and a higher-density internal wiring structure can be provided.

  FIG. 7 is a structural cross-sectional view showing a seventh embodiment of the present invention. In the present embodiment, as in the fifth and sixth embodiments, another IC chip 711 is face-down bonded on the IC chip 101 serving as a support substrate and incorporated in the package. However, in this embodiment, in addition to the structure of the fifth embodiment, a penetrating electrode 719 is newly provided inside the IC chip 711. The through electrode 719 penetrates the IC chip 711 and has a conductor 720 inside. The conductor 720 is insulated from the semiconductor substrate of the IC chip 711. Here, the through electrode 719 is illustrated as including a through hole and a conductor 720 provided on the side wall of the through hole, but may have a structure other than the above. For example, a columnar conductor that penetrates the IC chip 711 may be provided so as to be insulated from the semiconductor substrate of the IC chip 711.

  On the surface of the IC chip 711 facing the IC chip 101, a pad 712, a surface protective film 513, and an electrode connection material 518 are formed. The pad 712 is connected to the through electrode 719 and is electrically connected to the internal integrated circuit of the IC chip 101. The surface protective film 513 covers the surface of the IC chip 711 and has an opening on the pad 712. The electrode connecting material 518 is connected to the pad 712 and also to the conductor 505 on the IC chip 101.

  A back electrode 722 and two layers of surface protective films 713 and 714 are formed on the back surface of the IC chip 711. The back electrode 722 is electrically connected to the through electrode 719. The surface protective films 713 and 714 are for protecting the surface of the wiring formed on the back surface of the IC chip 711, and have openings on the back electrode 722. Further, the conductor 715 is connected to the back surface electrode 722, the columnar conductor 116 is connected to the conductor 715, and the connection material 117 is formed on the conductor 116.

  With the configuration as described above, one end of the through electrode 719 is connected to the IC chip 101 via the electrode connecting material 518 and the conductor 505, and the other end is connected to a conductor to the outside of the package. As a result, an electrical connection can be made directly from the IC chip 711 to the outside of the package through the through electrode 719.

  According to the present embodiment, in addition to the effects of the fifth embodiment, each IC can be electrically connected between the IC chip serving as the support substrate and the IC chip incorporated in the other semiconductor package. It is. In addition, an electrical connection can be made directly from the built-in IC chip other than the support substrate to the outside of the semiconductor package. As a result, a multi-pin semiconductor package can be provided, and the degree of freedom of wiring is increased.

  In the above, the example in which the connection materials 107 and 117 are provided has been described. However, since the surfaces of the conductors 106 and 116 are exposed on the surface of the resin 130, even when the connection materials 107 and 117 are omitted, electrical connection with the outside is possible. Connection is possible. The effect of the present invention can be obtained. When the connection materials 107 and 117 are omitted, there is an advantage that a lower cost semiconductor device can be provided.

  FIG. 11 is a structural cross-sectional view showing an eighth embodiment of the present invention. This is one example in which the present invention is applied to the conventional CSP shown in FIG. Another IC chip 811 is die-bonded on the IC chip 801 serving as a support substrate and incorporated in the package. The size of the package is the same as that of the IC chip 801 serving as the support substrate.

  An aluminum electrode pad 802 is formed on the IC chip 801. The aluminum electrode pad 802 is electrically connected to the internal integrated circuit of the IC chip 801. A copper post 805, which is a columnar conductor, is formed in connection with the aluminum electrode pad 802. Further, an IC chip 811 is fixed on the IC chip 801 via an adhesive sheet 808. The IC chip 811 is a chip different from the IC chip 801 serving as a support substrate, and is smaller than the IC chip 801 and ground so as to be embedded in the same package. Aluminum electrode pads 812 are formed on the IC chip 811. The aluminum electrode pad 812 is electrically connected to the internal integrated circuit of the IC chip 811. A gold bump 815 is formed in connection with the aluminum electrode pad 812.

  The resin 830 seals at least the integrated circuit formation surface of all IC chips. A plurality of rewiring patterns 806 whose surfaces are plated with gold, tin, or the like are formed at predetermined intervals on the resin 830, on the copper posts 805, and on the gold bristle nest bumps 815. On the rewiring pattern 806, solder balls 807 for external connection terminals are formed.

  A copper post 805 can electrically connect the aluminum electrode pad 802 to an external terminal of the package, and a solder ball 807 can connect the package to an external substrate. That is, the internal integrated circuit of the IC chip 801 and the external substrate of the package can be electrically connected by a series of connected aluminum electrode pads 802, copper posts 805, rewiring patterns 806, and solder balls 807.

  Similarly, the gold bumps 815 can be electrically connected from the aluminum electrode pads 812 to the external terminals of the package, and the solder balls 807 can be connected to the external substrate. That is, the internal integrated circuit of the IC chip 811 and the external substrate of the package can be electrically connected by a series of connected aluminum electrode pads 812, gold bumps 815, rewiring patterns 806, and solder balls 807. Further, the IC chip 801 and the IC chip 811 can be connected by the rewiring pattern 806 and the solder ball 807. As described above, according to the present embodiment, the same effects as those of the first embodiment can be obtained.

  An example of the manufacturing method according to the eighth embodiment will be described below with reference to FIG. First, the IC chip 801 is prepared with an aluminum electrode pad 802 formed, and the IC chip 811 is prepared with an aluminum electrode pad 812 and a gold bump 815 formed thereon. Here, the case of the wafer state before the IC chip 801 is separated into individual pieces will be described. In FIG. 15A, a wafer 881 is a wafer on which a semiconductor element to be an IC chip 801 is formed, and an aluminum electrode pad 802 is formed thereon.

  Next, as shown in FIG. 15B, a copper post 805 is formed on the aluminum electrode pad 802. The formation of the copper post 805 can be obtained by sequentially performing the steps of vapor deposition of a metal film on the entire surface of the wafer 881, application of a photosensitive resist, patterning, copper plating, removal of the photosensitive resist, and peeling of an excess metal film. Next, as shown in FIG. 15C, an IC chip 811 on which an aluminum electrode pad 812 and a gold bump 815 are formed is mounted on a wafer 881 using an adhesive sheet 808.

  Thereafter, as shown in FIG. 15D, everything on the wafer 881 is sealed with a resin 830 to protect it. In this state, both the copper post 805 and the gold bump 815 are buried inside the resin 830. Next, as shown in FIG. 15E, the upper surface of the resin 830 is cut off until the copper post 805 and the gold bump 815 are exposed.

  Next, as shown in FIG. 15F, a rewiring pattern 806 is formed on the resin 830, the copper post 805, and the gold bump 815. The rewiring pattern 806 is formed by depositing a metal film on the entire surface of the resin 830, applying a photosensitive resist, patterning, copper plating, removing the photosensitive resist, peeling off an excess metal film, and electroless tin (or gold) plating. It is obtained by sequentially performing the steps.

  Next, as shown in FIG. 15G, solder balls 807 are formed on the rewiring pattern 806. Finally, the wafer is diced and separated into individual pieces as shown in FIG. 15H to complete the CSP of the eighth embodiment.

  FIG. 12 is a structural sectional view showing a ninth embodiment of the present invention. This is also one example in which the present invention is applied to the conventional CSP shown in FIG. A significant difference from the eighth embodiment is that another IC chip 911 is face-down bonded on an IC chip 801 serving as a support substrate and incorporated in the package. The size of the package is the same as that of the IC chip 801 serving as the support substrate. The IC chip 911 is a chip different from the IC chip 801 serving as a support substrate, and is smaller than the IC chip 801 and ground so as to be embedded in the same package.

  In the present embodiment, compared to the eighth embodiment, in addition to the aluminum electrode pad 802, the aluminum electrode pad 902 is formed at a position facing the IC chip 911 on the IC chip 801. In place of the aluminum electrode pad 812, an aluminum electrode pad 912 is formed on the surface of the IC chip 911 facing the IC chip 801. A gold bump 915 is formed between the aluminum electrode pad 902 and the aluminum electrode pad 912 so as to be connected to both. As described above, the adhesive sheet 808 is not used for bonding the IC chip 911. Further, there is no conductor that directly connects the IC chip 911 and the rewiring pattern 806. Other configurations are the same as those of the eighth embodiment.

  The aluminum electrode pads 802 and 902 are electrically connected to the internal integrated circuit of the IC chip 801. The aluminum electrode pad 912 is electrically connected to the internal integrated circuit of the IC chip 911. Therefore, the internal integrated circuits of the IC chip 801 and the IC chip 911 are electrically connected inside the package. When it is desired to connect the IC chip 911 to the external substrate, it is possible to connect via the IC chip 801, the rewiring pattern 806, and the solder ball 807. In this embodiment mode, since the adhesive sheet 808 is not used, an inexpensive CSP can be provided. As described above, according to the present embodiment, the same effect as in the fifth embodiment can be obtained.

  Hereinafter, an example of the manufacturing method according to the ninth embodiment will be described with reference to FIG. First, the IC chip 801 is prepared with aluminum electrode pads 802 and 902 formed, and the IC chip 911 is prepared with an aluminum electrode pad 912 and gold bumps 915 formed thereon. Here, the case of the wafer state before the IC chip 801 is separated into individual pieces will be described. In FIG. 16A, a wafer 881 is a wafer on which semiconductor elements to be IC chips 801 are formed, and aluminum electrode pads 802 and 902 are formed thereon.

  Next, as shown in FIG. 16B, a copper post 805 is formed on the aluminum electrode pad 802. The formation of the copper post 805 is performed in the same manner as described with reference to FIG. Next, as shown in FIG. 16C, an IC chip 911 formed with aluminum electrode pads 912 and gold bumps 915 is mounted on a wafer 881 by face-down bonding. Thereafter, as shown in FIG. 16 (d), everything on the wafer 881 is sealed with a resin 830. Next, as shown in FIG. 16E, the upper surface of the resin 830 is scraped until the copper post 805 is exposed.

  Next, as shown in FIG. 16F, a rewiring pattern 806 is formed on the resin 830 and the copper post 805. The rewiring pattern 806 is formed in the same manner as described with reference to FIG. The subsequent steps shown in FIGS. 16 (g) and 16 (h) are the same as those described in FIGS. 15 (g) and 15 (h). As described above, the CSP of the ninth embodiment is completed.

  FIG. 13 is a structural cross-sectional view showing a tenth embodiment of the present invention. This is obtained by eliminating the solder ball 807 from the ninth embodiment. Other configurations are the same as those of the ninth embodiment. By omitting the solder ball 807, a further low-cost CSP can be provided.

  FIG. 14 is a structural sectional view showing an eleventh embodiment of the present invention. In this case, the number of IC chips incorporated by face-down bonding is two. Other configurations are the same as those of the ninth embodiment. The built-in IC chips 921 and 931 may be the same or different. Also, the number of built-in IC chips is not limited to two but may be three or more. By increasing the number of built-in IC chips, it is possible to provide a CSP with higher functionality.

  As mentioned above, although preferred embodiment concerning this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to this example. It is obvious for those skilled in the art that various changes or modifications can be conceived within the scope of the technical idea described in the claims. It is understood that it belongs to.

1 is a structural cross-sectional view showing a first embodiment of the present invention. It is structural sectional drawing which shows the 2nd Embodiment of this invention. It is structural sectional drawing which shows the 3rd Embodiment of this invention. It is structural sectional drawing which shows the 4th Embodiment of this invention. It is structural sectional drawing which shows the 5th Embodiment of this invention. It is structural sectional drawing which shows the 6th Embodiment of this invention. It is structural sectional drawing which shows the 7th Embodiment of this invention. It is the figure which mounted the semiconductor package which concerns on the 1st Embodiment of this invention on the mounting board | substrate. It is a figure explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is structural sectional drawing which shows the 8th Embodiment of this invention. It is structural sectional drawing which shows the 9th Embodiment of this invention. It is structural sectional drawing which shows the 10th Embodiment of this invention. It is structural sectional drawing which shows the 11th Embodiment of this invention. It is a figure explaining the manufacturing method of the semiconductor device which concerns on the 8th Embodiment of this invention. It is a figure explaining the manufacturing method of the semiconductor device which concerns on the 9th Embodiment of this invention. It is structural sectional drawing which shows the conventional semiconductor device.

Explanation of symbols

100 Semiconductor device 101, 111 IC chip 102, 112 Pad 103, 104, 113, 114 Surface protective film 105, 106, 115, 116 Conductor 107, 117 Connection material 108 Die bonding material 130 Resin

Claims (21)

A first IC chip having a main surface on which a first pad is formed; a first protective film covering the main surface of the first IC chip so as to expose a part of the first pad; ,
The first protective film has a first surface on which a second pad is formed and a second surface opposite to the first surface, and the second surface faces the first protective film. A second IC chip provided above;
A second protective film covering the first surface of the second IC chip so as to expose a part of the second pad;
A conductor provided on the second pad and the second protective film and electrically connected to the second pad;
A columnar conductor provided on the conductor and electrically connected to the conductor;
A semiconductor device comprising: the first and second protective films, a resin covering the conductor and a side surface of the second IC chip so as to expose one end of the columnar conductor ;
The semiconductor device according to claim 1, wherein a distance from an outer edge portion of the second IC chip to the second pad is shorter than a distance from the outer edge portion of the second IC chip to the columnar conductor. The semiconductor device according to claim 1, wherein a connection material is provided at one end of the columnar conductor exposed from the resin. A first IC chip having a main surface on which a first pad is formed; a first protective film covering the main surface of the first IC chip so as to expose a part of the first pad; ,
The first protective film has a first surface on which a second pad is formed and a second surface opposite to the first surface, and the second surface faces the first protective film. A second IC chip provided above;
A second protective film covering the first surface of the second IC chip so as to expose a part of the second pad;
A conductor provided on the second pad and the second protective film and electrically connected to the second pad;
A columnar conductor provided on the conductor and electrically connected to the conductor;
A resin covering the first and second protective films, the conductor, and a side surface of the second IC chip so as to expose one end of the columnar conductor;
A second conductor provided on the first pad and the first protective film and electrically connected to the first pad;
A semiconductor device comprising a second columnar conductor provided on the second conductor such that one end is exposed from the resin and electrically connected to the conductor;
Wherein a distance from an outer edge of the first IC chip to said first pad, semiconductors you being shorter than the distance from the outer edge of the first IC chip to said second columnar conductor apparatus. The semiconductor device according to claim 3 , wherein a second connection material is provided at one end of the second columnar conductor exposed from the resin. 2. The semiconductor device according to claim 1, wherein a cut surface cut by dicing is formed on a side surface of the first IC chip and a side surface of the resin. A first IC chip having a main surface with a pad formed thereon;
A protective film covering the main surface of the first IC chip so as to expose a part of the pad;
A conductor provided on the pad and the protective film and electrically connected to the pad;
A columnar conductor provided on the conductor and electrically connected to the conductor;
A second IC chip provided on the conductor;
A semiconductor device comprising a resin covering the protective film, the conductor, and the second IC chip so as to expose one end of the columnar conductor,
Wherein a distance from an outer edge to the pad of the first IC chip, the semi-conductor device you being shorter than the distance from the outer edge of the first IC chip to said columnar conductor. The semiconductor device according to claim 6 , wherein a connection material is provided at one end of the columnar conductor exposed from the resin. A first IC chip having a main surface with a pad formed thereon;
A protective film covering the main surface of the first IC chip so as to expose a part of the pad;
A conductor provided on the pad and the protective film and electrically connected to the pad;
A columnar conductor provided on the conductor and electrically connected to the conductor;
A second IC chip provided on the conductor;
A resin covering the protective film, the conductor, and the second IC chip so as to expose one end of the columnar conductor;
The second IC chip has a first surface on which a second pad is formed and a second surface facing the conductor;
A second protective film covering the first surface of the second IC chip so as to expose a part of the second pad;
A second conductor provided on the second pad and the second protective film and electrically connected to the second pad;
A semiconductor device comprising: a second columnar conductor provided on the second conductor such that one end is exposed from the resin; and electrically connected to the conductor;
Wherein a distance from an outer edge of the second IC chip to said second pads, semiconductors you being shorter than the distance from the outer edge of the second IC chip to the second columnar conductor apparatus. 9. The semiconductor device according to claim 8 , wherein a second connection material is provided at one end of the second columnar conductor exposed from the resin. 9. The semiconductor device according to claim 8 , wherein a cut surface cut by dicing is formed on a side surface of the first IC chip and a side surface of the resin. A first IC chip having a main surface on which a first pad is formed; a first protective film covering the main surface of the first IC chip so as to expose a part of the first pad; ,
The first protective film has a first surface on which a second pad is formed and a second surface opposite to the first surface, and the second surface faces the first protective film. A second IC chip provided on the second IC chip; a second protective film covering the first surface of the second IC chip so as to expose a part of the second pad;
A conductor provided on the first and second pads and the first and second protective films and electrically connected to the first and second pads;
A columnar conductor provided on the conductor and electrically connected to the conductor;
A semiconductor device comprising: a resin covering the first and second protective films, the conductor, and a side surface of the second IC chip so as to expose one end of the columnar conductor;
The columnar conductor is formed on the conductor formed on the main surface of the first IC chip,
Wherein a distance from an outer edge of the first IC chip to said first pad, semiconductors devices you being shorter than the distance from the outer edge of the first IC chip to said columnar conductor. The semiconductor device according to claim 11 , wherein a connection material is provided at one end of the columnar conductor exposed from the resin. A first IC chip having a main surface on which a first pad is formed; a first protective film covering the main surface of the first IC chip so as to expose a part of the first pad; ,
The first protective film has a first surface on which a second pad is formed and a second surface opposite to the first surface, and the second surface faces the first protective film. A second IC chip provided on the second IC chip; a second protective film covering the first surface of the second IC chip so as to expose a part of the second pad;
A conductor provided on the first and second pads and the first and second protective films and electrically connected to the first and second pads;
A columnar conductor provided on the conductor and electrically connected to the conductor;
A semiconductor device comprising: a resin covering the first and second protective films, the conductor, and a side surface of the second IC chip so as to expose one end of the columnar conductor;
The columnar conductor is formed on the conductor formed on the main surface of the second IC chip,
Wherein a distance from an outer edge of the second IC chip to said second pads, semi conductor device you being shorter than the distance from the outer edge of the second IC chip to the columnar conductor. The first IC chip is a logic system chip semiconductor device according to claim 11 or 13, characterized in that said second IC chip is a memory-based chip. The semiconductor device according to claim 11 or 13, wherein the first and second IC chips are both logic-based chips. The semiconductor device according to claim 11 or 13, wherein the first and second IC chips are both the memory-based chip. 14. The semiconductor device according to claim 11 , wherein a cut surface cut by dicing is formed on a side surface of the first IC chip and a side surface of the resin. A first IC chip having a main surface on which a first pad is formed;
A protective film covering the main surface of the first IC chip so as to expose a part of the first pad;
A first surface on which a second pad is formed, and a second surface opposite to the first surface, the second surface facing the main surface of the first IC chip. A second IC chip formed on the first pad and excluding a part of the second pad, wherein the first surface and the second surface are covered with the protective film;
A conductor provided on the first and second pads and the protective film and electrically connected to the first and second pads;
A columnar conductor provided on the conductor and electrically connected to the conductor;
A semiconductor device comprising a resin covering the protective film and the conductor so as to expose one end of the columnar conductor,
Wherein a distance from an outer edge of the first IC chip to said first pad, semiconductors devices you being shorter than the distance from the outer edge of the first IC chip to said columnar conductor. A first IC chip having a main surface on which a first pad is formed;
A protective film covering the main surface of the first IC chip so as to expose a part of the first pad;
A first surface on which a second pad is formed, and a second surface opposite to the first surface, the second surface facing the main surface of the first IC chip. A second IC chip formed on the first pad and excluding a part of the second pad, wherein the first surface and the second surface are covered with the protective film;
A conductor provided on the first and second pads and the protective film and electrically connected to the first and second pads;
A columnar conductor provided on the conductor and electrically connected to the conductor;
A semiconductor device comprising a resin covering the protective film and the conductor so as to expose one end of the columnar conductor,
The columnar conductor is provided on the conductor on the second IC chip, and the distance from the outer edge of the second IC chip to the second pad is determined from the outer edge of the second IC chip. semi conductor arrangement it is shorter than the distance to the columnar conductor. The semiconductor device according to claim 18 , wherein a connection material is provided at one end of the columnar conductor exposed from the resin. The semiconductor device according to claim 18 , wherein a cut surface cut by dicing is formed on a side surface of the first IC chip and a side surface of the resin.

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