JP3365879B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3365879B2 JP3365879B2 JP752395A JP752395A JP3365879B2 JP 3365879 B2 JP3365879 B2 JP 3365879B2 JP 752395 A JP752395 A JP 752395A JP 752395 A JP752395 A JP 752395A JP 3365879 B2 JP3365879 B2 JP 3365879B2
- Authority
- JP
- Japan
- Prior art keywords
- bumps
- bump
- leveling
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップの表面上
に複数のバンプを配設してなるフリップチップ方式の半
導体装置の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flip-chip type semiconductor device in which a plurality of bumps are provided on the surface of a semiconductor chip.
【０００２】[0002]
【従来の技術】フリップチップ方式の半導体装置の製造
においては、半導体チップの表面上に配設した複数のバ
ンプの高さを揃えるためのレベリング処理を必要とし、
この処理に高い精度が要求される。2. Description of the Related Art In manufacturing a flip-chip type semiconductor device, a leveling process is required to make the heights of a plurality of bumps arranged on the surface of a semiconductor chip uniform.
High precision is required for this processing.
【０００３】従来のレベリング処理工程の一例を示す図
５を参照すると、複数のバンプ１、１…を表面上に配設
してなる半導体チップ２が、平坦なレベリングステージ
３上に、表面を上向きにして載置されている。この状態
で加圧プレート４が下降し、加圧プレート４の平滑な下
面で複数のバンプ１、１…を押圧するので、複数のバン
ブ１、１…の主として頭部が変形し、それぞれの高さが
均一に揃えられる。Referring to FIG. 5 showing an example of a conventional leveling process, a semiconductor chip 2 having a plurality of bumps 1, 1, ... Arranged on the surface thereof is placed on a flat leveling stage 3 and the surface thereof faces upward. It has been placed. In this state, the pressure plate 4 descends and presses the plurality of bumps 1, 1, ... With the smooth lower surface of the pressure plate 4, so that the heads of the plurality of bumps 1, 1 ,. Are evenly arranged.
【０００４】[0004]
【発明が解決しようとする課題】このように、複数のバ
ンプ１、１…はレベリング処理中に変形するが、変形量
は全バンプ１、１…に一様でなく、個体差が生じる。し
たがって、レベリング処理の過不足や、短絡等の障害発
生の有無をこの段階で検査しておくことが必要となる。
しかし、目視に頼る方法では、的確にして効率のよい検
査を望むことができないという課題があった。As described above, although the plurality of bumps 1, 1, ... Deforms during the leveling process, the amount of deformation is not uniform among all the bumps 1, 1 ,. Therefore, it is necessary to inspect at this stage whether or not the leveling process is excessive or deficient and whether a fault such as a short circuit has occurred.
However, the method relying on visual inspection has a problem in that it is not possible to request an accurate and efficient inspection.
【０００５】また、半導体チップの大型化に伴い、必要
とするバンプ数が増えるので、レベリング処理に必要な
押圧荷重が大きくなる。そのために、高価な大型プレス
機を導入しなければならないという課題もあった。Further, as the size of the semiconductor chip increases, the number of bumps required increases, so that the pressing load required for the leveling process increases. Therefore, there is also a problem that an expensive large press machine must be introduced.
【０００６】したがって本発明の第１の目的は、レベリ
ング処理で変形したバンプの機械的および電気的特性を
的確かつ効率よく掌握できる半導体装置の製造方法を提
供することにある。また、本発明の第２の目的は、バン
プを高い精度で変形させ得るのみならず、多数のバンプ
を備えた半導体チップに対するレベリング処理をも容易
に達成できる半導体装置の製造方法を提供することにあ
る。Therefore, it is a first object of the present invention to provide a method of manufacturing a semiconductor device capable of accurately and efficiently grasping mechanical and electrical characteristics of a bump deformed by a leveling process. A second object of the present invention is to provide a method of manufacturing a semiconductor device, which can not only deform the bumps with high accuracy but also easily achieve the leveling process for a semiconductor chip having a large number of bumps. is there.
【０００７】[0007]
【課題を解決するための手段】本発明によると、上述の
目的を達成するために、複数のバンプを表面上に配設し
てなる半導体チップを、その裏面側から半導体保持具で
保持し、前記複数のバンプを全面的または部分的にレベ
リングステージに押し付けて、これらバンプの高さを均
一に揃えると同時に、レベリングステージのバンプ当接
予定位置に、導通テスト用の電極を設けておき、バンプ
の導通テストを行うことを特徴とする半導体装置の製造
方法が提供される。According to the present invention, in order to achieve the above-mentioned object, a semiconductor chip having a plurality of bumps arranged on the front surface is held by a semiconductor holder from the back surface side thereof. By pressing the plurality of bumps onto the leveling stage in whole or in part, the bumps of the leveling stage are brought into contact with the bumps of the leveling stage at the same time.
A method for manufacturing a semiconductor device is provided, in which electrodes for a continuity test are provided at predetermined positions to conduct a bump continuity test.
【０００８】[0008]
【０００９】また、導通テスト用の電極が１個のバンプ
に対し、１対の電気接点からなり、１対の電気接点の間
隔をバンプの頭部幅が変形しているか否かを検査するこ
とができるように設定した構成となすことができる。Further, the electrode for the continuity test is composed of a pair of electric contacts for one bump, and is provided between the pair of electric contacts.
Check whether the head width of the bump is deformed.
It can be configured so that it can be set .
【００１０】また、半導体保持具およびレベリングステ
ージの少なくとも一方を加熱することができる。Further, at least one of the semiconductor holder and the leveling stage can be heated.
【００１１】[0011]
【作用】本発明においては、複数のバンプをレベリング
ステージに押し付けてバンプの高さを均一に揃えるレベ
リング処理中に、これらバンプの導通テストを併せ行う
ので、的確な検査を効率よく達成することができるのみ
ならず、導通テストの結果をみながら、レベリング処理
の過不足を是正することが可能となる。In the present invention, since the bump continuity test is also performed during the leveling process in which a plurality of bumps are pressed against the leveling stage so that the bumps have a uniform height, an accurate inspection can be efficiently achieved. Not only can it be done, but it is possible to correct the excess or deficiency of the leveling process while checking the result of the continuity test.
【００１２】また、半導体保持具およびレベリングステ
ージの少なくとも一方を加熱することによっては、レベ
リング処理中のバンプを軟化させ得るので、レベリング
処理の精度を高めることができるのみならず、比較的小
さい押圧荷重でもって一度に多数のバンプをレベリング
処理することができる。By heating at least one of the semiconductor holder and the leveling stage, the bumps during the leveling process can be softened, so that not only the accuracy of the leveling process can be improved, but also a relatively small pressing load. Therefore, many bumps can be leveled at one time.
【００１３】[0013]
【実施例】つぎに、本発明の実施例を図面を参照しなが
ら説明する。Embodiments of the present invention will now be described with reference to the drawings.
【００１４】図１の（ａ）に示すように、複数のバンプ
１、１…を表面上に配列してなる半導体チップ２が、吸
着ノズルからなる半導体保持具５によって裏面側から吸
着保持される。各バンプ１、１…はＡｕ等からなり、球
面状の頭部を有している。そして、半導体保持具５の下
方に設けられたレベリングステージ６は、バンプ１、１
…の当接予定位置に複数の電極７、７…を有し、各電極
７、７…は検査機８に接続されている。As shown in FIG. 1A, a semiconductor chip 2 having a plurality of bumps 1, 1, ... Arranged on its surface is suction-held from the back side by a semiconductor holder 5 composed of a suction nozzle. . Each of the bumps 1, 1, ... Is made of Au or the like and has a spherical head. Then, the leveling stage 6 provided below the semiconductor holder 5 includes the bumps 1, 1
A plurality of electrodes 7, 7 ... Are provided at the expected contact positions of ... And each electrode 7, 7 ... Is connected to the inspection machine 8.
【００１５】半導体保持具５が図１の（ａ）に示すよう
に下降すると、バンプ１、１…がそれぞれに対する電極
７、７…に押し当てられ、レベリング処理される。それ
と同時に、半導体チップ２の内部回路が電極７、７…を
介して検査機８と電通し、検査機８は、その負荷側のオ
ープン・ショート状態および動作状態を検査し、検査結
果を表示器上に表示する。そのため、レベリング処理の
過不足やバンプの欠損等をレベリング処理中に瞬時に掌
握することが可能となる。When the semiconductor holder 5 is lowered as shown in FIG. 1 (a), the bumps 1, 1 ... Are pressed against the electrodes 7, 7 ... for each of them, and the leveling process is performed. At the same time, the internal circuit of the semiconductor chip 2 is electrically connected to the inspection machine 8 via the electrodes 7, 7 ..., The inspection machine 8 inspects the open / short state and the operating state of the load side, and displays the inspection result on the display unit. Display on top. Therefore, it becomes possible to instantly grasp the excess or deficiency of the leveling process, the loss of bumps, and the like during the leveling process.
【００１６】上述した実施例では、導通テスト用の電極
７、７…をレベリングステージ６の頂面に設けたが、半
導体保持具５の下面に設けてもよい。この場合、半導体
チップ２はその表面を上向きにして、レベリングステー
ジ６上に載置される。In the above-mentioned embodiment, the electrodes 7, 7 ... For the continuity test are provided on the top surface of the leveling stage 6, but they may be provided on the lower surface of the semiconductor holder 5. In this case, the semiconductor chip 2 is mounted on the leveling stage 6 with its surface facing upward.
【００１７】複数の導通テスト用電極７、７…をそれぞ
れ２分割することができる。図２の（ａ）、（ｂ）に示
す実施例では、バンプ当接予定位置のそれぞれに、つま
り、１個のバンプに対して、相隣接する２個の電気接点
７ａ、７ｂを導通テスト用電極として設けている。この
場合、１対の電気接点７ａ、７ｂ間で導通テストができ
るので、所定のバンプが存在するか否かをより確実に検
査することができる。Each of the plurality of continuity test electrodes 7, 7 ... Can be divided into two. In the embodiment shown in FIGS. 2 (a) and 2 (b), two electrical contacts 7a and 7b adjacent to each other for each bump contacting position, that is, one bump, are used for the continuity test. It is provided as an electrode. In this case, since the continuity test can be performed between the pair of electrical contacts 7a and 7b, it is possible to more surely inspect whether or not a predetermined bump is present.
【００１８】また、１対の電気接点７ａ、７ｂの間隔を
例えば４０μｍに設定しておくと、バンプの頭部幅が４
０μｍ以上に変形しているか否かを検査することができ
る。When the distance between the pair of electrical contacts 7a and 7b is set to 40 μm, for example, the head width of the bump is 4
It can be inspected whether it is deformed to 0 μm or more.
【００１９】図３に示す実施例では、半導体保持具５に
加熱ヒータ９を設けている。また、図４に示す実施例で
は、レベリングステージ６に加熱ヒータ９を設けてい
る。このように構成すると、レベリング処理中のバンプ
１、１…を加熱して軟化させることができるので、バン
プ１、１…を高い精度で変形させることができるのみな
らず、レベリング処理に必要押圧荷重を低減させること
ができる。In the embodiment shown in FIG. 3, the semiconductor holder 5 is provided with a heater 9. Further, in the embodiment shown in FIG. 4, the heater 9 is provided on the leveling stage 6. With such a configuration, the bumps 1, 1, ... During the leveling process can be heated and softened, so that the bumps 1, 1, ... Can be deformed with high accuracy, and the pressing load required for the leveling process can be achieved. Can be reduced.
【００２０】バンプ１、１…の加熱温度を１５０℃に設
定すると、常温時に比べて約１／３の押圧荷重で足り、
３００℃に設定すると、常温時に比べて約１／２の押圧
荷重で足りる。このため、プレス機の出力を減らし得る
のみならず、半導体チップ２にクラックを生じさせる危
険を減らすことができる。When the heating temperature of the bumps 1, 1, ... Is set to 150 ° C., a pressing load of about 1/3 is sufficient as compared with the normal temperature.
When the temperature is set to 300 ° C, a pressing load of about 1/2 is sufficient as compared with the case of normal temperature. Therefore, not only the output of the press machine can be reduced, but also the risk of cracking the semiconductor chip 2 can be reduced.
【００２１】[0021]
【発明の効果】以上のように本発明によると、レベリン
グ処理中にバンプの導通テストを併せ行うので、的確な
検査を効率よく達成することができる。また、導通テス
トの結果をみながらレベリング処理の過不足を是正する
ことができる。また、半導体保持具およびレベリングス
テージの少なくとも一方を加熱することによっては、レ
ベリング処理中のバンプを軟化させ得るので、レベリン
グ処理の精度を高め得るのみならず、比較的小さい押圧
荷重でもって一度に多数のバンプをレベリング処理する
ことができる。As described above, according to the present invention, since the bump continuity test is also performed during the leveling process, an accurate inspection can be efficiently achieved. Further, it is possible to correct the excess or deficiency of the leveling process while observing the result of the continuity test. Further, by heating at least one of the semiconductor holder and the leveling stage, the bumps during the leveling process can be softened, so that not only can the accuracy of the leveling process be improved, but also a relatively small pressing load can be applied to a large number at a time. The bumps can be leveled.
【図１】本発明の一実施例におけるレベリング処理の工
程を示す図。FIG. 1 is a diagram showing steps of a leveling process according to an embodiment of the present invention.
【図２】本発明の他の実施例におけるレベリング処理の
工程を示す図。FIG. 2 is a diagram showing a step of leveling processing in another embodiment of the present invention.
【図３】本発明の他の実施例におけるレベリング処理装
置の側面図。FIG. 3 is a side view of a leveling processing device according to another embodiment of the present invention.
【図４】本発明の他の実施例におけるレベリング処理装
置の側面図。FIG. 4 is a side view of a leveling processing device according to another embodiment of the present invention.
【図５】従来のレベリング処理装置の側面図。FIG. 5 is a side view of a conventional leveling processing device.
１ バンプ ２ 半導体チップ ５ 半導体保持具 ６ レベリングステージ ７ 電極 ７ａ、７ｂ 電気接点 ８ 検査器 ９ 加熱ヒータ 1 bump 2 semiconductor chips 5 Semiconductor holder 6 Leveling stage 7 electrodes 7a, 7b electrical contacts 8 inspection equipment 9 heater
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平４−180232（ＪＰ，Ａ) 特開 平４−116832（ＪＰ，Ａ) 特開 平３−246946（ＪＰ，Ａ) 特開 平６−84921（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-180232 (JP, A) JP-A-4-116832 (JP, A) JP-A-3-246946 (JP, A) JP-A-6- 84921 (JP, A) (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 21/60
Claims (3)
導体チップを、その裏面側から半導体保持具で保持し、
前記複数のバンプを全面的または部分的にレベリングス
テージに押し付けて、これらバンプの高さを均一に揃え
ると同時に、レベリングステージのバンプ当接予定位置
に、導通テスト用の電極を設けておき、バンプの導通テ
ストを行うことを特徴とする半導体装置の製造方法。1. A semiconductor chip formed by arranging a plurality of bumps on its front surface is held by a semiconductor holder from its back surface side.
By pressing the plurality of bumps onto the leveling stage in whole or in part, the heights of these bumps are evenly aligned, and at the same time, the bump contact positions of the leveling stage.
A method for manufacturing a semiconductor device, comprising: providing an electrode for a continuity test in advance, and conducting a continuity test of the bump.
し、１対の電気接点からなり、１対の電気接点の間隔を
バンプの頭部幅が変形しているか否かを検査することが
できるように設定したことを特徴とする請求項１記載の
半導体装置の製造方法。 2. An electrode for a continuity test is composed of a pair of electrical contacts for one bump, and the distance between the pair of electrical contacts is set.
It is possible to inspect whether the head width of the bump is deformed
The method for manufacturing a semiconductor device according to claim 1 , wherein the method is set so that the semiconductor device can be set .
の少なくとも一方を加熱することを特徴とする請求項１
または２記載の半導体装置の製造方法。 3. A process according to claim 1, wherein the heating at least one of the semiconductor holder and the leveling stage
Alternatively, the method of manufacturing a semiconductor device according to the item 2 .
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP752395A JP3365879B2 (en) | 1995-01-20 | 1995-01-20 | Method for manufacturing semiconductor device |
| US08/576,160 US5686353A (en) | 1994-12-26 | 1995-12-21 | Semiconductor device and manufacturing method thereof |
| EP95120500A EP0720226B1 (en) | 1994-12-26 | 1995-12-22 | Semiconductor device comprising contact bumps |
| DE69535551T DE69535551T2 (en) | 1994-12-26 | 1995-12-22 | Semiconductor arrangement with contact holes |
| TW084113772A TW288194B (en) | 1994-12-26 | 1995-12-22 | |
| CN95113148A CN1051641C (en) | 1994-12-26 | 1995-12-25 | Semiconductor and its producing method |
| KR1019950056321A KR100239286B1 (en) | 1994-12-26 | 1995-12-26 | Semiconductor device and manufacturing method thereof |
| CNB991084586A CN1153267C (en) | 1994-12-26 | 1999-06-11 | Semiconductor device and process for producing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP752395A JP3365879B2 (en) | 1995-01-20 | 1995-01-20 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08203902A JPH08203902A (en) | 1996-08-09 |
| JP3365879B2 true JP3365879B2 (en) | 2003-01-14 |
Family
ID=11668141
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP752395A Expired - Fee Related JP3365879B2 (en) | 1994-12-26 | 1995-01-20 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3365879B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006075361A1 (en) * | 2005-01-12 | 2006-07-20 | Renesas Technology Corp. | Method for manufacturing semiconductor integrated circuit device |
| JP5479979B2 (en) * | 2010-03-31 | 2014-04-23 | 日本特殊陶業株式会社 | Manufacturing method of wiring board having solder bump |
-
1995
- 1995-01-20 JP JP752395A patent/JP3365879B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08203902A (en) | 1996-08-09 |
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