JPH0677273A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0677273A JPH0677273A JP5148734A JP14873493A JPH0677273A JP H0677273 A JPH0677273 A JP H0677273A JP 5148734 A JP5148734 A JP 5148734A JP 14873493 A JP14873493 A JP 14873493A JP H0677273 A JPH0677273 A JP H0677273A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- signal
- semiconductor chip
- integrated circuit
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
- H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
- H01L2224/06156—Covering only the central area of the surface to be connected, i.e. central arrangements
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01059—Praseodymium [Pr]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路装置に係
り、特にＬＯＣ（Lead on Chip) 型半導体集積回路装置
における配線接続構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a wiring connection structure in a LOC (Lead on Chip) type semiconductor integrated circuit device.
【０００２】[0002]
【従来の技術】リードフレームのリードを半導体チップ
上に延在させてリード先端部とボンディングパッドとを
ボンディングワイヤーで接続するＬＯＣ型半導体集積回
路装置は、半導体チップの面積を大きくすることがで
き、またボンディングパッドを半導体チップの周辺部の
みならずその中央部にも設置することができるので、近
年広く用いられている。2. Description of the Related Art A LOC type semiconductor integrated circuit device in which leads of a lead frame are extended on a semiconductor chip and a tip of the lead and a bonding pad are connected by a bonding wire can increase the area of the semiconductor chip. In addition, since the bonding pad can be installed not only in the peripheral portion of the semiconductor chip but also in the central portion thereof, it has been widely used in recent years.
【０００３】図５に従来技術のＬＯＣ型半導体集積回路
装置の一例を示す。電源系電位供給用のボンディングパ
ッド（以下、電源パッド、と略す）１３とクロック信
号、アドレス信号、データ入出力信号等の信号を供受す
るボンディングパッド（以下、信号パッド、と略す）１
２とが半導体チップ１１の中央部においてその長辺方向
に配列されている。なお各図において、電源パッドは黒
四角で示し、信号パッドは白四角で示してある。そして
電源系電位供給用リード（以下、電源リード、と略す）
１５および各信号を供受するリード（以下、信号リー
ド、と略す）１４が半導体チップ１１上に入り込みその
先端部とそれぞれの電源パッド１３，信号パッド１２と
をボンディングワイヤー１７で接続している。しかしな
がら、このような半導体集積回路装置では、複数の電源
パッド１３のそれぞれに対応して電源リード１５を必要
とするから、リードフレームの電源リード数が多くなっ
てしまう。FIG. 5 shows an example of a conventional LOC type semiconductor integrated circuit device. A bonding pad (hereinafter, abbreviated as a power supply pad) 13 for supplying a power supply system potential and a bonding pad (hereinafter, abbreviated as a signal pad) 1 for supplying and receiving signals such as a clock signal, an address signal, a data input / output signal
2 and 2 are arranged in the long side direction in the central portion of the semiconductor chip 11. In each figure, the power supply pad is shown by a black square and the signal pad is shown by a white square. And a lead for supplying a power system potential (hereinafter, abbreviated as a power lead)
15 and a lead (hereinafter, abbreviated as signal lead) 14 for supplying and receiving each signal enter the semiconductor chip 11 and connect the tip end thereof to each power supply pad 13 and signal pad 12 by a bonding wire 17. However, in such a semiconductor integrated circuit device, since the power supply lead 15 is required corresponding to each of the plurality of power supply pads 13, the number of power supply leads of the lead frame increases.
【０００４】このために半導体チップ１１にＰＲ技術で
電源配線層を形成し、この配線層を引き廻して供給する
電源電位が同じ複数の電源パッド１３を接続する方法を
用いると、電源リード１５の数は少なくてすむ。しかし
ながらこの方法では、電源配線層が長くなることに起因
して配線層抵抗が増大し特性に悪影響を及ぼす。Therefore, when a method of forming a power supply wiring layer on the semiconductor chip 11 by the PR technique and connecting a plurality of power supply pads 13 having the same power supply potential around the wiring layer is used, The number is small. However, in this method, the wiring layer resistance increases due to the lengthening of the power supply wiring layer, which adversely affects the characteristics.
【０００５】上記不都合を解消する技術として、米国特
許第４，９１６，５１９号に図６に示すようなＬＯＣ型
半導体集積回路装置が提示されている。同図において、
一対の電源リード２５ａと２５ｂ間を接続導体部２６ａ
で連続的に接続して第１の電源電位供給用、例えばＶｃ
ｃ電位供給用の電源リード構造を構成し、他の一対の電
源リード２５ｃと２５ｄ間を接続導体部２６ｂで連続的
に接続して第２の電源電位供給用、例えば接地（ＧＮ
Ｄ）電位供給用の電源リード構造を構成している。Ｖｃ
ｃ用の電源パッド１３はボンディングワイヤー１７によ
り接続導体部２６ａに接続され、接地用の電源パッド１
３はボンディングワイヤー１７により接続導体部２６ｂ
に接続されている。そして信号パッド１２はそれぞれの
信号リード１４とボンディングワイヤー２７により接続
されるが、信号パッド１２と信号リード１４との間には
電源電位の接続導体部２６ａ，２６ｂが配設されている
から、ボンディングワイヤー２７は接続導体部２６ａ，
２６ｂを立体交叉、すなわち接続導体部２６ａ，２６ｂ
上を横断することになる。しかしながら上記構造では、
ボンディング時あるいは樹脂封止の際の流動樹脂流入時
に、接続導体部を跨いているボンディングワイヤー２７
に弛みが生じ、信号系であるボンディングワイヤー２７
が電源電位系の接続導体部と短絡する事故が発生する可
能性がある。As a technique for solving the above inconvenience, US Pat. No. 4,916,519 discloses a LOC type semiconductor integrated circuit device as shown in FIG. In the figure,
A connecting conductor portion 26a is provided between the pair of power supply leads 25a and 25b.
For continuous supply of the first power supply potential, for example, Vc
A power supply lead structure for supplying a c-potential is formed, and another pair of power supply leads 25c and 25d are continuously connected by a connecting conductor portion 26b to supply a second power supply potential, for example, ground (GN).
D) A power supply lead structure for supplying a potential is constructed. Vc
The power supply pad 13 for c is connected to the connection conductor portion 26a by the bonding wire 17, and the power supply pad 1 for grounding is provided.
3 is a bonding wire 17 for connecting conductor portion 26b
It is connected to the. The signal pads 12 are connected to the respective signal leads 14 by the bonding wires 27. Since the connection conductor portions 26a and 26b for the power source potential are arranged between the signal pads 12 and the signal leads 14, the bonding is performed. The wire 27 is a connecting conductor portion 26a,
26b is three-dimensionally crossed, that is, connecting conductor portions 26a and 26b
You will cross over. However, in the above structure,
A bonding wire 27 straddling the connecting conductor portion at the time of bonding or flowing of a fluid resin at the time of resin sealing.
The slack occurs in the bonding wire 27 which is a signal system.
There is a possibility that a short circuit may occur with the connection conductor of the power supply potential system.
【０００６】[0006]
【発明が解決しようとする課題】以上説明したように従
来技術のＬＯＣ型半導体集積回路装置では、電源リード
の数を多く必要としたり、電源電位系の配線抵抗が増大
したり、信号系の短絡事故が発生したりする問題点があ
った。As described above, in the conventional LOC type semiconductor integrated circuit device, a large number of power supply leads are required, the wiring resistance of the power supply potential system is increased, and the signal system is short-circuited. There was a problem that an accident occurred.
【０００７】したがって本発明の目的は、電源リードの
数を最少限にし、電源電位系の抵抗を減少させ、かつ短
絡事故を回避したＬＯＣ型半導体集積回路装置を提供す
ることである。Therefore, an object of the present invention is to provide a LOC type semiconductor integrated circuit device in which the number of power supply leads is minimized, the resistance of the power supply potential system is reduced, and a short circuit accident is avoided.
【０００８】[0008]
【課題を解決するための手段】本発明の特徴は、半導体
チップ、前記半導体チップに形成された複数の電源パッ
ドおよび複数の信号パッド、前記半導体チップの外側よ
り前記半導体チップ上に延在して形成された複数の電源
リードおよび複数の信号リード、一対の前記電源リード
間を接続して前記半導体チップ上を延在する接続導体
部、前記電源パッドと前記接続導体部とを接続する第１
のボンディングワイヤー、および前記信号パッドと前記
信号リードのボンディング領域とを接続する第２のボン
ディングワイヤーを有する半導体集積回路装置におい
て、それぞれの前記信号パッドとそれに接続する前記信
号リードのボンディング領域とはその間に前記接続導体
部を介在させることなく対向配置され、これにより前記
第２のボンディングワイヤーが前記接続導体部上を横断
していない半導体集積回路装置にある。A feature of the present invention is that a semiconductor chip, a plurality of power supply pads and a plurality of signal pads formed on the semiconductor chip, and an extension from the outside of the semiconductor chip onto the semiconductor chip. A plurality of formed power supply leads and a plurality of signal leads, a connection conductor portion that extends between the pair of power supply leads and extends on the semiconductor chip, and a first connection between the power supply pad and the connection conductor portion.
In the semiconductor integrated circuit device having the above-mentioned bonding wire and the second bonding wire connecting the signal pad and the bonding area of the signal lead, the signal pad and the bonding area of the signal lead connected thereto are between In the semiconductor integrated circuit device, the second bonding wires are arranged so as to face each other without interposing the connection conductor portion therebetween, and thus the second bonding wire does not cross over the connection conductor portion.
【０００９】本発明の他の発明は、第１の方向をたがい
に平行に伸びる第１および第２の端辺と前記第１の方向
とは直角方向の第２の方向をたがいに平行に伸びる第３
および第４の端辺とを有する半導体チップと、前記半導
体チップの外側から前記半導体チップ上に延在する第１
の電源電位供給用の第１および第２の電源リードと、前
記半導体チップの外側から前記半導体チップ上に延在す
る第２の電源電位供給用の第３および第４の電源リード
と、前記第１および第２の電源リードと連続的に形成さ
れて前記半導体チップ上を前記第１の方向に延在する箇
所を有する第１の接続導体部と、前記第３および第４の
電源リードと連続的に形成されて前記第１の接続導体部
と所定の間隔を有して前記半導体チップ上を前記第１の
方向に延在する箇所を有する第２の接続導体部と、前記
第１の端辺上を通過して前記第１の接続導体部と前記第
１の端辺間の前記半導体チップ上を延在する複数の第１
の信号リードと、前記第２の端辺上を通過して前記第２
の接続導体部と前記第２の端辺間の前記半導体チップ上
を延在する複数の第２の信号リードと、前記半導体チッ
プに形成された第１の電源パッドと、前記半導体チップ
に形成された第２の電源パッドと、前記第１の接続導体
部下と前記第１の端辺との間の前記半導体チップの部分
に形成された複数の第１の信号パッドと、前記第２の接
続導体部下と前記第２の端辺との間の前記半導体チップ
の部分に形成された複数の第２の信号パッドと、前記第
１の電源パッドと前記第１の接続導体部間および前記第
２の電源パッドと前記第２の接続導体間をそれぞれ接続
する複数の第１のボンディングワイヤーと、複数の前記
第１および第２の信号パッドと複数の前記第１および第
２の信号リード間をそれぞれ接続する複数の第２のボン
ディングワイヤーとを有する半導体集積回路装置にあ
る。In another aspect of the present invention, the first and second end sides extending in parallel to each other in the first direction and the second direction perpendicular to the first direction extend in parallel to each other in the second direction. Third
And a semiconductor chip having a fourth edge, and a first chip extending from the outside of the semiconductor chip onto the semiconductor chip.
First and second power supply leads for supplying a power supply potential, third and fourth power supply leads for supplying a second power supply potential extending from outside the semiconductor chip onto the semiconductor chip, and A first connecting conductor portion which is formed continuously with the first and second power supply leads and has a portion extending on the semiconductor chip in the first direction, and continuous with the third and fourth power supply leads. Connection conductor portion that is formed integrally and has a predetermined distance from the first connection conductor portion and extends on the semiconductor chip in the first direction; and the first end. A plurality of first conductors passing over the sides and extending on the semiconductor chip between the first connection conductor portion and the first end sides.
Of the signal lead and the second end passing over the second edge.
A plurality of second signal leads extending on the semiconductor chip between the connection conductor portion and the second end side, a first power supply pad formed on the semiconductor chip, and a second power supply pad formed on the semiconductor chip. A second power supply pad, a plurality of first signal pads formed in the portion of the semiconductor chip between the first connection conductor portion and the first end side, and the second connection conductor A plurality of second signal pads formed in the portion of the semiconductor chip between the subordinates and the second end side, between the first power supply pad and the first connection conductor portion, and the second A plurality of first bonding wires that respectively connect the power supply pad and the second connection conductor, and a plurality of first and second signal pads and a plurality of the first and second signal leads, respectively. A plurality of second bonding wires In the semiconductor integrated circuit device having a.
【００１０】ここで、複数の前記第１の信号パッドは前
記第１の接続導体部下と前記第１の端辺との間の前記半
導体チップの部分を前記第１の方向に配列して形成さ
れ、複数の前記第２の信号パッドは前記第２の接続導体
部下と前記第２の端辺との間の前記半導体チップの部分
を前記第１の方向に配列して形成されることができる。
この場合、複数の前記第１の信号パッドは前記半導体チ
ップの前記第１の端辺の近傍部分を前記第１の方向に配
列して形成され、複数の前記第２の信号パッドは前記半
導体チップの前記第２の端辺の近傍部分を前記第１の方
向に配列して形成され、前記第１の信号リードに接続さ
れた前記第２のボンディングワイヤーは前記第１の端辺
方向に延びて前記第１の端辺の近傍部分に配列されたそ
れぞれの前記第１の信号パッドと接続され、前記第２の
信号リードに接続された前記第２のボンディングワイヤ
ーは前記第２の端辺方向に延びて前記第２の端辺の近傍
部分に配列されたそれぞれの前記第２の信号パッドと接
続されることができる。Here, the plurality of first signal pads are formed by arranging portions of the semiconductor chip between the first connection conductor portion and the first end side in the first direction. The plurality of second signal pads may be formed by arranging portions of the semiconductor chip between the second connection conductor portion and the second end side in the first direction.
In this case, the plurality of first signal pads are formed by arranging the vicinity of the first end side of the semiconductor chip in the first direction, and the plurality of second signal pads are formed in the semiconductor chip. The second bonding wire connected to the first signal lead extends in the direction of the first edge and is formed by arranging a portion near the second edge in the first direction. The second bonding wire connected to each of the first signal pads arranged in the vicinity of the first edge and connected to the second signal lead extends in the second edge direction. The second signal pads may extend and be connected to the respective second signal pads arranged in the vicinity of the second end side.
【００１１】さらに、前記第１の導電体部下と前記第１
の端辺との間の領域の外側の前記半導体チップの領域で
あってかつ前記第１の端辺の近傍を、第３の信号パッド
が複数の前記第１の信号パッドとともに前記第１の方向
に配列して形成され、前記第２の導電体部下と前記第２
の端辺との間の領域の外側の前記半導体チップの領域で
あってかつ前記第２の端辺の近傍を、第４の信号パッド
が複数の前記第２の信号パッドとともに前記第１の方向
に配列して形成され、第３の信号リードに接続された第
２のボンディングワイヤーが前記第１の端辺方向に延び
て前記第１の端辺の近傍部分に配列されたそれぞれの前
記第３の信号パッドと接続されており、第４の信号リー
ドに接続された前記第２のボンディングワイヤーが前記
第２の端辺方向に延びて前記第２の端辺の近傍部分に配
列されたそれぞれの前記第４の信号パッドと接続される
ことができる。Further, under the first conductor portion and the first conductor portion.
A third signal pad together with a plurality of the first signal pads in the first direction in a region of the semiconductor chip outside a region between the first signal line and the first signal line. Are formed in an array, and are formed under the second conductor part and the second conductor part.
A fourth signal pad together with the plurality of second signal pads in the first direction in the region of the semiconductor chip outside the region between the second signal pad and Second bonding wires connected to the third signal lead and extending in the first end side direction and arranged in the vicinity of the first end side. Each of the second bonding wires connected to the fourth signal lead and connected to the fourth signal lead extend in the second end side direction and are arranged in the vicinity of the second end side. It can be connected to the fourth signal pad.
【００１２】前記各ボンディングワイヤーは前記各信号
リードの先端箇所にボンディングされることができる。
前記各ボンディングワイヤーは信号リードの先端箇所か
ら離間した箇所にボンディングされることができる。こ
の場合、前記先端箇所は凹凸平面形状となっていること
が好ましい。Each of the bonding wires may be bonded to a tip portion of each of the signal leads.
Each of the bonding wires may be bonded to a location separated from the tip of the signal lead. In this case, it is preferable that the tip portion has an uneven planar shape.
【００１３】あるいは、複数の前記第１の信号パッドは
前記第１の接続導体部下と前記第１の端辺との間の前記
半導体チップの部分を前記第２の方向に配列して形成さ
れ、複数の前記第２の信号パッドは前記第２の接続導体
部下と前記第２の端辺との間の前記半導体チップの部分
を前記第２の方向に配列して形成されることができる。
この場合、前記第１の信号リードは前記第２の方向に延
びて前記第１の端辺上を通過して前記半導体チップ上を
延在した後に前記第１の方向に向って曲りその先端部を
前記第１の信号パッドと対向させ、前記第２の信号リー
ドは前記第２の方向に延びて前記第２の端辺上を通過し
て前記半導体チップ上を延在した後に前記第１の方向に
向って曲りその先端部を前記第２の信号パッドと対向さ
せることが好ましい。Alternatively, the plurality of first signal pads are formed by arranging portions of the semiconductor chip between under the first connection conductor portion and the first end side in the second direction. The plurality of second signal pads may be formed by arranging portions of the semiconductor chip between the second connection conductor portion and the second end side in the second direction.
In this case, the first signal lead extends in the second direction, passes over the first end side, extends over the semiconductor chip, and then bends in the first direction, and the tip portion thereof is bent. Are opposed to the first signal pad, the second signal lead extends in the second direction, passes over the second end side, extends over the semiconductor chip, and then extends over the first chip. It is preferable to bend in a direction and to make the tip end face the second signal pad.
【００１４】前記信号パッドならびに前記信号リード
は、それぞれクロック信号用、データ入出力用、アドレ
ス入力用、ライト・イネーブル用、ロウ・アドレス・ス
トローブ用、アウトプット・イネーブル用あるいはカラ
ム・アドレス・ストローブ用等のリードならびにボンデ
ィングパッドとすることができる。The signal pad and the signal read are for clock signal, data input / output, address input, write enable, row address strobe, output enable, or column address strobe, respectively. And the like as well as bonding pads.
【００１５】半導体集積回路装置に前記第１および第２
の電源パッドをそれぞれ複数個形成することが好まし
い。この場合、前記複数の第１の電源パッドのうちの一
部のパッドは前記第１の接続導体部下と前記第１の端辺
との間の前記半導体チップの領域に形成され残りのパッ
ドは前記第１および第２の接続導体部間下の前記半導体
チップの領域に形成されており、前記複数の第２の電源
パッドのうちの一部パッドは前記第２の接続導体部下と
前記第２の端辺との間の前記半導体チップの領域に形成
され残りのパッドは前記第１および第２の接続導体部間
下の前記半導体チップの領域に形成されることができ
る。あるいは、前記複数の第１および第２の電源パッド
の全てを前記第１および第２の接続導体部間下の前記半
導体チップの領域に形成することができる。The first and second semiconductor integrated circuit devices are provided.
It is preferable to form a plurality of power supply pads. In this case, some pads of the plurality of first power supply pads are formed in the region of the semiconductor chip between the first connection conductor portion and the first end side, and the remaining pads are A part of the plurality of second power supply pads is formed in the region of the semiconductor chip below the first and second connection conductor portions, and some pads of the second power supply pads are under the second connection conductor portion and the second connection conductor portion. The rest of the pads formed in the region of the semiconductor chip between the edge and the edge may be formed in the region of the semiconductor chip below the first and second connection conductor portions. Alternatively, all of the plurality of first and second power supply pads can be formed in the region of the semiconductor chip under the first and second connection conductor portions.
【００１６】また、前記第１および第２の電源リードを
前記第１の端辺上を通過して前記半導体チップ上に延在
し、前記第３および第４の電源リードを前記第２の端辺
上を通過して前記半導体チップ上に延在させることがで
きる。あるいは、前記第１および第３の電源リードを前
記第３の端辺上を前記第２の方向に延在して前記半導体
チップ内上に入り込ませ、前記第２および第４の電源リ
ードを前記第４の端辺上を前記第２の方向に延在してか
ら前記半導体チップ内上に入り込ませることができる。
または、前記第１および第３の電源リードを前記第３の
端辺上を前記第２の方向に延在して前記半導体チップ内
上に入り込ませ、前記第２の電源リードをその全て幅に
わたって前記第１の端辺上を横断して前記半導体チップ
内上に入り込ませ、前記第４の電源リードをその全て幅
にわたって前記第２の端辺上を横断して前記半導体チッ
プ内上に入り込ませることもできる。Further, the first and second power supply leads extend over the semiconductor chip by passing over the first end side, and the third and fourth power supply leads extend over the second end. It can pass over the side and extend over the semiconductor chip. Alternatively, the first and third power supply leads extend on the third end side in the second direction and enter the inside of the semiconductor chip, and the second and fourth power supply leads are provided. It is possible to extend on the fourth side in the second direction and then enter the inside of the semiconductor chip.
Alternatively, the first and third power supply leads extend over the third end side in the second direction and enter the inside of the semiconductor chip, and the second power supply lead extends over the entire width thereof. Letting the semiconductor chip go into the semiconductor chip across the first edge, and letting the fourth power supply lead into the inside of the semiconductor chip across the entire width across the second edge. You can also
【００１７】さらに、前記第１の接続導体部と接続され
ていない第１の電源電位供給用の第５の電源リードおよ
び前記第２の接続導体部と接続されていない第２の電源
電位供給用の第６の電源リードを形成し、前記第５の電
源リードは前記第１の接続導体部と接続されていない第
１の電源パッドと第１のボンディングワイヤーにより接
続し、前記第６の電源リードを前記第２の接続導体部と
接続されていない第２の電源パッドと第１のボンディン
グワイヤーにより接続することができる。Further, a fifth power supply lead for supplying a first power supply potential which is not connected to the first connection conductor portion and a second power supply potential which is not connected to the second connection conductor portion. Forming a sixth power supply lead of the sixth power supply lead, the fifth power supply lead being connected to a first power supply pad not connected to the first connecting conductor portion by a first bonding wire. Can be connected to the second power supply pad that is not connected to the second connection conductor portion by the first bonding wire.
【００１８】前記第１の電源電位は接地電位に対して正
電位（Ｖｃｃ）もしくは負の電位（Ｖｓｓ）であり前記
第２が電源電位は接地電位（ＧＮＤ）であっても、ある
いは、前記第１の電源電位は接地電位に対して正電位で
あり、前記第２の電源電位は接地電位に対して負電位で
あってもよい。The first power source potential is a positive potential (Vcc) or a negative potential (Vss) with respect to the ground potential and the second power source potential is the ground potential (GND), or the first power source potential is the ground potential (GND). The first power supply potential may be positive with respect to the ground potential, and the second power supply potential may be negative with respect to the ground potential.
【００１９】[0019]
【実施例】本発明の第１の実施例を示す図１において、
Ｘ方向をたがいに平行に伸びる２０ｍｍ長の第１および
第２の端辺４１，４２およびＸ方向と直角方向のＹ方向
をたがいに平行に伸びる１０ｍｍ長の第３および第４の
端辺４３，４４を有する半導体チップ３１の中央部に、
Ｖｃｃ供給用の複数の第１の電源パッド３３ａ，接地電
位供給用の複数の第２の電源パッド３３ｂ，複数の第１
および第２の信号パッド３２ａおよび３２ｂが形成され
ている。一方、Ｖｃｃ供給用の第１および第２の電源リ
ード３５ａ，３５ｂは第１の端辺４１からそれぞれ第３
および第４の端辺４３，４４上をＹ方向に延在して半導
体チップ３１上に入り、そこでＸ方向を延在する部分を
有する０．５〜０．８ｍｍ幅の第１の接続導体部３６ａ
と連続的に接続されてＶｃｃ用のリード構造を形成して
いる。同様に、接地電位供給用の第３および第４の電源
リード３５ｃ，３５ｄは第２の端辺４２からそれぞれ第
３および第４の端辺４３，４４上をＹ方向に延在して半
導体チップ３１上に入り、そこで第１の接続導体部３６
ａと２．０〜２．５ｍｍの間隔を保って平行にＸ方向を
延在する部分を有する０．５〜０．８ｍｍ幅の第２の接
続導体部３６ｂと連続的に接続されて接地電位用のリー
ド構造を形成している。また、クロック信号等の各信号
を供受する複数の第１および第２の信号リード３４ａ，
３４ｂはそれぞれ第１および第２の端辺４１，４２を横
断して半導体チップ上に約３ｍｍ入り込んでいる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1 showing the first embodiment of the present invention,
20 mm long first and second edges 41, 42 extending parallel to the X direction and 10 mm long third and fourth edges 43 extending parallel to the Y direction perpendicular to the X direction. In the central portion of the semiconductor chip 31 having 44,
A plurality of first power supply pads 33a for supplying Vcc, a plurality of second power supply pads 33b for supplying a ground potential, a plurality of first power supplies
And second signal pads 32a and 32b are formed. On the other hand, the first and second power supply leads 35a and 35b for supplying Vcc are respectively provided from the first end side 41 to the third side.
And a first connecting conductor portion having a width of 0.5 to 0.8 mm, which has a portion extending on the fourth end sides 43 and 44 in the Y direction to enter on the semiconductor chip 31 and extending there in the X direction. 36a
Is continuously connected to form a lead structure for Vcc. Similarly, the third and fourth power supply leads 35c, 35d for supplying the ground potential extend in the Y direction from the second end side 42 on the third and fourth end sides 43, 44, respectively, and the semiconductor chip 31 on which the first connecting conductor 36
a and the second connection conductor portion 36b having a width of 0.5 to 0.8 mm, which has a portion extending in the X direction in parallel with a distance of 2.0 to 2.5 mm, and is continuously connected to the ground potential. Forming a lead structure for the. Further, a plurality of first and second signal leads 34a for supplying and receiving signals such as clock signals,
The reference numeral 34b crosses the first and second end sides 41 and 42, respectively, and enters about 3 mm on the semiconductor chip.
【００２０】そして複数の第１の信号パッド３２ａの全
部および第１の電源パッド３３ａの一部は、第１の端辺
４１と第１の接続導体部３６ａとの間をＸ方向に配列さ
れ、各第１の信号パッド３２ａはそれと接続する第１の
信号リード３４ａのボンディング領域とそれぞれ対向配
置している。同様に、複数の第２の信号パッド３２ｂの
全部および第２の電源パッド３３ｂの一部は、第２の端
辺４２と第２の接続導体部３６ｂとの間をＸ方向に配列
され、各第２の信号パッド３２ｂはそれと接続する第２
の信号リード３４ｂのボンディング領域とそれぞれ対向
配置している。また、残りの第１および第２の電源パッ
ド３３ａ，３３ｂは第１の接続導体部３６ａと第１の接
続導体部３６ｂとの間に配置されている。All of the plurality of first signal pads 32a and part of the first power supply pad 33a are arranged in the X direction between the first end 41 and the first connection conductor portion 36a. Each of the first signal pads 32a is arranged so as to face the bonding region of the first signal lead 34a connected thereto. Similarly, all of the plurality of second signal pads 32b and part of the second power supply pad 33b are arranged in the X direction between the second end side 42 and the second connection conductor portion 36b, and The second signal pad 32b is connected to the second signal pad 32b.
Are arranged so as to face the bonding regions of the signal leads 34b. The remaining first and second power supply pads 33a and 33b are arranged between the first connecting conductor portion 36a and the first connecting conductor portion 36b.
【００２１】このような構成により、複数の第１の電源
パッド３３ａは第１，第２の電源リード３５ａ，３５ｂ
および第１の接続導体部３６ａからなるＶｃｃ用リード
構造の近くの部分にそれぞれ第１のボンディングワイヤ
ー４７でボンディング接続することができ、複数の第２
の電源パッド３３ｂは第３，第４の電源リード３５ｃ，
３５ｄおよび第２の接続導体部３６ｂからなる接地電位
用リード構造の近くの部分にそれぞれ第１のボンディン
グワイヤー４７でボンディング接続することができる。
接続導体部はリードフレームの一部であり、リードと同
じ材質、膜厚であるから接続導体部による抵抗は無視す
ることができる。With this configuration, the plurality of first power supply pads 33a are connected to the first and second power supply leads 35a and 35b.
And a portion near the Vcc lead structure composed of the first connecting conductor portion 36a can be bonded and connected by the first bonding wire 47.
Of the power supply pad 33b of the third and fourth power supply leads 35c,
The first bonding wire 47 can be used for bonding connection to the portions near the ground potential lead structure composed of 35d and the second connection conductor portion 36b.
Since the connecting conductor portion is a part of the lead frame and has the same material and film thickness as the lead, the resistance due to the connecting conductor portion can be ignored.
【００２２】さらに上記構成によれば、第１の端辺４１
と第１の接続導電部３６ａとの間に複数の第１の信号パ
ッド３２ａおよびそれらと接続する第１の信号リード３
４ａが配設され、第２の端辺４２と第２の接続導電部３
６ｂとの間に複数の第２の信号パッド３２ｂおよびそれ
らと接続する第２の信号リード３４ｂが配設されてい
る。すなわちこれらのパッドおよびこのパッドと接続す
るリードのボンディング領域は、一対の電源リードと接
続導体部により囲まれた同一の領域内に載置されてい
る。したがって、第１，第２の信号リード３４ａ，３４
ｂと第１，第２の信号パッド３２ａ，３２ｂとをそれぞ
れボンディング接続する第２のボンディングワイヤー３
７が第１，第２の接続導電部３６ａ，３６ｂを含む電源
リード構造上を横断することはない。これにより第１の
ボンディングワイヤー３７と電源リード構造との短絡事
故は皆無となる。また同図に示すように、ボンディング
ワイヤー３７が他の信号リードもしくは他のボンディン
グワイヤーと立体交叉することもないから、それによる
短絡事故も生じない。Further, according to the above configuration, the first end side 41
And the first connection conductive portion 36a between the plurality of first signal pads 32a and the first signal leads 3 connected to them.
4a is provided, and the second end side 42 and the second connection conductive portion 3 are provided.
A plurality of second signal pads 32b and a second signal lead 34b connected to the second signal pads 32b are provided between the second signal pads 32b and 6b. That is, the bonding regions of these pads and the leads connected to these pads are placed in the same region surrounded by the pair of power supply leads and the connecting conductor portion. Therefore, the first and second signal leads 34a, 34
second bonding wire 3 for bonding and connecting b and the first and second signal pads 32a and 32b, respectively.
7 does not cross over the power supply lead structure including the first and second connection conductive portions 36a and 36b. As a result, there is no short circuit between the first bonding wire 37 and the power supply lead structure. Further, as shown in the figure, since the bonding wire 37 does not three-dimensionally intersect with another signal lead or another bonding wire, a short circuit accident due to that does not occur.
【００２３】ここでボンディングワイヤー３７，４７
は、例えば直径０．０３ｍｍの金細線であり、１．２〜
２．５ｍｍのワイヤー長で熱圧着法や超音波法でボンデ
ィング接続される。また、上記各信号リード、電源リー
ドおよび接続導電部は、例えば板厚０．２ｍｍの銅系の
板から一体的に形成されたリードフレームで、半導体チ
ップ上面に、例えば０．０９ｍｍ厚の接着テープで接着
されている。Here, the bonding wires 37, 47
Is, for example, a thin gold wire with a diameter of 0.03 mm,
Bonding connection is performed by a thermocompression bonding method or an ultrasonic method with a wire length of 2.5 mm. The signal leads, the power supply leads, and the connecting conductive portions are lead frames integrally formed of a copper-based plate having a thickness of 0.2 mm, for example. It is glued in.
【００２４】図１の工程の後、図２に示すように半導体
チップおよびその近傍を樹脂によりモールドし、その封
止樹脂４０の側面から導出した各リードをリードフレ−
ムから切り離し、直角に曲げて半導体集積回路装置を完
成する。After the step of FIG. 1, as shown in FIG. 2, the semiconductor chip and its vicinity are molded with resin, and each lead led out from the side surface of the sealing resin 40 is connected to the lead frame.
The semiconductor integrated circuit device is completed by separating it from the frame and bending it at a right angle.
【００２５】次に図３を参照して本発明の第２の実施例
を説明する。尚、図３において図１と同一もしくは類似
の機能の箇所は同じ符号で示してあるから、重複する説
明は省略する。Next, a second embodiment of the present invention will be described with reference to FIG. Note that, in FIG. 3, the portions having the same or similar functions to those in FIG.
【００２６】この第２の実施例では、電源パッド３３
ａ，３３ｂは全て第１の接続導電部３６ａと第２の接続
導電部３６ｂとの間に配設されている。一方、第１およ
び第２の信号パッド３２ａ，３２ｂは半導体チップ５１
の第１および第２の端辺４１，４２と直角のＹ方向に配
列され、第１の信号リード３４ａはＹ方向に延びて第１
の端辺４１上を通過して半導体チップ５１上を延在した
後にＸ方向に向って曲りその先端部を信号パッド３２と
対向させ、同様に、第２の信号リード３４ｂはＹ方向に
延びて第２の端辺４２上を通過して半導体チップ５１上
を延在した後にＸ方向に向って曲りその先端部を信号用
ボンディングパッドと対向させている。半導体チップの
形状や回路レイアウトによっては、この実施例のような
配置が好ましい場合が生じる。In the second embodiment, the power supply pad 33
All of a and 33b are arranged between the first connecting conductive portion 36a and the second connecting conductive portion 36b. On the other hand, the first and second signal pads 32a and 32b are connected to the semiconductor chip 51.
Are arranged in the Y direction at right angles to the first and second end sides 41, 42 of the first signal lead 34a, and the first signal lead 34a extends in the Y direction.
After passing over the edge 41 of the semiconductor chip 51 and bending in the X direction so that its tip end faces the signal pad 32. Similarly, the second signal lead 34b extends in the Y direction. After passing over the second end side 42 and extending over the semiconductor chip 51, it is bent in the X direction so that its tip end faces the signal bonding pad. Depending on the shape of the semiconductor chip and the circuit layout, the arrangement as in this embodiment may be preferable.
【００２７】図４に第３の実施例として、本発明を半導
体記憶装置に適用した例を示す。尚、図４において図１
と同一もしくは類似の機能の箇所は同じ符号で示してあ
るから、重複する説明は省略する。FIG. 4 shows a third embodiment in which the present invention is applied to a semiconductor memory device. In addition, in FIG.
Since the portions having the same or similar functions as those of the above are denoted by the same reference numerals, duplicate description will be omitted.
【００２８】半導体チップ６１の第１および第２の端辺
４１，４２を横断して複数の第１および第２の信号リー
ド３４ａ，３４ｂがチップ上に延在している。第１の信
号リード３４ａは、データ入出力用の信号リードＩ3 、
ライト・イネーブル用の信号リードＷＥ、ロウ・アドレ
ス・ストローブ入力用の信号リードＲＡＳ、アドレス入
力用の信号リードＡ0 〜Ａ5 を有しており、第２の信号
リード３４ｂは、アドレス入力用の信号リードＡ6 〜Ａ
12、アウトプット・イネーブル用の信号リードＯＥ、カ
ラム・アドレス・ストローブ入力用の信号リードＣＡ
Ｓ、データ入出力用の信号リードＩ4 〜Ｉ5 を有してい
る。さらにその外側（図の右側）には、第１の端辺４１
を横断してデータ入出力用の信号リードＩ0 〜Ｉ2 が第
３の信号リード３４ｃとして延在し、第２の端辺４２を
横断してデータ入出力用の信号リードＩ6 〜Ｉ7 が第４
の信号リード３４ｄとして延在している。A plurality of first and second signal leads 34a, 34b extend on the chip across the first and second edges 41, 42 of the semiconductor chip 61. The first signal lead 34a is a signal lead I 3 for data input / output,
It has a signal lead WE for write enable, a signal lead RAS for row address strobe input, and signal leads A 0 to A 5 for address input, and the second signal lead 34 b is for address input. Signal lead A 6 ~ A
12 , signal lead OE for output enable, signal lead CA for column address strobe input
S, signal leads I 4 to I 5 for data input / output. Further, on the outer side (on the right side of the figure), the first edge 41
The signal leads I 0 to I 2 for data input / output extend as the third signal lead 34 c across the line, and the signal leads I 6 to I 7 for data input / output across the second edge 42. Is the fourth
Signal lead 34d.
【００２９】一方、Ｖｃｃ供給用の第１の電源リード３
５ａは第１の端辺４１上から第３の端辺４３上をＹ方向
に延在して、また第２の電源リード３５ｂは第１の端辺
４１を横断して半導体チップ６１上に入り、両者が第１
の接続導体部３６ａと連続的に接続されてＶｃｃ用のリ
ード構造を形成している。同様に、接地電位（ＧＮＤ）
供給用の第３の電源リード３５ｃは第２の端辺４２上か
ら第３の端辺４３上をＹ方向に延在して、また第４の電
源リード３５ｄは第２の端辺４２を横断して半導体チッ
プ６１上に入り、両者が第２の接続導体部３６ｂと連続
的に接続されてＧＮＤ用のリード構造を形成している。
またこの実施例では、第１の接続導体部３６ａとは接続
されないＶｃｃ供給用の第５の電源リード３５ｅが第１
の端辺４１上から第４の端辺４４上をＹ方向に延在して
半導体チップ６１上に入り、同様に、第２の接続導体部
３６ｂとは接続されないＧＮＤ供給用の第６の電源リー
ド３５ｆが第２の端辺４２上から第４の端辺４４をＹ方
向に延在して半導体チップ６１上に入り込んでいる。ま
たＶｃｃ系のリード構造の一部は第２の端辺４２の方向
に突出して第２の端辺近傍のＶｃｃ用の電源パッド３３
ａと第１のボンディングワイヤー４７によりボンディン
グ接続され、接地電位系のリード構造の一部は第１の端
辺４１方向に突出して第１の端辺近傍の接地電位用の電
源パッド３３ｂと第１のボンディングワイヤー４７によ
りボンディング接続されている。On the other hand, the first power supply lead 3 for supplying Vcc
5a extends in the Y direction from above the first edge 41 to above the third edge 43, and the second power supply lead 35b crosses over the first edge 41 and enters the semiconductor chip 61. , Both are first
Is continuously connected to the connecting conductor portion 36a to form a lead structure for Vcc. Similarly, ground potential (GND)
The third power supply lead 35c for supplying extends in the Y direction from above the second end side 42 to above the third end side 43, and the fourth power supply lead 35d crosses the second end side 42. Then, they are placed on the semiconductor chip 61, and both are continuously connected to the second connecting conductor portion 36b to form a lead structure for GND.
Further, in this embodiment, the fifth power supply lead 35e for supplying Vcc which is not connected to the first connecting conductor portion 36a is the first
The sixth power supply for GND supply which extends in the Y direction from the end side 41 to the fourth side 44 and enters on the semiconductor chip 61, and is not connected to the second connection conductor portion 36b. The lead 35f extends from the second end side 42 to the fourth end side 44 in the Y direction and enters the semiconductor chip 61. Further, a part of the Vcc lead structure projects in the direction of the second edge 42, and the Vcc power supply pad 33 near the second edge 42.
a is connected to the first bonding wire 47 by bonding, and a part of the ground potential system lead structure projects toward the first edge 41 and is connected to the ground potential power supply pad 33b near the first edge and the first edge 41a. Bonding connection is made by a bonding wire 47.
【００３０】第１乃至第４の信号リード３４ａ〜３４ｄ
の先端箇所は、封止樹脂とリードフレームとの熱膨張率
の差によるワイヤー切れ防止のために凹凸形状６３とな
っており、この先端箇所より離間した箇所と白四角で示
すそれぞれの第１乃至第４の信号パッド３２ａ〜３２ｄ
とが第２のボンディングワイヤー３７でボンディング接
続されている。The first to fourth signal leads 34a to 34d.
Has a concavo-convex shape 63 for preventing wire breakage due to a difference in coefficient of thermal expansion between the sealing resin and the lead frame. Fourth signal pads 32a-32d
And are connected by bonding with a second bonding wire 37.
【００３１】また、第１乃至第６の電源リード３５ａ〜
３５ｆならびに第１および第２の接続導電部３６ａ，３
６ｂのＹ方向に突出する箇所にも同様の目的で凹凸形状
となっており、この凹凸形状の近傍の箇所と黒四角で示
すそれぞれの第１および第２の電源パッド３３ａ，３３
ｂとが第１のボンディングワイヤー４７でボンディング
接続されている。The first to sixth power supply leads 35a-
35f and first and second connection conductive portions 36a, 3
The portion of 6b protruding in the Y direction has an uneven shape for the same purpose, and portions near this uneven shape and the respective first and second power supply pads 33a, 33 shown by black squares.
b is connected by bonding with a first bonding wire 47.
【００３２】第１の信号リード３４ａに接続される全て
の第１の信号パッド３２ａおよび第３の信号リード３４
ｃに接続される全ての第３の信号パッド３２ｃならびに
第１および第２の電源パッド３３ａ，３３ｂの一部は、
第１の端辺４１の近傍をこの端辺と平行にＸ方向に配列
配置されている。同様に、第２の信号リード３４ｂに接
続される全ての第２の信号パッド３２ｂおよび第４の信
号リード３４ｄに接続される全ての第４の信号パッド３
２ｄならびに第１および第２の電源パッド３３ａ，３３
ｂの一部は、第２の端辺４２の近傍をこの端辺と平行に
Ｘ方向に配列配置されている。そして第１および第２の
電源パッド３３ａ，３３ｂの別の一部は第１の接続導体
部３６ａと第２の接続導体部３６ｂ間下およびその延長
線下の半導体チップの中央部にＸ線方向に配列配置して
いる。All of the first signal pads 32a and the third signal leads 34 connected to the first signal leads 34a.
All the third signal pads 32c connected to c and a part of the first and second power supply pads 33a and 33b are
The vicinity of the first edge 41 is arranged in parallel with the edge in the X direction. Similarly, all the second signal pads 32b connected to the second signal leads 34b and all the fourth signal pads 3 connected to the fourth signal leads 34d.
2d and the first and second power supply pads 33a, 33
Part of b is arranged in the X direction in the vicinity of the second end side 42 in parallel with the end side. Then, another part of the first and second power supply pads 33a and 33b is formed in the X-ray direction in the central portion of the semiconductor chip under the first connecting conductor portion 36a and the second connecting conductor portion 36b and under the extension thereof. Are arranged in an array.
【００３３】このような構成によれば図４に示すよう
に、第１および第３の信号リード３４ａ，３４ｃに接続
され第１の端辺４１方向に向ってそこの第１および第３
の信号パッド３２ａ，３２ｃにそれぞれ接続する第２の
ボンディングワイヤー３７および第２および第４の信号
リード３４ｂ，３４ｄに接続され第２の端辺４２方向に
向ってそこの第２および第４の信号パッド３２ｂ，３２
ｄにそれぞれ接続する第２のボンディングワイヤー３７
は、いずれも電源リード構造および他の信号リードのど
の部分上も横断しないように、また他のボンディングワ
イヤー上を横断しないようにすることが出来る。また第
１および第２の電源パッド３３ａ，３３ｂに接続された
第１のボンディングワイヤー４７は、いづれも他方の電
源リード構造および信号リードのどの部分上も横断しな
いように、また他のボンディングワイヤー上を横断しな
いようにすることが出来る。したがって、上記横断によ
るワイヤーの短絡事故を皆無にすることができる。尚、
図４において、ＮＣは使用しないリ−ドであり、ワイヤ
ーが接続されていない白四角は使用していないパッドを
示す。また、各リードが半導体チップ６１の外側でジグ
ザグ形状６２を有しているのは、樹脂封止を行ないリー
ドフレームから切離した後、引張り外力でリードが封入
樹脂から抜け落ないようにするためである。According to this structure, as shown in FIG. 4, the first and third signal leads 34a, 34c are connected to the first and third signal leads 34a, 34c in the direction of the first end 41.
Second bonding wire 37 connected to the signal pads 32a and 32c and second and fourth signals connected to the second and fourth signal leads 34b and 34d toward the second end 42, respectively. Pads 32b, 32
second bonding wire 37 connected to each of d
Can be neither crossed over any portion of the power lead structure and other signal leads, nor over other bond wires. Also, the first bonding wire 47 connected to the first and second power supply pads 33a and 33b should not cross over any part of the other power supply lead structure and signal lead, and on the other bonding wires. You can avoid crossing. Therefore, it is possible to eliminate the wire short circuit accident due to the crossing. still,
In FIG. 4, NC is a lead that is not used, and a white square to which a wire is not connected indicates a pad that is not used. Further, each lead has the zigzag shape 62 on the outside of the semiconductor chip 61 in order to prevent the leads from falling out of the encapsulating resin by an external pulling force after the resin is sealed and separated from the lead frame. is there.
【００３４】[0034]
【発明の効果】以上説明したように本発明では、一対の
電源リードと接続導体部とにより構成された、電源リー
ド構造に囲まれた同一領域内に載置された信号リードと
信号パッドとをボンディングワイヤーにより接続するか
ら、ボンディングワイヤーが接続導体部上を横断してい
ないことはない。したがって、信号系のボンディングワ
イヤーと電源電位系の接続導体部との短絡事故は皆無と
なる。As described above, according to the present invention, the signal lead and the signal pad, which are formed by the pair of power supply leads and the connecting conductor portion and are placed in the same region surrounded by the power supply lead structure, are provided. Since they are connected by the bonding wires, the bonding wires do not cross over the connecting conductor portion. Therefore, there is no short-circuit accident between the signal system bonding wire and the power supply potential system connecting conductor portion.
【図１】本発明の第１の実施例の半導体集積回路装置の
半導体チップとリードとの関係を示す平面図である。FIG. 1 is a plan view showing a relationship between a semiconductor chip and a lead of a semiconductor integrated circuit device according to a first embodiment of the present invention.
【図２】本発明の第１の実施例の半導体集積回路装置の
封止樹脂を一部切断して示した斜視図である。FIG. 2 is a perspective view showing a part of the sealing resin of the semiconductor integrated circuit device according to the first embodiment of the present invention.
【図３】本発明の第２の実施例の半導体集積回路装置の
半導体チップとリードとの関係を示す平面図である。FIG. 3 is a plan view showing a relationship between a semiconductor chip and a lead of a semiconductor integrated circuit device according to a second embodiment of the present invention.
【図４】本発明の第３の実施例の半導体集積回路装置の
半導体チップとリードとの関係を示す平面図である。FIG. 4 is a plan view showing a relationship between a semiconductor chip and a lead of a semiconductor integrated circuit device according to a third embodiment of the present invention.
【図５】従来技術の半導体集積回路装置の半導体チップ
とリードとの関係を示す平面図である。FIG. 5 is a plan view showing a relationship between a semiconductor chip and a lead of a semiconductor integrated circuit device according to a conventional technique.
【図６】他の従来技術の半導体集積回路装置の半導体チ
ップとリードとの関係を示す平面図である。FIG. 6 is a plan view showing a relationship between a semiconductor chip and a lead of another conventional semiconductor integrated circuit device.
１１，３１，５１，６１ 半導体チップ １２，３２ 信号パッド １３，３３ 電源パッド １４，３４ 信号リード １５，２５，３５ 電源リード １７，２７，３７，４７ ボンディングワイヤー ２６，３６ 接続導体部 ４０ モールド樹脂 ４１，４２，４３，４４ 半導体チップの端辺 ６２ リードのジグザグ形状 ６３ リードの凹凸形状 11, 31, 51, 61 Semiconductor chip 12, 32 Signal pad 13, 33 Power supply pad 14, 34 Signal lead 15, 25, 35 Power supply lead 17, 27, 37, 47 Bonding wire 26, 36 Connection conductor part 40 Mold resin 41 , 42, 43, 44 Edges of semiconductor chip 62 Zigzag shape of lead 63 Uneven shape of lead
Claims (25)
された複数の電源電位供給用ボンディングパッドおよび
複数の信号用ボンディングパッド、前記半導体チップの
外側より前記半導体チップ上に延在して形成された複数
の電源電位供給用リードおよび複数の信号用リード、一
対の前記電源電位供給用リード間を接続して前記半導体
チップ上を延在する接続導体部、前記電源電位供給用ボ
ンディングパッドと前記接続導体部とを接続する第１の
ボンディングワイヤー、および前記信号用ボンディング
パッドと前記信号用リードのボンディング領域とを接続
する第２のボンディングワイヤーを有する半導体集積回
路装置において、 それぞれの前記信号用ボンディングパッドとそれに接続
する前記信号用リードのボンディング領域とはその間に
前記接続導体部を介在させることなく対向配置され、こ
れにより前記第２のボンディングワイヤーが前記接続導
体部上を横断していないことを特徴とする半導体集積回
路装置。1. A semiconductor chip, a plurality of power supply potential supply bonding pads and a plurality of signal bonding pads formed on the semiconductor chip, and a plurality of semiconductor chips formed on the semiconductor chip from outside the semiconductor chip. Of power supply potential supply leads and a plurality of signal leads, a connecting conductor portion extending between the pair of power supply potential supply leads and extending on the semiconductor chip, the power supply potential supply bonding pad and the connection conductor portion In a semiconductor integrated circuit device having a first bonding wire for connecting the signal bonding pad and a second bonding wire for connecting the signal bonding pad and the bonding region of the signal lead, each of the signal bonding pad and Between the bonding area of the signal lead to be connected Are opposed without interposing a serial connection conductor portions, the semiconductor integrated circuit device according to claim this by the second bonding wire does not cross over the connecting conductor part.
および第２の端辺と前記第１の方向とは直角方向の第２
の方向をたがいに平行に伸びる第３および第４の端辺と
を有する半導体チップと、 前記半導体チップの外側から前記半導体チップ上に延在
する第１の電源電位供給用の第１および第２の電源リー
ドと、 前記半導体チップの外側から前記半導体チップ上に延在
する第２の電源電位供給用の第３および第４の電源リー
ドと、 前記第１および第２の電源リードと連続的に形成されて
前記半導体チップ上を前記第１の方向に延在する箇所を
有する第１の接続導体部と、 前記第３および第４の電源リードと連続的に形成されて
前記第１の接続導体部と所定の間隔を有して前記半導体
チップ上を前記第１の方向に延在する箇所を有する第２
の接続導体部と、 前記第１の端辺上を通過して前記第１の接続導体部と前
記第１の端辺間の前記半導体チップ上を延在する複数の
第１の信号用リードと、 前記第２の端辺上を通過して前記第２の接続導体部と前
記第２の端辺間の前記半導体チップ上を延在する複数の
第２の信号用リードと、 前記半導体チップに形成された第１の電源電位供給用ボ
ンディングパッドおよび第２の電源電位供給用ボンディ
ングパッドと、 前記第１の接続導体部下と前記第１の端辺との間の前記
半導体チップの部分に形成された複数の第１の信号用ボ
ンディングパッドと、 前記第２の接続導体部下と前記第２の端辺との間の前記
半導体チップの部分に形成された複数の第２の信号用ボ
ンディングパッドと、 前記第１の電源電位供給用ボンディングパッドと前記第
１の接続導体部間および前記第２の電源電位供給用ボン
ディングパッドと前記第２の接続導体間をそれぞれ接続
する複数の第１のボンディングワイヤーと、 複数の前記第１および第２の信号用ボンディングパッド
と複数の前記第１および第２の信号用リード間をそれぞ
れ接続する複数の第２のボンディングワイヤーとを有す
ることを特徴とする半導体集積回路装置。2. A first extending parallel to the first direction.
And a second edge which is perpendicular to the first end and the first direction.
A semiconductor chip having third and fourth end sides extending in parallel with each other in the direction of, and first and second first power supply potential supply extending from the outside of the semiconductor chip onto the semiconductor chip. Power supply leads, third and fourth power supply leads for supplying a second power supply potential extending from the outside of the semiconductor chip onto the semiconductor chip, and continuously with the first and second power supply leads. A first connecting conductor portion which is formed and has a portion extending on the semiconductor chip in the first direction, and the first and second connecting conductors which are continuously formed with the third and fourth power supply leads. A second portion having a portion that extends in the first direction on the semiconductor chip with a predetermined distance from the portion
And a plurality of first signal leads extending over the semiconductor chip between the first connection conductor portion and the first end side, passing through the first end side. A plurality of second signal leads extending on the semiconductor chip between the second connection conductor portion and the second end side, passing through the second end side; The first power supply potential supply bonding pad and the second power supply potential supply bonding pad that are formed, and the semiconductor chip portion between the first connection conductor portion and the first end side. A plurality of first signal bonding pads, and a plurality of second signal bonding pads formed in a portion of the semiconductor chip between the second connection conductor portion and the second end side. The first power supply potential supply bonding pad and the A plurality of first bonding wires connecting between the first connection conductor portions and between the second power supply potential supply bonding pad and the second connection conductor, and a plurality of the first and second signal bondings A semiconductor integrated circuit device comprising: a pad and a plurality of second bonding wires respectively connecting between the plurality of first and second signal leads.
ッドは前記第１の接続導体部下と前記第１の端辺との間
の前記半導体チップの部分を前記第１の方向に配列して
形成され、複数の前記第２の信号用ボンディングパッド
は前記第２の接続導体部下と前記第２の端辺との間の前
記半導体チップの部分を前記第１の方向に配列して形成
されていることを特徴とする請求項２に記載の半導体集
積回路装置。3. A plurality of the first signal bonding pads are formed by arranging portions of the semiconductor chip between the first connection conductor portion and the first end side in the first direction. The plurality of second signal bonding pads are formed by arranging portions of the semiconductor chip between the second connection conductor portion and the second end side in the first direction. The semiconductor integrated circuit device according to claim 2, wherein
ッドは前記半導体チップの前記第１の端辺の近傍部分を
前記第１の方向に配列して形成され、複数の前記第２の
信号用ボンディングパッドは前記半導体チップの前記第
２の端辺の近傍部分を前記第１の方向に配列して形成さ
れ、前記第１の信号用リードに接続された前記第２のボ
ンディングワイヤーは前記第１の端辺方向に延びて前記
第１の端辺の近傍部分に配列されたそれぞれの前記第１
の信号用ボンディングパッドと接続されており、前記第
２の信号用リードに接続された前記第２のボンディング
ワイヤーは前記第２の端辺方向に延びて前記第２の端辺
の近傍部分に配列されたそれぞれの前記第２の信号用ボ
ンディングパッドパッドと接続されていることを特徴と
する請求項２に記載の半導体集積回路装置。4. A plurality of the first signal bonding pads are formed by arranging portions near the first end side of the semiconductor chip in the first direction, and a plurality of the second signal bonding pads are formed. The bonding pad is formed by arranging a portion near the second edge of the semiconductor chip in the first direction, and the second bonding wire connected to the first signal lead is the first bonding wire. Of each of the first edges extending in the direction of the edge of the first edge and arranged in the vicinity of the first edge.
Second bonding wire connected to the second signal bonding pad and connected to the second signal lead extends in the second end side direction and is arranged in the vicinity of the second end side. 3. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device is connected to each of the formed second signal bonding pad pads.
との間の領域の外側の前記半導体チップの領域であって
かつ前記第１の端辺の近傍を、第３の信号用ボンディン
グパッドが複数の前記第１の信号用ボンディングパッド
とともに前記第１の方向に配列して形成され、前記第２
の導電体部下と前記第２の端辺との間の領域の外側の前
記半導体チップの領域であってかつ前記第２の端辺の近
傍を、第４の信号用ボンディングパッドが複数の前記第
２の信号用ボンディングパッドとともに前記第１の方向
に配列して形成され、第３の信号用リードに接続された
第２のボンディングワイヤーが前記第１の端辺方向に延
びて前記第１の端辺の近傍部分に配列されたそれぞれの
前記第３の信号用ボンディングパッドと接続されてお
り、第４の信号用リードに接続された前記第２のボンデ
ィングワイヤーが前記第２の端辺方向に延びて前記第２
の端辺の近傍部分に配列されたそれぞれの前記第４の信
号用ボンディングパッドと接続されていることを特徴と
する請求項４に記載の半導体集積回路装置。5. A third signal is provided in a region of the semiconductor chip outside a region between the lower portion of the first conductor and the first edge and in the vicinity of the first edge. Bonding pads for use with the plurality of first bonding pads for signals are arranged in the first direction, and
A region of the semiconductor chip outside a region between the conductor portion below and the second end side, and in the vicinity of the second end side, a plurality of fourth signal bonding pads are provided. A second bonding wire, which is formed together with two signal bonding pads in the first direction and is connected to the third signal lead, extends in the first edge direction and extends in the first end. The second bonding wire connected to each of the third signal bonding pads arranged in the vicinity of the side and connected to the fourth signal lead extends in the second end side direction. The second
5. The semiconductor integrated circuit device according to claim 4, wherein the semiconductor integrated circuit device is connected to each of the fourth signal bonding pads arranged in the vicinity of the edge of the.
第１および第２の信号用リードの先端箇所にボンディン
グされていることを特徴とする請求項２に記載の半導体
集積回路装置。6. The semiconductor integrated circuit device according to claim 2, wherein the second bonding wire is bonded to tip portions of the first and second signal leads.
第１および第２の信号用リードの先端箇所から離間した
箇所にボンディングされていることを特徴とする請求項
２に記載の半導体集積回路装置。7. The semiconductor integrated circuit device according to claim 2, wherein the second bonding wire is bonded to a portion separated from the tip portions of the first and second signal leads.
ることを特徴とする請求項７に記載の半導体集積回路装
置。8. The semiconductor integrated circuit device according to claim 7, wherein the tip portion has an uneven planar shape.
ヤーは前記第１乃至および第４の信号用リードの先端箇
所から離間した箇所にそれぞれボンディングされている
ことを特徴とする請求項５に記載の半導体集積回路装
置。9. The method according to claim 5, wherein the second and third bonding wires are respectively bonded to locations separated from the tip portions of the first to fourth signal leads. Semiconductor integrated circuit device.
いることを特徴とする請求項９に記載の半導体集積回路
装置。10. The semiconductor integrated circuit device according to claim 9, wherein the tip portion has an uneven planar shape.
パッドは前記第１の接続導体部下と前記第１の端辺との
間の前記半導体チップの部分を前記第２の方向に配列し
て形成され、複数の前記第２の信号用ボンディングパッ
ドは前記第２の接続導体部下と前記第２の端辺との間の
前記半導体チップの部分を前記第２の方向に配列して形
成されていることを特徴とする請求項２に記載の半導体
集積回路装置。11. A plurality of the first signal bonding pads are formed by arranging portions of the semiconductor chip between the first connection conductor portion and the first end side in the second direction. The plurality of second signal bonding pads are formed by arranging portions of the semiconductor chip between under the second connection conductor portion and the second end side in the second direction. The semiconductor integrated circuit device according to claim 2, wherein
方向に延びて前記第１の端辺上を通過して前記半導体チ
ップ上を延在した後に前記第１の方向に向って曲りその
先端部を前記第１の信号用ボンディングパッドと対向さ
せ、前記第２の信号用リードは前記第２の方向に延びて
前記第２の端辺上を通過して前記半導体チップ上を延在
した後に前記第１の方向に向って曲りその先端部を前記
第２の信号用ボンディングパッドと対向させていること
を特徴とする請求項１１に記載の半導体集積回路装置。12. The first signal lead extends in the second direction, passes over the first end side, extends over the semiconductor chip, and then bends in the first direction. The tip portion is opposed to the first signal bonding pad, and the second signal lead extends in the second direction, passes over the second end side, and extends over the semiconductor chip. 12. The semiconductor integrated circuit device according to claim 11, wherein the semiconductor integrated circuit device is bent in the first direction and is bent so that its tip end faces the second signal bonding pad.
ならびに前記複数の信号用リードはそれぞれクロック信
号用ボンディングパッドならびにクロック信号用リード
を含んでいることを特徴とする請求項２に記載の半導体
集積回路装置。13. The semiconductor integrated circuit device according to claim 2, wherein the plurality of signal bonding pads and the plurality of signal leads include a clock signal bonding pad and a clock signal lead, respectively. .
であり、前記複数の信号用ボンディングパッドならびに
前記複数の信号用リードはそれぞれデータ入出力用、ア
ドレス入力用、ライト・イネーブル用、ロウ・アドレス
・ストローブ用、アウトプット・イネーブル用ならびに
カラム・アドレス・ストローブ用のリードならびにボン
ディングパッドを含んでいることを特徴とする請求項２
に記載の半導体集積回路装置。14. A semiconductor integrated circuit device is a semiconductor memory device, wherein the plurality of signal bonding pads and the plurality of signal leads are for data input / output, address input, write enable, and row address, respectively. 3. Includes leads and bonding pads for strobes, output enables and column address strobes.
The semiconductor integrated circuit device according to 1.
ボンディングパッドはそれぞれ複数個形成されているこ
とを特徴とする請求項２に記載の半導体集積回路装置。15. The semiconductor integrated circuit device according to claim 2, wherein each of the first and second power supply potential supply bonding pads is formed in plural.
ディングパッドのうちの一部のパッドは前記第１の接続
導体部下と前記第１の端辺との間の前記半導体チップの
領域に形成され残りのパッドは前記第１および第２の接
続導体部間下の前記半導体チップの領域に形成されてお
り、前記複数の第２の電源電位供給用ボンディングパッ
ドのうちの一部のパッドは前記第２の接続導体部下と前
記第２の端辺との間の前記半導体チップの領域に形成さ
れ残りのパッドは前記第１および第２の接続導体部間下
の前記半導体チップの領域に形成されていることを特徴
とする請求項２に記載の半導体集積回路装置。16. A part of the plurality of first power supply potential supply bonding pads is formed in a region of the semiconductor chip between under the first connection conductor portion and the first end side. The remaining pads are formed in the region of the semiconductor chip below the first and second connection conductor portions, and some pads of the plurality of second power supply potential supply bonding pads are The remaining pads are formed in the region of the semiconductor chip between the second connection conductor portion and the second end side, and the remaining pads are formed in the region of the semiconductor chip between the first and second connection conductor portions. The semiconductor integrated circuit device according to claim 2, wherein
供給用ボンディングパッドの全ては前記第１および第２
の接続導体部間下の前記半導体チップの領域に形成され
ていることを特徴とする請求項２に記載の半導体集積回
路装置。17. All of the plurality of first and second bonding pads for supplying a power source potential are the first and second bonding pads.
3. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device is formed in a region of the semiconductor chip below between the connection conductor portions.
び第２の電源リードは前記第１の端辺上を通過して前記
半導体チップ上に延在し、前記第２の電源電位供給用の
第３および第４の電源リードは前記第２の端辺上を通過
して前記半導体チップ上に延在していることを特徴とす
る請求項２に記載の半導体集積回路装置。18. The first and second power supply leads for supplying the first power supply potential pass over the first end side and extend on the semiconductor chip to supply the second power supply potential. 3. The semiconductor integrated circuit device according to claim 2, wherein the third and fourth power supply leads for use pass through the second end side and extend on the semiconductor chip.
記第３の端辺上を前記第２の方向に延在して前記半導体
チップ内上に入り込んでいることを特徴とする請求項２
に記載の半導体集積回路装置。19. The first and third power supply leads extend on the third end side in the second direction and extend into the semiconductor chip.
The semiconductor integrated circuit device according to 1.
記第４の端辺上を前記第２の方向に延在してから前記半
導体チップ内上に入り込んでいることを特徴とする請求
項１９に記載の半導体集積回路装置。20. The second and fourth power supply leads extend into the second direction on the fourth side and then enter the inside of the semiconductor chip. 19. The semiconductor integrated circuit device according to item 19.
わたって前記第１の端辺上を横断して前記半導体チップ
内上に入り込み、前記第４の電源リードはその全て幅に
わたって前記第２の端辺上を横断して前記半導体チップ
内上に入り込んでいることを特徴とする請求項１９に記
載の半導体集積回路装置。21. The second power supply lead penetrates into the semiconductor chip across its entire width across the first end side, and the fourth power supply lead extends over the entire width of the second power supply lead. 20. The semiconductor integrated circuit device according to claim 19, wherein the semiconductor integrated circuit device penetrates into the inside of the semiconductor chip across an edge.
ない第１の電源電位供給用の第５の電源リードおよび前
記第２の接続導体部と接続されていない第２の電源電位
供給用の第６の電源リードが形成され、前記第５の電源
リードは前記第１の接続導体部と接続されていない第１
の電源電位供給用ボンディングパッドと前記第１のボン
ディングワイヤーにより接続され、前記第６の電源リー
ドは前記第２の接続導体部と接続されていない第２の電
源電位供給用ボンディングパッドと前記第１のボンディ
ングワイヤーにより接続されていることを特徴とする請
求項２に記載の半導体集積回路装置。22. A fifth power supply lead for supplying a first power supply potential that is not connected to the first connection conductor portion and a second power supply potential that is not connected to the second connection conductor portion. A sixth power supply lead is formed, and the fifth power supply lead is not connected to the first connection conductor portion.
The power supply potential supply bonding pad is connected by the first bonding wire, and the sixth power supply lead is not connected to the second connection conductor portion by the second power supply potential supply bonding pad and the first bonding wire. 3. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit devices are connected by the bonding wire.
て正電位もしくは負の電位であり、前記第２の電源電位
は接地電位であることを特徴とする請求項２に記載の半
導体集積回路装置。23. The semiconductor integrated device according to claim 2, wherein the first power supply potential is a positive potential or a negative potential with respect to a ground potential, and the second power supply potential is a ground potential. Circuit device.
て正電位であり、前記第２の電源電位は接地電位に対し
て負電位であることを特徴とする請求項２に記載の半導
体集積回路装置。24. The semiconductor according to claim 2, wherein the first power supply potential is a positive potential with respect to the ground potential and the second power supply potential is a negative potential with respect to the ground potential. Integrated circuit device.
樹脂により封止され、この封止樹脂から前記各リードが
導出されていることを特徴とする請求項２に記載の半導
体集積回路装置。25. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor pellet and its vicinity are sealed with a resin, and the leads are led out from the sealing resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05148734A JP3119544B2 (en) | 1992-07-08 | 1993-06-21 | Semiconductor integrated circuit device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18131792 | 1992-07-08 | ||
| JP4-181317 | 1992-07-08 | ||
| JP05148734A JP3119544B2 (en) | 1992-07-08 | 1993-06-21 | Semiconductor integrated circuit device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19352698A Division JP3169898B2 (en) | 1992-07-08 | 1998-07-09 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0677273A true JPH0677273A (en) | 1994-03-18 |
| JP3119544B2 JP3119544B2 (en) | 2000-12-25 |
Family
ID=26478840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP05148734A Expired - Fee Related JP3119544B2 (en) | 1992-07-08 | 1993-06-21 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3119544B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100266531B1 (en) * | 1996-10-29 | 2000-09-15 | 가네꼬 히사시 | Chip-lead interconnection structure in a semiconductor device |
| US6215157B1 (en) | 1998-07-31 | 2001-04-10 | Nec Corporation | Electrostatic discharge protection circuit for a semiconductor integrated circuit and layout thereof |
| WO2005008774A2 (en) * | 2003-07-11 | 2005-01-27 | Infineon Technologies Ag | Semiconductor chip comprising terminal contact areas grouped together in a confined zone |
| CN110034086A (en) * | 2015-09-15 | 2019-07-19 | 东芝存储器株式会社 | Lead frame |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06275771A (en) * | 1993-03-23 | 1994-09-30 | Hitachi Ltd | Semiconductor device and semiconductor chip incorporated in the semiconductor device |
| JPH06302644A (en) * | 1993-04-15 | 1994-10-28 | Hitachi Ltd | Semiconductor device |
| JPH06349875A (en) * | 1993-06-14 | 1994-12-22 | Hitachi Ltd | Semiconductor device |
-
1993
- 1993-06-21 JP JP05148734A patent/JP3119544B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06275771A (en) * | 1993-03-23 | 1994-09-30 | Hitachi Ltd | Semiconductor device and semiconductor chip incorporated in the semiconductor device |
| JPH06302644A (en) * | 1993-04-15 | 1994-10-28 | Hitachi Ltd | Semiconductor device |
| JPH06349875A (en) * | 1993-06-14 | 1994-12-22 | Hitachi Ltd | Semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100266531B1 (en) * | 1996-10-29 | 2000-09-15 | 가네꼬 히사시 | Chip-lead interconnection structure in a semiconductor device |
| US6215157B1 (en) | 1998-07-31 | 2001-04-10 | Nec Corporation | Electrostatic discharge protection circuit for a semiconductor integrated circuit and layout thereof |
| WO2005008774A2 (en) * | 2003-07-11 | 2005-01-27 | Infineon Technologies Ag | Semiconductor chip comprising terminal contact areas grouped together in a confined zone |
| WO2005008774A3 (en) * | 2003-07-11 | 2005-08-11 | Infineon Technologies Ag | Semiconductor chip comprising terminal contact areas grouped together in a confined zone |
| CN110034086A (en) * | 2015-09-15 | 2019-07-19 | 东芝存储器株式会社 | Lead frame |
| CN110034086B (en) * | 2015-09-15 | 2024-03-01 | 铠侠股份有限公司 | Lead frame |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3119544B2 (en) | 2000-12-25 |
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