JPH06275771A - Semiconductor device and semiconductor chip incorporated in the semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a wire from being seen through a package surface and being exposed by extending a bus bar lead along a center of a main surface of a semiconductor device, by arranging an electrode along both sides and by arranging a lead inner end part in an outside thereof. CONSTITUTION:A lead inner end part 6 of a lead part inside a package 1 is extended on a main surface of a semiconductor chip 3 through an insulating tape 7. Leads on both sides of a lead line in each lead line projecting to the both sides of the package 1 are connected inside the package 1 and form a bus bar lead 9. One bus bar lead 9 becomes a power supply lead 10 and the other becomes a grounding lead. The two bus bar leads 9 are applied on a vacant zone 5 at a center of the main surface of the semiconductor chip 3 through the insulating tape 7. Thereby, a wire does not cross over a bus bar lead and a lead inner end part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, especially LOC.
The present invention relates to a semiconductor device called "lead on chip" and a semiconductor chip incorporated in this semiconductor device.

[0002]

2. Description of the Related Art Electronic devices are required to have high-density mounting in terms of functions, and to be lightweight, compact, and thin in terms of mounting. Further, in order to reduce the manufacturing cost of electronic components, a resin-encapsulated (resin package) type semiconductor device, which is cheap in material and good in productivity, is widely used as a package form. Known resin package type semiconductor devices include those using a metal lead frame, TCP (Tape Carrier Packageng) in which leads are formed on the surface of an insulating film, and the like.

A semiconductor device using a lead frame is described in "Hitachi Kenron", No. 3, 1992, issued by Hitachi Hyoronsha, and issued on March 25, 1992, P75 to P80. This document describes TSO as a smaller and thinner package.
P (Thin Small Outline Package), SSOP (Shrink
Small Outline Package), TQFP (Thin Quad Flat)
Package), STZIP (Shrink Thin Zigzag Inline
Package) is disclosed. In addition, SOP (Small Outli
The ne Package) has outer leads arranged on two sides of the package, and the QFP (Thin Quad Flat Package) has outer leads arranged on the four sides of the package.
Further, in TSOP and TQFP, the lead pitch size is narrowed to 0.5 mm and the package body thickness is thinned to 1 mm.

Surface mounting is described in "Nikkei Electronics," issued by Nikkei BP, March 19, 1990 (No. 495), P119 to P136. In this document, as a package form of a multi-terminal / narrow-pitch LSI, a plastic flat package such as plastic or plastic SOP, TAB (Tape Automated Bonding) as a tape carrier package (TCP), and transfer mold as a tape carrier package. Mold TAB (mold TCP) by
Narrow pitch of outer leads in the package
It is described that it is shifting to 0.3 mm to 0.2 mm.

On the other hand, "Electronic Materials" issued by the Industrial Research Institute, July 1989 issue, July 1, the same year, P22 to P26, describes advantages and future prospects of the TAB technology. In this document, in the columns of mounting density and increasing number of pins, “the size of the IC pad for wire bonding is about 100 μm □, whereas the size of the bump is 50 μm □ for TAB. Also, the pad pitch for wire bonding is 120 μm minimum for the reason of machine, but 80 μm for TAB.
It is becoming possible even with the pitch of, and the appearance of the 50 μm pitch is also considered. It is described as ". Further, in this document, as the TAB tape, a ground tape capable of speeding up the device and reducing noise, and an area tape suitable for increasing the number of pins are introduced.

On the other hand, regarding a wire bonder for wire bonding, "Electronic Materials Separate Volume", 1991, published by the Industrial Research Board.
Issued on November 22, 2012, described on pages P92 to P97. In this document, the package structure is diversifying with the increase in speed, high integration, and multi-functionality (multi-terminal / large chip). In 16M DRAM, LOC (Lead On Chip)
It seems that more and more companies will adopt COL (Chip On Lead). ... "," The wire bonder is required to have a loop control function capable of coping with diversified packages at the same time as the conventional trend of increasing the bonding speed and in-line. " And
Deep access loops and J-shaped loops have been introduced as special loop shapes.

[0007] Further, TQFP having a package thickness of 1 mm is described in "Nikkei Microdevice", September 1988 issue, Nikkei BP, September 1, 1988, P115-P121. This document describes the control of the height of the bonding wire, and the variation in the height of the wire (loop height) is set to ± 50 μm or less, and the “bonding height is 200 μm or less. Average height. Is set to about 150 μm for bonding. ”

As one of the structures of the semiconductor device using the lead frame, the inner ends of the leads are mounted on the semiconductor chip via an insulating tape, and the inner ends of the leads are bonded to the upper surface of the semiconductor chip. LOC (Le (Lead) is formed by connecting pads with wires and encapsulating semiconductor chips, wires, and inner ends of leads with resin packages.
A semiconductor device having an ad on chip structure has been developed. LO
For the C (lead-on-chip) structure, see Nikkei BP
Published by Nikkei Microdevices, February 1991, 2
Issued on the 1st of the month, it is described in P89-P97. In the LOC structure, electrode pads (bonding pads) are arranged along the center of the semiconductor chip, and bus bar leads as power lines and ground lines are arranged on both sides of the bonding pad row via insulating tapes. Has been done. In addition, the inner end portions of the leads, which are signal lines, are arranged on the semiconductor chip outside the bus bar leads. Also, the bonding pad and bus bar
The leads and the inner ends of the leads are connected by conductive wires. The bus bar leads and other inner ends of the leads are adhered to the upper surface of the semiconductor chip via an insulating tape.

[0009]

As described in the above document, in the LOC structure, electrodes (electrode pads) are arranged along the center of the semiconductor chip, and bus bar leads extend outside the electrodes. Leads (lead inner ends) are lined up on the outside. The wire that electrically connects the electrode pad and the inner end of the lead is formed into a loop by crossing over the bus bar lead for power supply or ground. Therefore, the wire loop needs to be formed high so that the wire does not come into contact with the bus bar lead. On the other hand, as the semiconductor device becomes thinner, the thickness of the package also becomes thinner. TQF with a package thickness of 1 mm
In P, the thickness (height) from the upper surface of the inner end of the lead to the surface of the package is about 195 μm. When the package becomes thin as described above, a wire phenomenon is sometimes exposed on the surface of the package or a defect phenomenon in which the wire can be seen through occurs. Even if the loop forming accuracy in wire bonding is improved, the rigidity of the wire may vary
High wire loops are inevitable. In addition, the introduction of a wire bonding device that forms a special loop shape so that the wire does not hang down and contact the bus bar leads leads to a high bonding cost.

An object of the present invention is to provide a semiconductor device having a LOC structure in which wires are not visible or exposed on the package surface.

Another object of the present invention is to provide a semiconductor chip in which the wire loop can be lowered so that the wire cannot be seen through the package surface. The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

[0012]

The outline of the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, the semiconductor chip of the present invention is a chip in which a plurality of electrodes are provided along the central portion of the main surface
A bus bar, which is a semiconductor chip incorporated in a semiconductor device having an on-lead structure, wherein the electrodes are arranged in two rows, and between the rows are attached to a main surface of the semiconductor chip via an insulator (insulating tape).・ It is an empty zone with a width that allows leads to extend.

The LOC structure semiconductor device of the present invention has the semiconductor chip in a package having a vacant zone in which a bus bar lead can be arranged in the central portion of the main surface. Bus bar leads for power supply and ground extend through an insulating tape in an empty zone on the main surface of the semiconductor chip. The electrodes provided on the main surface of the semiconductor chip are arranged on both sides (outside) of the bus bar leads.
Leads (lead inner ends) are arranged on the main surface of the semiconductor chip further outside the electrode array via an insulating tape. Therefore, in this structure, the electrode of the semiconductor chip is located between the bus bar lead and the inner end of the lead. The electrodes are connected to the bus bar leads and the inner ends of the leads by wires made of conductive gold wire.

A semiconductor device having a LOC structure according to another embodiment of the present invention has a molded TCP structure. Leads (including bus bar leads) extending inside and outside the package made of resin are patterned on the insulating tape. Also, the insulating tape partially overlaps the main surface of the semiconductor chip. The semiconductor chip has a structure having the empty zone, and the bus bar leads extend through the insulating tape to the empty zone of the semiconductor chip. The inner ends of the leads are located on both sides of the bus bar leads. A part of the bus bar lead and the inner end of the lead serves as a joint, and the joint extends to the opening where the insulating tape is partially removed and is joined to the electrode on the main surface of the semiconductor chip. There is.

[0015]

According to the above-mentioned means, in the semiconductor chip of the present invention, the electrodes provided in the center of the main surface are in two rows, and the rows are vacant zones. In the LOC structure semiconductor device incorporating this semiconductor chip,
Bus bar leads are arranged in the empty zone. Therefore, when the electrode is connected to the inner end of the lead and the bus bar lead by a conductive wire, the electrode is located between the bus bar lead and the inner end of the lead, and thus the wire is It is possible to reduce the loop height of the wire without crossing over the bus bar lead or the inner end portion of the lead, and it is possible to prevent the occurrence of a defect in which the wire can be seen through the surface of the package.

Further, in another semiconductor device of the present invention having a molded TCP structure, the bus bar lead and the inner end portion of the lead are connected to the electrode by superposing the two, so that the wire is connected. The defects due to the structure are eliminated, and the thickness of the package can be further reduced.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 is a plan view showing a main part of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view of the same semiconductor device, FIG. 3 is a plan view of the same semiconductor device, and FIG. 4 is a view of an embodiment of the present invention. FIG. 5 is a plan view showing the main part of the semiconductor chip.
6 is a plan view showing a lead frame used for manufacturing the semiconductor device of the present invention, FIG. 6 is a plan view showing a state in which a lead frame is attached to a semiconductor chip in manufacturing the semiconductor device, and FIG. 7 is an insulating tape for the semiconductor device. Similarly, FIG. 8 is a plan view showing a lead frame on which a package is formed in the manufacture of a semiconductor device.

In the present invention, a DRAM (Dynamic Random Acc
A semiconductor device incorporating an ess memory will be described. The semiconductor device of the present invention, as shown in FIGS.
A plurality of leads 2 are respectively projected from both sides of a rectangular package 1 made of a resin.
A semiconductor chip 3 having a rectangular shape is sealed inside the package 1. Although not shown, a DRAM is formed on the semiconductor chip 3. In addition, as shown in FIG.
Electrodes (electrode pads: bonding pads) 4 across rows
Are provided in plural. The electrode rows are arranged along the longitudinal direction of the leads 2 and so as to form empty zones 5 having a constant width a between the rows.

In the lead 2 extending inside and outside the package 1, the lead portion (outer lead) outside the package 1 is molded, and as shown in FIG.
-It has a lead structure. In the lead portion (inner lead) in the package 1, the lead inner end portion 6 extends on the main surface of the semiconductor chip 3 via an insulating tape 7 (only the outer shape is shown in FIG. 1). Further, in each of the lead rows projecting on both sides of the package 1, the leads on both sides of the lead row are connected in the package 1 to form the bus bar leads 9. One of the bus bar leads 9 serves as a power supply lead 10 and the other serves as a grounding lead 11. These two bus bar leads 9
Is affixed to an empty zone 5 at the center of the main surface of the semiconductor chip 3 via an insulating tape 7.

The insulating tape 7 is a polyimide resin double-sided adhesive tape having a thickness of about 80 μm, and has a rectangular shape smaller than the semiconductor chip 3. The insulating tape 7 is provided with two slit-shaped openings 12 in parallel as shown in FIG. 7 so as not to block the electrodes 4 of the semiconductor chip 3 when attached to the main surface of the semiconductor chip 3. ing. The two bus bar leads 9 have the openings 12
Is adhered to the bus bar lead adhesion portion 15 of the above, and the lead inner end portion 6 is adhered to the lead adhesion portion 16 outside the opening 12.

The electrode 4 of the semiconductor chip 3 and the inner end portion 6 of the lead
And the bus bar lead 9 is a wire 1 made of a gold wire.
It is electrically connected by 7. . As an example of the dimensions of each part of the semiconductor device 20 having such a structure, the semiconductor chip 3 has a thickness of 280 μm, the insulating tape 7 has a thickness of 80 μm, the leads 2 have a thickness of 125 μm, and the semiconductor chip 3 has a lower portion. The resin has a thickness of 320 μm, the resin above the leads 2 has a thickness of 195 μm, and the package 1 has a thickness of 1 mm. Further, the loop height of the wire 17 enables low loop wire bonding, and a defect such that the wire 17 can be seen through the surface of the empty zone 5 does not occur.

Next, manufacturing of such a semiconductor device 20 will be described. First, the lead frame 21 as shown in FIG. 5 is prepared. This lead frame 21
Is formed by patterning a metal plate made of a Fe--Ni alloy or Cu alloy having a thickness of 0.125 mm by etching or precision press.
The lead frame 21 has a shape in which a plurality of unit lead patterns are arranged in series in one direction. The unit lead pattern is a frame 24 formed by a pair of outer frames 22 extending in parallel and a pair of inner frames 23 connecting the pair of outer frames 22 and extending in a direction orthogonal to the outer frame 22. Is formed inside.

On the other hand, a plurality of leads 2 extend from the inside of the inner frame 23 of the frame 24 toward the center of the frame 24.
These leads 2 extend in parallel to each other partway to form outer leads, but are bent toward the center of the frame 24 from the middle to form inner leads having a cantilever structure. The leads on both sides of the lead row are frame 24
Extending along the center of each of the bus bars to form a bus bar lead 9 connected to each other. This bus bar lead 9
It is formed by the leads 2 extending from both inner frames 23, one of which serves as a power supply lead 10 and the other of which serves as a grounding lead 11. The bus bar lead 9 extends in the center of the frame 24 in parallel with the inner frame 23 and is designed to overlap the empty zone 5 of the semiconductor chip 3. Further, the lead 2 of the outer lead portion is the inner frame 2
They are connected by a dam 25 extending in parallel with 3.
The dam 25 functions as a dam for blocking the outflow of the melted resin and as a strength member during the resin molding described later. A guide hole (not shown) is provided in the outer frame 22. This guide hole is for the lead frame 2
It is used as a guide for transporting and positioning 1.

In the lead frame 21, the tips of the leads 2 extending from the inner frames 23 (lead inner ends 6)
Face each of the bus bar leads 9 and have a constant distance from the bus bar leads 9. The electrode 4 of the semiconductor chip 3 is located in this space (space).

Next, the lead frame 21
Are stacked on the main surface of the semiconductor chip 3, as shown in FIG. An 80 μm thick insulating tape 7 made of a double-sided adhesive tape having a shape as shown in FIG. 7 is attached to the main surface of the semiconductor chip 3, and the inner lead portion of the lead frame 21 is attached to the insulating tape 7. It can be pasted. As shown in FIG. 7, the two bus bar leads 9 are bonded to the bus bar lead bonding portion 15 between the openings 12 of the insulating tape 7, and the lead inner end 6 is only partially shown. Are bonded to the lead bonding portion 16 outside the opening 12. Further, the electrodes 4 arranged in two rows of the semiconductor chip 3 are
It is located in the opening 12 of the insulating tape 7 and maintains an electrically independent state. As a result, the lead 2 becomes the semiconductor chip 3
Is insulatively attached to the major surface of the to form a LOC structure. In addition, this is one of the features of the present invention.
The electrode 4 is located between the bar lead 9 and the inner end 6 of the lead.

Next, the electrode 4 and the inner end portion 6 of the lead, and the electrode 4 and the bus bar lead 9 are electrically connected by a wire 17 made of a gold wire. In this wire bonding, even if the loop of the wire 17 is lowered, the wire 1
Since there is no conductor such as the bus bar lead 9 in the region where the wire 7 is stretched, the wire 17 can be stretched low.

Next, the lead frame 21 is formed with the package 1 at a predetermined portion by a commonly used molding (transfer molding) technique. Package 1 is
As shown in FIG. 8, the semiconductor chip 3, the inner end portion of the lead 6, the inner end portion of the bus bar lead 9 and the wire 17 are formed.
To cover. The package 1 has a thickness of 1 mm. Next, the unnecessary lead frame portion is cut and removed.
Further, the leads 2 protruding from the package 1 are molded to manufacture a gull-wing type semiconductor device 20 as shown in FIG.

[0028]

(1) In the semiconductor device having the LOC structure of the present invention, the semiconductor chip to be incorporated is provided with an empty zone in which the bus bar leads can extend in the center of the main surface thereof. The electrodes are positioned on both sides of the empty zone, and the electrodes of the semiconductor chip are positioned between the bus bar leads and the inner ends of the leads. Therefore, when electrically connecting the electrode to the inner end of the lead and the electrode to the bus bar lead by wire bonding, a short circuit does not occur even if the wire is lowered and sags, so that the wire can be stretched as low as possible. The effect is obtained.

(2) According to the above (1), in the semiconductor device of the present invention, the wire loop can be lowered at the time of manufacturing, so that the wire is exposed on the surface of the package or the wire can be seen through. It is possible to obtain the effect that no major defects occur. Therefore, the degree of moisture infiltration into the semiconductor chip through the wire is reduced, and the moisture resistance of the semiconductor device can be improved.

(3) Due to the above (2), the semiconductor device of the present invention can have a lower wire loop at the time of its manufacture, so that there is an effect that the thickness of the package can be made thinner.

(4) The semiconductor chip incorporated in the semiconductor device having the LOC structure of the present invention has a structure in which the bus bar leads can be extended along the center of the main surface of the semiconductor chip. Since the electrodes can be located on both sides of the bus bar lead, the structure is such that the bus bar lead is not arranged between the electrode and the inner end portion of the lead, and the wire bonding performed in the semiconductor device, that is, In wire bonding for connecting the inner end of the lead and the electrode with a wire, the effect that the wire can be formed low is obtained.

(5) Due to the above (1) to (4), according to the present invention, it is possible to prevent the occurrence of defects such that the wires can be seen through the surface of the package, so that the manufacturing yield of the semiconductor device can be improved. At the same time, a synergistic effect that a thinner package can be achieved can be obtained.

The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say, for example,
In the above-mentioned embodiment, the electrodes 4 of the semiconductor chip 3 are arranged along the longitudinal direction of the package 1, but they may be arranged along the width direction of the semiconductor chip 3.

9 to 10 are views showing a semiconductor device according to another embodiment of the present invention. FIG. 9 is a plan view showing an essential part of the semiconductor device, and FIG. 10 is a connection between inner ends of leads and electrodes. FIG. 11 is a cross-sectional view showing the state, and FIG. 11 is a cross-sectional view showing the connection state between the electrodes and the bus bar leads. The semiconductor device 20 of this embodiment has a molded TCP structure. That is, as shown in FIGS. 10 and 11, the leads 2 extending inside and outside the package 1 are supported by an insulating tape 30 made of polyimide resin and having a thickness of 35 μm. In addition, the insulating tape 30 is provided with an opening 31 by partially removing the insulating tape 30, similarly to the opening 12 of the insulating tape 7. Then, as shown in FIG. 9, the lead inner end portion 6 extends in the opening portion 31. A bonding portion 32 is provided on the lower surface of the lead inner end portion 6, that is, the surface of the semiconductor chip 3 facing the electrode 4. Also, from the bus bar lead 9 to the joining lead portion 3
3 projects and extends into the opening 31. A bonding portion 34 is provided on the lower surface of the bonding lead portion 33, that is, the surface of the semiconductor chip 3 facing the electrode 4. The lead 2 is formed by the TAB technique. That is, after the insulating tape is prepared, desired punching is performed by punching. Then, a copper foil is attached to one surface of the insulating tape, and the copper foil is etched to form a desired lead pattern. The inner ends 6 of the leads and the joining portions 32 and 34 of the joining lead portion 33 are made of, for example, gold bumps and are directly connected to the electrodes 4 of the semiconductor chip 3 by thermocompression bonding or the like. In this structure, since wire bonding is not performed, a defect in which the wire can be seen through the surface of the package 1 does not occur, and the package 1 does not occur.
Can be made thinner, for example, the package 1
Can be 0.5 mm or less.

In the above description, the invention made by the present inventor is the field of application which is the background of the invention.
Although the case of application to M has been described, the present invention is not limited to this, and can be applied to, for example, another IC manufacturing technology. INDUSTRIAL APPLICABILITY The present invention can be applied to the manufacture of at least a semiconductor device for wire bonding.

[Brief description of drawings]

FIG. 1 is a plan view showing a main part of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a plan view of a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a plan view showing a main part of a semiconductor chip according to an embodiment of the present invention.

FIG. 5 is a plan view showing a lead frame used for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a plan view showing a state in which a lead frame is attached to a semiconductor chip in manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 7 is a plan view showing an insulating tape in a semiconductor device according to an exemplary embodiment of the present invention.

FIG. 8 is a plan view showing a lead frame on which a package is formed in manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 9 is a plan view showing a main part of a semiconductor device according to another embodiment of the present invention.

FIG. 10 is a sectional view showing an essential part of a semiconductor device according to another embodiment of the present invention.

FIG. 11 is a sectional view showing a main part of a semiconductor device according to another embodiment of the present invention.

[Explanation of symbols]

1 ... Package, 2 ... Lead, 3 ... Semiconductor chip, 4 ...
Electrodes, 5 ... vacant zone, 6 ... inner end of lead, 7 ... insulating tape, 9 ... bus bar lead, 10 ... lead for power supply,
11 ... Ground lead, 12 ... Opening part, 15 ... Bus bar lead bonding part, 16 ... Lead bonding part, 17 ... Wire,
20 ... Semiconductor device, 21 ... Lead frame, 22 ... Outer frame, 23 ... Inner frame, 24 ... Frame, 25 ... Dam, 30 ... Insulating tape, 31 ... Opening part, 32 ... Joining part, 33 ... Joining lead part, 34 … Joints.

Claims (4)

[Claims] 1. A package made of a resin, leads extending inside and outside the package, and a semiconductor chip located in the package and having an electrode on a main surface thereof.
A bus bar lead and an inner end portion of the lead which are mounted on the main surface of the semiconductor chip via an insulator and extend, and a connection for electrically connecting the electrode to the bus bar lead and the inner end portion of the lead. Lead-on with means
In a semiconductor device having a chip structure, the bus bar lead extends along the center of the main surface of the semiconductor chip, and the electrodes are arranged along both sides of the bus bar lead and the electrode row A semiconductor device characterized in that inner ends of leads are arranged on the outer side. 2. The bus bar lead, the inner end of the lead and the electrode are electrically connected by a conductive wire, and the wire does not intersect with the bus bar lead. Item 1. The semiconductor device according to item 1. 3. The inner ends of the leads and the bus bar leads are formed on an insulating tape, and the inner ends of the leads and the bus bar leads have joints.
2. The semiconductor device according to claim 1, wherein the joint portion extends to the opening portion where the insulating tape is partially removed and is connected to the electrode of the semiconductor chip. 4. A semiconductor chip incorporated in a semiconductor device having a chip-on-lead structure in which a plurality of electrodes are provided along a central portion of a main surface, wherein the electrodes are arranged in two rows and the electrodes are arranged between the rows. Is a vacant zone having a width such that bus bar leads attached to the main surface of the semiconductor chip via an insulator can extend.