JP3856426B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JP3856426B2
JP3856426B2 JP2001271255A JP2001271255A JP3856426B2 JP 3856426 B2 JP3856426 B2 JP 3856426B2 JP 2001271255 A JP2001271255 A JP 2001271255A JP 2001271255 A JP2001271255 A JP 2001271255A JP 3856426 B2 JP3856426 B2 JP 3856426B2
Authority
JP
Japan
Prior art keywords
electrode pad
insulating film
interlayer insulating
opening
wire bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001271255A
Other languages
Japanese (ja)
Other versions
JP2003086624A (en
Inventor
光陽児 太田
寛之 大倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2001271255A priority Critical patent/JP3856426B2/en
Publication of JP2003086624A publication Critical patent/JP2003086624A/en
Application granted granted Critical
Publication of JP3856426B2 publication Critical patent/JP3856426B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0392—Methods of manufacturing bonding areas involving a specific sequence of method steps specifically adapted to include a probing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0392—Methods of manufacturing bonding areas involving a specific sequence of method steps specifically adapted to include a probing step
    • H01L2224/03921—Methods of manufacturing bonding areas involving a specific sequence of method steps specifically adapted to include a probing step by repairing the bonding area damaged by the probing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48647—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4

Description

【０００１】
【発明の属する技術分野】
本発明は電極パッドを備えた半導体装置に係り、特にダイソート用電極パッドとワイヤボンディング用電極パッドとを備えた半導体装置及びその製造方法に関するものである。
【０００２】
【従来の技術】
従来のボンディングパッドを備えた半導体装置のワイヤボンディング方法について、図９を用いて説明する。
【０００３】
図９（Ａ）には、ワイヤボンディングが行なわれる前のボンディングパッド周辺の半導体装置の断面が示される。図９（Ａ）に示されるように半導体基板５０上に第１層間絶縁膜５１を設けている。この第１層間絶縁膜５１上には、内部配線５２が設けられ、この内部配線５２上及び第１層間絶縁膜５１上には、第２層間絶縁膜５４が設けられている。内部配線５２にはコンタクト５３が接続されている。このコンタクト５３に接続されて、第２層間絶縁膜５４上にワイヤボンディング用電極パッド５５が設けられている。このワイヤボンディング用電極パッド５５の一部には開口部５６が設けられて、その上表面が露出している。この開口部５６以外のワイヤボンディング用電極パッド５５及び第２層間絶縁膜５４の上表面にはパッシベーション層５７が設けられている。
【０００４】
通常、半導体装置は半導体ウェハー状態での製造工程を終了した後、パッケージアセンブリをする前にウェハーレベルで不良品をスクリーニングするダイソートテストを行っている。
【０００５】
このダイソートテストを行なわずにワイヤボンディングを行なった状態が、図９（Ｂ）に示される。図９（Ａ）に示された開口部５６に露出したワイヤボンディング用電極パッド５５の上表面にボンディングワイヤ５８が接着されている。
【０００６】
次に、図１０を用いて、ダイソートテストを行なった場合のワイヤボンディング用電極パッド周辺の半導体装置の構造について説明する。図１０（Ａ）には、ダイソートテストの状態の断面が示される。金属製のダイソート用プローブ５９を開口部５６に露出したワイヤボンディング用電極パッド５５の上表面に接触させてダイソートを行なっている。ここで、ダイソート用プローブ５９とワイヤボンディング用電極パッド５５との電気的な接続を保証するように、ある程度の圧力をかけるために、ワイヤボンディング用電極パッド５５には傷６０が生じる。
【０００７】
このダイソートテストを行なった後で、ダイソート用プローブ５９を引き離し、このワイヤボンディング用電極パッド５５はパッケージアセンブリ工程でボンディングワイヤ５７を接続する。この様子が図１０（Ｂ）に断面図で示される。ボンディングワイヤ５７は、開口部５６に露出したワイヤボンディング用電極パッド５５上表面に接着される。ここで、ダイソート用プローブ５９の接触により生じた傷６０が原因でボンディングワイヤ５７の下に空隙６１ができる。この空隙６１により、ボンディングワイヤ５７とワイヤボンディング用電極パッド５５との接合面積が低下し、コンタクト性の悪化、パッケージ化された半導体装置の信頼性が劣化することが問題となる。
【０００８】
この問題を解決するために、従来では図１１に示されるような対策が提案されている。図１１は特開昭６２−２６１１３９号公報に記載された技術である。半導体基板６５上には、フィールド絶縁膜６６が形成されている。このフィールド絶縁膜６６上には、層間絶縁膜６７が設けられている。この層間絶縁膜６７が設けられていないチップ領域の周辺領域からスクライブライン上にかけて、フィールド絶縁膜６６の一部の上に検査用電極層６８が設けられている。このスクライブライン６８の一部分の上には検査用電極層６８が設けられ、この層間絶縁膜６７が設けられていない接続部分６９で配線金属層７０に接続されていて、チップ領域内の層間絶縁膜６７上に配線金属層７０が延在して設けられている。チップ領域内のパッド領域７２以外には、表面保護膜７１が設けられている。また、スクライブライン上には、検査用電極層６８に上表面が露出したダイソート用プローブの針当て領域７３が設けられている。このように、チップ領域以外にダイソート用プローブの針当て領域７３を設けることで、ダイソート用プローブによる傷がワイヤボンディング用電極パッドに影響を与えないようにしている。
【０００９】
また、図１２及び図１３に示されるような特開平１１−８７４４１号公報に記載された提案もある。図１２（Ａ）には、第１のタイプの電極パッドの断面構造が示され、図１２（Ｂ）には、その電極パッドの上面図が示される。このように同一電極パッドをダイソート用プローブの針当て領域７５とワイヤボンディング領域７６とに分けている。ダイソート用プローブの針当て領域７５には、ダイソート用プローブが接触した部分には、窪み状のプローブ接触痕７７が形成されている。ワイヤボンディング領域７６では、ボンディングワイヤ７８がその表面上に接着されている。
【００１０】
また、図１３（Ａ）には、第２のタイプの電極パッドの断面構造が示され、図１３（Ｂ）には、その電極パッドの上面図が示される。このように、隣接する電極パッドを配線８０でつなぎ、一つ目の電極パッドをダイソート用プローブの針当て領域８１に、もう一つの電極パッドをワイヤボンディング領域８２としている。ダイソート用プローブの針当て領域８１には、ダイソート用プローブが接触した部分には、窪み状のプローブ接触痕８３が形成されている。ワイヤボンディング領域８２では、ボンディングワイヤ８４がその表面上に接着されている。
【００１１】
これらの方法でダイソート時にダイソート用プローブにより生じた傷による影響がボンディングワイヤに接着されたパッド電極に及ばないようにしていた。
【００１２】
【発明が解決しようとする課題】
以上のような従来の半導体装置では、以下の課題が生じる。
【００１３】
図１１に示された方法では、スクライブラインの針当て領域とワイヤボンディング用電極パッドが離れてしまうデザイン、例えばチップの中央に電極パッドがある場合、スクライブラインと電極パッドを接続する配線の引き回しが困難になってしまう。またスクライブラインと電極パッドを接続する配線の延長は抵抗値を高めて回路特性を悪化させる要因となる欠点があった。特に高周波半導体装置では、配線長が長いことは抵抗が高くなり特性上の課題となる。
【００１４】
また、図１２又は図１３に示された方法では、電極パッドの面積を広げることになり半導体チップ縮小化への障害や、電極パッドから周辺回路までの配線が長くなることで回路特性を悪化させる要因があった。
【００１５】
本発明の目的は以上のような従来技術の課題を解決することにある。
【００１６】
特に、本発明の目的は電極パッド領域の面積を増加させずにボンディングワイヤとワイヤボンディング用電極パッドの電気特性を向上させた半導体装置及びその製造方法を提供することにある。
【００１７】
【課題を解決するための手段】
上記目的を達成するために、本発明の一態様の半導体装置は、半導体基板と、この半導体基板上に設けられた第１層間絶縁膜と、この第１層間絶縁膜上の一部に設けられた配線層と、前記第１層間絶縁膜上及び前記配線層上に設けられた第２層間絶縁膜と、この第２層間絶縁膜を介して形成され、かつ、前記配線層に接続された第１電極パッドと、この第１電極パッド上及び前記第２層間絶縁膜上に設けられ、その一部に前記第１電極パッド表面を露出させる開口が設けられた第３層間絶縁膜と、この第３層間絶縁膜を介して形成され、前記第３層間絶縁膜の開口上に開口を有する第２電極パッドと、この第２電極パッド上及び前記第３層間絶縁膜上に形成され、前記第２電極パッドの開口上に開口を有するパッシベーション層を備えることを特徴とする。
【００１８】
また、本発明の別の態様の半導体装置は、回路素子がその表面に形成された半導体基板と、この半導体基板上に形成された第1層間絶縁膜と、この第１層間絶縁膜上に形成され、前記回路素子に接続された内部配線層と、その内部配線層上と前記第１層間絶縁膜上に形成された第２層間絶縁膜と、その第２層間絶縁膜上に形成されたワイヤボンディング用電極パッドと、このワイヤボンディング用電極パッドと前記内部配線層とを接続する第１コンタクトと、前記ワイヤボンディング用電極パッド上に形成された第３層間絶縁膜と、この第３層間絶縁膜を介して、前記ワイヤボンディング用電極パッド上に形成されたダイソート用電極パッドと、このダイソート用電極パッドと前記ワイヤボンディング用電極パッドとの間に接続された第２コンタクトを備え、前記ダイソート用電極パッドはその一部に開口が設けられ、この開口下の前記第３層間絶縁膜に開口が設けられ、その前記第３層間絶縁膜の開口に前記ワイヤボンディング用電極パッド表面が露出していることを特徴とする。
【００１９】
また、本発明の別の態様の半導体装置は、半導体基板と、この半導体基板上に設けられた第１層間絶縁膜と、この第１層間絶縁膜上の一部に設けられた配線層と、前記第１層間絶縁膜上及び前記配線層上に設けられた第２層間絶縁膜と、この第２層間絶縁膜を介して形成され、かつ、前記配線層に接続された第１電極パッドと、この第１電極パッド上及び前記第２層間絶縁膜上に設けられ、その一部に前記第１電極パッド表面を露出させる開口が設けられた第３層間絶縁膜と、この第３層間絶縁膜を介して形成され、前記第３層間絶縁膜の開口上に開口を有する第２電極パッドと、この第２電極パッド上及び前記第３層間絶縁膜上に形成され、前記第２電極パッドの開口上に開口を有するパッシベーション層と、露出した前記第１電極パッド表面の少なくとも一部にワイヤボンディングされたボンディングワイヤを備えることを特徴とする。
【００２０】
また、本発明の別の態様の半導体装置の製造方法は、半導体基板上に第１層間絶縁膜を形成する工程と、この第１層間絶縁膜上に内部配線を形成する工程と、この内部配線上及び前記第１層間絶縁膜上に第２層間絶縁膜を形成する工程と、この第２層間絶縁膜上に前記内部配線に接続された第１電極パッドを形成する工程と、この第１電極パッド上及び前記第２層間絶縁膜上に第３層間絶縁膜を形成する工程と、この第３層間絶縁膜上に前記第１電極パッドに接続された第２電極パッドを形成する工程と、この第２電極パッド上及び前記第３層間絶縁膜上にパッシベーション層を形成する工程と、このパッシベーション層の前記第２電極パッド上表面の少なくとも一部を露出させるように開口を設ける工程と、この開口中に露出した前記第２電極パッドにプローブを当てて、ダイソートテストを行なう工程と、前記露出した第２電極パッド及びこの露出した第２電極パッド下方の前記第３層間絶縁膜を除去して、前記第１電極パッド上表面を露出する工程と、この露出した前記第１電極パッド上表面にボンディングワイヤをワイヤボンディングする工程を備えることを特徴とする。
【００２１】
【発明の実施の形態】
本実施の形態の半導体装置の構造を図１を用いて説明する。シリコンなどからなる半導体基板１上にＴＥＯＳ等のシリコン酸化膜などからなる第１層間絶縁膜２が形成されている。この第１層間絶縁膜２上には、半導体基板上に形成されているトランジスタ（図示せず）に接続される内部配線３が形成されている。この内部配線３にはＡｌ、Ｗなどの導電材料が用いられて形成される第１コンタクト４が接続されている。
【００２２】
この第１コンタクト４の上、及び第１層間絶縁膜２の上には、第２層間絶縁膜５が形成されている。さらに、この第２層間絶縁膜５上には、ワイヤボンディング用電極パッド６が形成されている。このワイヤボンディング用電極パッド６は例えば、アルミニウム合金や銅合金などから形成されている。このワイヤボンディング用電極パッド６には、第１コンタクト４が接続されている。このようにして、ワイヤボンディング用電極パッド６は第１コンタクト４と内部配線３により、トランジスタなどの回路素子から形成される信号入出力回路や電源回路等に接続される。
【００２３】
このワイヤボンディング用電極パッド６及び第２層間絶縁膜５上には、ＴＥＯＳなどのシリコン酸化膜からなる厚さが例えば、約０．４μｍ程度の第３層間絶縁膜８が形成されている。この第３層間絶縁膜８中には、ワイヤボンディング用電極パッド６に接続するように第２コンタクト７がＡｌ、Ｗなどの導電材料が用いられて形成されている。なお、第１コンタクト４及び第２コンタクト７はパッドと同様のアルミニウムなどの材料でもよい。
【００２４】
この第２コンタクト７に接続され、第３層間絶縁膜８の上で、かつ、ワイヤボンディング用電極パッド６の直上にダイソート用電極パッド９が形成されている。このダイソート用電極パッド９は例えば、アルミニウム合金や銅合金などから形成されている。ダイソート用電極パッド９は、ワイヤボンディングを行うことがないので、ボンディングワイヤとの接合性を考慮する必要が無く、アルミ合金や銅合金以外にポリシリコン、タングステン、タングステンシリサイド、チタン、窒化チタンなどから適宜、選択的に使用することができる。
【００２５】
このダイソート用電極パッド９には、開口部１０が設けられ、その開口部１０の大きさは例えば６０μｍ四方の四角形で形成されている。また、このダイソート用電極パッド９の開口部１０の真下の第３層間絶縁膜８中には、開口部１０が設けられ、ワイヤボンディング用電極パッド６の上表面が露出している。
【００２６】
ここで、ダイソート用電極パッド９及びワイヤボンディング用電極パッド６の厚さは例えば約１μｍ程度である。なお、ダイソート用電極パッド９の厚さはさらにより薄く設定してもよい、
さらに、第２層間絶縁膜５及びダイソート用電極パッド９の上には、シリコン窒化膜などから形成されるパッシベーション層１１が形成されている。このパッシベーション層１１においても、ダイソート用電極パッド９の開口部１０の真上に開口部１０が形成されている。ダイソート用電極パッド９の表面は開口部１０以外では、パッシベーション層１１により保護されている。
【００２７】
ワイヤボンディング用電極パッド９の開口部１０に露出した表面上には、金などから形成されたボンディングワイヤ１２が接続されている。
【００２８】
ダイソート用電極パッド９とワイヤボンディング用電極パッド６は、半導体基板１上の電極パッドの領域では開口して電極パッドとして機能するが、それ以外の領域では配線としても機能する。
【００２９】
また、ダイソート用電極パッド９の大きさをワイヤボンディング用電極パッド６の大きさより小さく形成することで、ボンディング面の開口部を設ける際にワイヤボンディング用電極パッド６の下面と同一面の第２層間絶縁膜５が露出することを防止でき、半導体装置の信頼性向上に役に立つ。なお、ワイヤボンディング用電極パッド６は特に電源パッドとして使用する場合などには、より大きい形状としてもよい。
【００３０】
本実施の形態によれば、ダイソート用電極パッドとワイヤボンディング用電極パッドを層構造とすることで半導体チップ表面における電極パッド領域の面積を小さくすることができ、半導体装置の高集積化を図ることができる。すなわち、従来例のようにダイソート用電極パッドとワイヤボンディング用電極パッドとを同一平面上に設けた場合と比べて、ダイソート用電極パッド分の面積を縮小することができる。
【００３１】
また、センターパッド方式の半導体装置であっても、センターパッド領域に抵抗の増大無しにダイソート用電極パッドを設けることができ、さらに小面積のパッド領域を得ることができる。
【００３２】
また、ダイソート用パッドの露出部は、ワイヤボンディング時には除去されている。このため、ダイソートを多数回繰り返して行って、ダイソート用パッド表面に多数の傷が生じていても、その傷が残ることがない。こうして、表面に凹凸が生じたパッドを持たない半導体装置を提供でき、半導体装置の信頼性を向上できる。
【００３３】
次に、本実施の形態の半導体装置の製造方法を図１乃至図８を用いて説明する。
【００３４】
図２に断面が示されるように、半導体基板１上にトランジスタ（図示せず）を設け、このトランジスタ上にＴＥＯＳ膜などからなる第１層間絶縁膜２を設け、その第１層間絶縁膜２中にトランジスタに接続する内部配線３を設ける。
【００３５】
さらに、この内部配線３上及び第１層間絶縁膜２上に第２層間絶縁膜５を設ける。さらに、この内部配線３に接続する第１コンタクト４を設ける。
【００３６】
次に、この第１コンタクト４に接続して、例えばアルミニウム合金又は銅合金などからなるワイヤボンディング用電極パッド６を第２層間絶縁膜５上に設ける。
【００３７】
このワイヤボンディング用電極パッド６及び第２層間絶縁膜５上にＴＥＯＳ膜などからなる第３層間絶縁膜８を形成する。
【００３８】
なお、ワイヤボンディング用電極パッド６に銅合金を使用した場合は、その表面には後の工程において接着されるボンディングワイヤとの接着性を増すためにアルミ二ウムを蒸着しておく。
【００３９】
さらに、第３層間絶縁膜８中にワイヤボンディング用電極パッド６に接続する第２コンタクト７を形成する。さらに、この第２コンタクト７に接続させて、ワイヤボンディング用電極パッド６の真上の第３層間絶縁膜８上に、例えばアルミニウム合金又は銅合金などからなるダイソート用電極パッド９を形成する。
【００４０】
さらに第３層間絶縁膜８上及びダイソート用電極パッド９上にパッシベーション層１１を形成する。さらに、このパッシベーション層１１の一部分を除去して開口部１３を設けて、ダイソート用電極パッド９の上表面の一部を露出させる。
【００４１】
ここでは、半導体基板は各半導体装置となる半導体チップとしては、まだ分割されておらず、半導体ウェハー状態となっている。
【００４２】
次に、図３に示されるように、開口部１３中で、金属製のダイソート用プローブ１４をダイソート用電極パッド９に接触させ、半導体ウェハー状態でのダイソートを行なう。ダイソート用プローブ１４と内部配線３は、ダイソート用電極パッド９、第２コンタクト７、ワイヤボンディング用電極パッド６、及び第１コンタクト４を介して電気的に接続されている。
【００４３】
次に、図４には、半導体ウェハー状態でのダイソートが終了した段階での半導体装置の断面図が示される。ここでは、ダイソート用プローブ１４をダイソート用電極パッド９から取り外した後の状態の断面が示されている。ダイソート用プローブ１４を取り外した後の開口部１３に露出したダイソート用電極パッド９には傷１６が生じている。図４に示されるように傷１６が深く形成された場合、第３層間絶縁膜８が露出した状態となっている。
【００４４】
さらに傷が深く形成されて、第３層間絶縁膜８中にまで達した場合であっても、後の工程で、当該部分の第３層間絶縁膜８は除去されるので、問題とはならない。
【００４５】
次に、図５には、マスク材１５を塗布した状態の半導体装置の断面が示される。このマスク材１５は感光性レジスト等が使用される。ｉ線等の光源によりダイソート用電極パッド９の開口部１３の位置に合わせて、マスク材１５がパターニングされる。この時、傷１６にマスク材１５が残らないように後処理をする。ここで、傷１６にマスク材１５が残らないように後処理を行うのは、次のアッシャー工程におけるＲＩＥ(Reactive Ion Etching)において、マスク材１５の残部で不均一なエッチングが行われてしまい、開口部に露出する第３層間絶縁膜８の上表面に凹凸が生じることを防止するためである。
【００４６】
次に、図６に示されるように半導体ウェハー表面からＣＤＥ（Chemical Dry Etching）、またはＲＩＥのエッチングを行い、ダイソート用電極パッド９に開口部１０を設ける。この際、第３層間絶縁膜８の表面はエッチングによりダメージがあるが、その下にあるワイヤボンディング用電極パッド６にはダメージは到達しない。このようにワイヤボンディング用電極パッド６にダメージが到達しないことで、後の工程におけるボンディングワイヤとの良好なボンディング性を維持できる。
【００４７】
この工程では、ダイソート用電極パッド９のエッチングが少々オーバー気味に行なわれた場合でも、その下方にある第３層間絶縁膜８を除去することがない。すなわち、使用する薬品と処理方法を変えることで、ダイソート用電極パッド９と第３層間絶縁膜８とを別々に除去することができる。なお、この工程において、ダイソートパッド全体を除去するのではなく、一部分のみを除去することで、開口をエッチングする際のばらつきなどによる周囲部分への影響を無くすことができる。
【００４８】
次に、図７に示されるようにレジスト１５をマスクとして、開口部１０に露出した第３層間絶縁膜８をＣＤＥ、又はＲＩＥのエッチングを行って取り除く。こうして、ワイヤボンディング用電極パッド６の上表面の一部が露出する。このとき、ワイヤボンディング用電極パッド６は、エッチングにより若干のダメージがあるが、それにより表面には第３層間絶縁膜８が残っていない状態となる。ここで、形成されるワイヤボンディング用電極パッド６の開口部１０の大きさは、図２で形成されるダイソート用電極パッド９の開口部１３の大きさよりも大きいことが好ましい。このような開口部の大小関係を持たせることで、ダイソート用電極パッド９に生じたダイソート用プローブ１４による損傷部１６を完全に除去することができる。
【００４９】
この工程においては、ボンディング用電極パッド６表面のエッチングダメージの制御は、ＲＩＥを用いた場合、使用する混合雰囲気の濃度とエッチング時間を調整して行なう。また、ＣＤＥを用いた場合、使用する薬液濃度とエッチング時間を調整して行う。また、第３層間絶縁膜８のエッチングの際には、少々オーバー気味にエッチングが行なわれてもボンディング用電極パッド６を溶かすことがないので、最終的にボンディング用電極パッド６の表面がダメージなく露出する。
【００５０】
なお、ボンディング用電極パッド６まで傷１６が到達してしまった場合、その表面をエッチングする際に、その傷１６を無くす程度までエッチングを進めると傷を残さなくすることも可能である。
【００５１】
ここで、ワイヤボンディング用電極パッド６の上に部分的に第３層間絶縁膜８が残っていると、絶縁膜が後の工程で接着するボンディングワイヤとワイヤボンディング用電極パッド６との間に介在することになり、ボンディング特性がきわだって低下する。このような状態が生じるのを防ぐため、例えば、約０．１μｍ程度の深さで余分にワイヤボンディング用電極パッド６の上表面を除去する。
【００５２】
次に、図８に示されるようにマスク材１５を除去して、パッシベーション層１１の上表面を露出させる。
【００５３】
次に、半導体ウェハーに複数個形成された半導体装置を個別にダイシングを施して、分離した後で、図１に示すようにワイヤボンディング用電極パッド６に例えば金からなるボンディングワイヤ１２を接続する。ワイヤボンディング用電極パッド６とボンディングワイヤ１２とは良好な接合をしている。すなわち、ダイソート用電極パッド９とワイヤボンディング用電極パッド６を分離して、配置することで、ダイソート用プローブ１４がダイソート用電極パッド９に接触するときに生ずる傷１６がワイヤボンディング用電極パッド６に影響を与えない。すなわち、ダイソート用電極パッド９とワイヤボンディング用電極パッド６とを分離して設けることで、ダイソート用プローブ１４の接触による電極パッドの傷があってもワイヤボンディング性に影響を与えない効果を得ることができる。
【００５４】
また、ダイソート用電極パッド９とワイヤボンディング用電極パッド６とを同一平面上に配置するのではなく、上下方向の層構造として配置することで、半導体装置に占める電極パッド領域の割合を小さくできる。
【００５５】
ここで、金からなるボンディングワイヤ１２が用いられ、アルミニウムからなるワイヤボンディング用電極パッド６が用いられた場合、ワイヤボンディング用電極パッド６のボンディングワイヤ１２との接触面には、アルミニウムと金との合金層が形成される。
【００５６】
なお、パッシベーション層１１とダイソート用電極パッド９との間、ダイソート用電極パッド９と第３層間絶縁膜８との間、ワイヤボンディング電極パッド６と第２層間絶縁膜５との間にそれぞれ、開口部を設けるエッチング工程の際にコロージョンが発生する可能性が見込まれる場合には、開口部に露出する側面をシリコン窒化膜などの保護膜で覆うことで、信頼性を向上することができる。この保護膜は図６に示される工程において、開口部１０を形成した後に露出面上にシリコン窒化膜を堆積する。さらに図７に示される工程において、第３層間絶縁膜８上に形成されたシリコン窒化膜を第３層間絶縁膜８とともに除去して、ボンディング用電極パッド６の上表面を露出することで、工程数の増加を最小限に抑制して、形成することができる。
【００５７】
また、ワイヤボンディング用電極パッド６に接着されたボンディングワイヤ１２が露出しているダイソート用電極パッド９の側面に接触するような状況が生じても、ダイソート用電極パッド９、ワイヤボンディング用電極パッド６、及びボンディングワイヤ１２は同一電位であるので、その特性上の問題はない。
【００５８】
なお、図６に示された工程において、ダイソート用電極パッド９やダイソート用電極パッド９とボンディング用電極パッド６との間の第２コンタクト７をすべて除去して、ボンディング用電極パッド６の開口部１０をより大きく形成することもできる。
【００５９】
さらに図６の工程において、ダイソート用電極パッド９やダイソート用電極パッド９とボンディング用電極パッド６との間の第２コンタクト７をすべて除去して、開口部１０の位置をダイソート用の開口部１３の位置と異ならせて、図６中でより右寄りに設けることもできる。
【００６０】
なお、図１で形成されたダイソート用電極パッド９は、すべてのパッドについてダイソートテストを行なう必要がなく、ダイソート用プローブ１４をすべてのダイソート用電極パッド９に接触しなくてもよい。そのようなダイソート用電極パッド９には、ダイソート用プローブ１４の接触による傷が表面に生じることはない。
【００６１】
本実施の形態によれば、ダイソート用電極パッドとワイヤボンディング用電極パッドを層構造とすることで半導体チップ表面における電極パッド領域の面積を小さくすることができ、高集積化された半導体装置の製造方法を提供できる。すなわち、従来例のようにダイソート用電極パッドとワイヤボンディング用電極パッドとを同一平面上に設けた場合と比べて、ダイソート用電極パッド分の面積を縮小した半導体装置の製造方法を提供することができる。
【００６２】
また、ダイソート用電極パッド９の露出部は、ワイヤボンディング時には除去されている。このため、ダイソートテストを多数回繰り返して行って、ダイソート用電極パッド９表面に多数の傷１６が生じていても、その傷１６が残ることがない。こうして、表面に凹凸が生じたワイヤボンディング用電極パッド６を持たない信頼性の高い半導体装置の製造方法を提供できる。
【００６３】
【発明の効果】
本発明によれば、電極パッド領域の面積を増加させずにボンディングワイヤとワイヤボンディング用電極パッドの電気特性を向上させた半導体装置及びその製造方法を提供できる。
【図面の簡単な説明】
【図１】 本発明の実施の形態の半導体装置の断面図。
【図２】 本発明の実施の形態の半導体装置の製造方法の一工程を表す断面図。
【図３】 本発明の実施の形態の半導体装置の製造方法の一工程を表す断面図。
【図４】 本発明の実施の形態の半導体装置の製造方法の一工程を表す断面図。
【図５】 本発明の実施の形態の半導体装置の製造方法の一工程を表す断面図。
【図６】 本発明の実施の形態の半導体装置の製造方法の一工程を表す断面図。
【図７】 本発明の実施の形態の半導体装置の製造方法の一工程を表す断面図。
【図８】 本発明の実施の形態の半導体装置の製造方法の一工程を表す断面図。
【図９】 （Ａ）は、従来の第１の技術の半導体装置の電極パッド周辺のワイヤボンディング前の状態を表す断面図であり、（Ｂ）は、従来の第１の技術の半導体装置の電極パッド周辺のワイヤボンディング後の状態を表す断面図である。
【図１０】 （Ａ）は、従来の第１の技術の半導体装置の電極パッド周辺のダイソートテストを行なっている状態を表す断面図であり、（Ｂ）は、従来の第１の技術の半導体装置の電極パッド周辺のダイソートテスト後のワイヤボンディング後の状態を表す断面図である。
【図１１】 従来の第２の技術の半導体装置の電極パッド周辺を表す断面図。
【図１２】 （Ａ）は、従来の第３の技術の半導体装置の電極パッド周辺を表す断面図であり、（Ｂ）は、従来の第３の技術の半導体装置の電極パッド周辺を表す上面図である。
【図１３】 （Ａ）は、従来の第４の技術の半導体装置の電極パッド周辺を表す断面図であり、（Ｂ）は、従来の第４の技術の半導体装置の電極パッド周辺を表す上面図である。
【符号の説明】
１ 半導体基板
２ 第１層間絶縁膜
３ 内部配線
４ 第１コンタクト
５ 第２層間絶縁膜
６ ワイヤボンディング用電極パッド
７ 第２コンタクト
８ 第３層間絶縁膜
９ ダイソート用電極パッド
１０，１３ 開口部
１１ パッシベーション層
１２ ボンディングワイヤ
１４ ダイソート用プローブ
１５ マスク材
１６ 傷[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including an electrode pad, and more particularly to a semiconductor device including a die sort electrode pad and a wire bonding electrode pad and a manufacturing method thereof.
[0002]
[Prior art]
A conventional wire bonding method for a semiconductor device having a bonding pad will be described with reference to FIG.
[0003]
FIG. 9A shows a cross section of the semiconductor device around the bonding pad before wire bonding is performed. As shown in FIG. 9A, a first interlayer insulating film 51 is provided on the semiconductor substrate 50. An internal wiring 52 is provided on the first interlayer insulating film 51, and a second interlayer insulating film 54 is provided on the internal wiring 52 and the first interlayer insulating film 51. A contact 53 is connected to the internal wiring 52. Connected to the contact 53, a wire bonding electrode pad 55 is provided on the second interlayer insulating film 54. An opening 56 is provided in a part of the wire bonding electrode pad 55 and its upper surface is exposed. A passivation layer 57 is provided on the upper surfaces of the wire bonding electrode pad 55 and the second interlayer insulating film 54 other than the opening 56.
[0004]
Usually, a semiconductor device performs a die sort test in which defective products are screened at a wafer level after completing a manufacturing process in a semiconductor wafer state and before package assembly.
[0005]
FIG. 9B shows a state in which wire bonding is performed without performing this die sort test. A bonding wire 58 is bonded to the upper surface of the wire bonding electrode pad 55 exposed at the opening 56 shown in FIG.
[0006]
Next, the structure of the semiconductor device around the wire bonding electrode pad when the die sort test is performed will be described with reference to FIG. FIG. 10A shows a cross section in the state of the die sort test. Die sorting is performed by bringing a metal die sort probe 59 into contact with the upper surface of the wire bonding electrode pad 55 exposed in the opening 56. Here, in order to apply a certain pressure so as to ensure electrical connection between the die sort probe 59 and the wire bonding electrode pad 55, the wire bonding electrode pad 55 is damaged.
[0007]
After performing the die sort test, the die sort probe 59 is pulled away, and the wire bonding electrode pads 55 are connected to the bonding wires 57 in the package assembly process. This state is shown in a cross-sectional view in FIG. The bonding wire 57 is bonded to the upper surface of the wire bonding electrode pad 55 exposed at the opening 56. Here, a gap 61 is formed under the bonding wire 57 due to the scratch 60 caused by the contact of the die sort probe 59. Due to the gap 61, the bonding area between the bonding wire 57 and the wire bonding electrode pad 55 is reduced, which causes a problem that the contact property is deteriorated and the reliability of the packaged semiconductor device is deteriorated.
[0008]
In order to solve this problem, conventionally, a countermeasure as shown in FIG. 11 has been proposed. FIG. 11 shows a technique described in Japanese Patent Laid-Open No. 62-261139. A field insulating film 66 is formed on the semiconductor substrate 65. An interlayer insulating film 67 is provided on the field insulating film 66. An inspection electrode layer 68 is provided on a part of the field insulating film 66 from the peripheral region of the chip region where the interlayer insulating film 67 is not provided to the scribe line. An inspection electrode layer 68 is provided on a part of the scribe line 68 and is connected to the wiring metal layer 70 at a connection portion 69 where the interlayer insulating film 67 is not provided. A wiring metal layer 70 is extended on 67. In addition to the pad area 72 in the chip area, a surface protective film 71 is provided. Further, on the scribe line, a needle contact area 73 of a die sort probe whose upper surface is exposed on the inspection electrode layer 68 is provided. In this manner, by providing the needle contact area 73 of the die sort probe in addition to the chip area, scratches caused by the die sort probe do not affect the wire bonding electrode pads.
[0009]
There is also a proposal described in JP-A-11-87441 as shown in FIGS. FIG. 12A shows a cross-sectional structure of the first type of electrode pad, and FIG. 12B shows a top view of the electrode pad. In this way, the same electrode pad is divided into the needle contact area 75 and the wire bonding area 76 of the die sort probe. In the needle contact area 75 of the die sort probe, a hollow probe contact mark 77 is formed at a portion where the die sort probe contacts. In the wire bonding region 76, the bonding wire 78 is bonded on the surface thereof.
[0010]
FIG. 13A shows a cross-sectional structure of a second type of electrode pad, and FIG. 13B shows a top view of the electrode pad. In this way, adjacent electrode pads are connected by the wiring 80, the first electrode pad is used as the needle contact area 81 of the die sort probe, and the other electrode pad is used as the wire bonding area 82. In the needle contact area 81 of the die sort probe, a hollow probe contact mark 83 is formed at a portion where the die sort probe contacts. In the wire bonding region 82, the bonding wire 84 is bonded on the surface thereof.
[0011]
With these methods, the effect of scratches caused by the die sort probe during die sort is prevented from affecting the pad electrode bonded to the bonding wire.
[0012]
[Problems to be solved by the invention]
The conventional semiconductor device as described above has the following problems.
[0013]
In the method shown in FIG. 11, when the needle pad area of the scribe line and the electrode pad for wire bonding are separated, for example, when there is an electrode pad at the center of the chip, wiring for connecting the scribe line and the electrode pad is not routed. It becomes difficult. In addition, the extension of the wiring connecting the scribe line and the electrode pad has a drawback of increasing the resistance value and deteriorating the circuit characteristics. In particular, in a high-frequency semiconductor device, a long wiring length increases resistance and causes a problem in characteristics.
[0014]
Further, in the method shown in FIG. 12 or FIG. 13, the area of the electrode pad is increased, an obstacle to the reduction of the semiconductor chip, and the wiring from the electrode pad to the peripheral circuit becomes longer, thereby deteriorating the circuit characteristics. There was a factor.
[0015]
An object of the present invention is to solve the above-described problems of the prior art.
[0016]
In particular, an object of the present invention is to provide a semiconductor device and a manufacturing method thereof in which the electrical characteristics of the bonding wire and the wire bonding electrode pad are improved without increasing the area of the electrode pad region.
[0017]
[Means for Solving the Problems]
To achieve the above objectiveThe semiconductor device of one embodiment of the present invention includes:A semiconductor substrate, a first interlayer insulating film provided on the semiconductor substrate, a wiring layer provided in a part on the first interlayer insulating film, and on the first interlayer insulating film and the wiring layer; A second interlayer insulating film provided; a first electrode pad formed through the second interlayer insulating film and connected to the wiring layer; the first electrode pad; and the second interlayer insulating film Provided on theAn opening for exposing the surface of the first electrode pad is provided in a part thereof.A third interlayer insulating film, and the third interlayer insulating film,An opening is formed on the opening of the third interlayer insulating film.Formed on the second electrode pad, the second electrode pad and the third interlayer insulating film;An opening is provided on the opening of the second electrode pad.A passivation layer is provided.
[0018]
In addition, a semiconductor device according to another aspect of the present invention includes:A semiconductor substrate having a circuit element formed on the surface thereof; a first interlayer insulating film formed on the semiconductor substrate; an internal wiring layer formed on the first interlayer insulating film and connected to the circuit element; A second interlayer insulating film formed on the internal wiring layer and the first interlayer insulating film, a wire bonding electrode pad formed on the second interlayer insulating film, and the wire bonding electrode pad; A first contact connecting the internal wiring layer, a third interlayer insulating film formed on the wire bonding electrode pad, and formed on the wire bonding electrode pad via the third interlayer insulating film An electrode pad for die sorting, and a second contact connected between the electrode pad for die sorting and the electrode pad for wire bonding,The die sort electrode pad has an opening in a part thereof, an opening is provided in the third interlayer insulating film below the opening, and the wire bonding electrode pad surface is exposed in the opening of the third interlayer insulating film. It is characterized by that.
[0019]
In addition, a semiconductor device according to another aspect of the present invention includes:A semiconductor substrate, a first interlayer insulating film provided on the semiconductor substrate, a wiring layer provided in a part on the first interlayer insulating film, and on the first interlayer insulating film and the wiring layer; A second interlayer insulating film provided; a first electrode pad formed through the second interlayer insulating film and connected to the wiring layer; the first electrode pad; and the second interlayer insulating film Provided on theAn opening for exposing the surface of the first electrode pad is provided in a part thereof.A third interlayer insulating film, and the third interlayer insulating film,An opening is formed on the opening of the third interlayer insulating film.Formed on the second electrode pad, the second electrode pad and the third interlayer insulating film;An opening is provided on the opening of the second electrode pad.A passivation layer,At least part of the exposed surface of the first electrode padIt comprises a bonding wire that is wire-bonded.
[0020]
A method for manufacturing a semiconductor device according to another aspect of the present invention includes:Forming a first interlayer insulating film on the semiconductor substrate; forming an internal wiring on the first interlayer insulating film; and forming a second interlayer insulating film on the internal wiring and on the first interlayer insulating film. A step of forming, a step of forming a first electrode pad connected to the internal wiring on the second interlayer insulating film, and a third interlayer insulating film on the first electrode pad and the second interlayer insulating film Forming a second electrode pad connected to the first electrode pad on the third interlayer insulating film, and a passivation layer on the second electrode pad and on the third interlayer insulating film. Forming an opening so as to expose at least a part of the surface of the passivation layer on the second electrode pad, applying a probe to the second electrode pad exposed in the opening, To test Removing the exposed second electrode pad and the third interlayer insulating film below the exposed second electrode pad to expose the upper surface of the first electrode pad; and A step of wire bonding a bonding wire to the upper surface of the first electrode pad is provided.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
The structure of the semiconductor device of this embodiment will be described with reference to FIG. A first interlayer insulating film 2 made of a silicon oxide film such as TEOS is formed on a semiconductor substrate 1 made of silicon or the like. On the first interlayer insulating film 2, an internal wiring 3 connected to a transistor (not shown) formed on the semiconductor substrate is formed. A first contact 4 formed by using a conductive material such as Al or W is connected to the internal wiring 3.
[0022]
A second interlayer insulating film 5 is formed on the first contact 4 and the first interlayer insulating film 2. Further, an electrode pad 6 for wire bonding is formed on the second interlayer insulating film 5. The wire bonding electrode pad 6 is made of, for example, an aluminum alloy or a copper alloy. A first contact 4 is connected to the wire bonding electrode pad 6. In this way, the wire bonding electrode pad 6 is connected to the signal input / output circuit, the power supply circuit, and the like formed from circuit elements such as transistors by the first contact 4 and the internal wiring 3.
[0023]
On the wire bonding electrode pad 6 and the second interlayer insulating film 5, a third interlayer insulating film 8 made of a silicon oxide film such as TEOS and having a thickness of about 0.4 μm, for example, is formed. In the third interlayer insulating film 8, a second contact 7 is formed using a conductive material such as Al or W so as to be connected to the electrode pad 6 for wire bonding. The first contact 4 and the second contact 7 may be made of a material such as aluminum similar to the pad.
[0024]
A die sort electrode pad 9 is formed on the third interlayer insulating film 8 and directly above the wire bonding electrode pad 6, connected to the second contact 7. The die sort electrode pad 9 is made of, for example, an aluminum alloy or a copper alloy. Since the die sort electrode pad 9 does not perform wire bonding, it is not necessary to consider the bonding property with the bonding wire, and other than aluminum alloy or copper alloy, polysilicon, tungsten, tungsten silicide, titanium, titanium nitride, etc. It can be used selectively as appropriate.
[0025]
The die sort electrode pad 9 is provided with an opening 10, and the size of the opening 10 is a square of 60 μm square, for example. An opening 10 is provided in the third interlayer insulating film 8 immediately below the opening 10 of the die sort electrode pad 9, and the upper surface of the wire bonding electrode pad 6 is exposed.
[0026]
Here, the thicknesses of the die sort electrode pad 9 and the wire bonding electrode pad 6 are, for example, about 1 μm. The thickness of the die sort electrode pad 9 may be set even thinner.
Further, a passivation layer 11 made of a silicon nitride film or the like is formed on the second interlayer insulating film 5 and the die sort electrode pad 9. Also in the passivation layer 11, the opening 10 is formed immediately above the opening 10 of the die sort electrode pad 9. The surface of the die sort electrode pad 9 is protected by a passivation layer 11 except for the opening 10.
[0027]
A bonding wire 12 made of gold or the like is connected to the surface exposed to the opening 10 of the wire bonding electrode pad 9.
[0028]
The die sort electrode pad 9 and the wire bonding electrode pad 6 open in the region of the electrode pad on the semiconductor substrate 1 and function as electrode pads, but also function as wiring in other regions.
[0029]
Further, by forming the die sort electrode pad 9 smaller than the wire bonding electrode pad 6, the second interlayer on the same surface as the lower surface of the wire bonding electrode pad 6 is provided when the opening of the bonding surface is provided. The insulating film 5 can be prevented from being exposed, which is useful for improving the reliability of the semiconductor device. The wire bonding electrode pad 6 may have a larger shape, particularly when used as a power supply pad.
[0030]
According to the present embodiment, the area of the electrode pad region on the surface of the semiconductor chip can be reduced by forming the electrode pad for die sorting and the electrode pad for wire bonding into a layer structure, thereby achieving high integration of the semiconductor device. Can do. That is, the area of the die sort electrode pad can be reduced as compared with the case where the die sort electrode pad and the wire bonding electrode pad are provided on the same plane as in the conventional example.
[0031]
Even in a center pad type semiconductor device, a die sort electrode pad can be provided in the center pad region without an increase in resistance, and a pad region with a smaller area can be obtained.
[0032]
The exposed portion of the die sort pad is removed during wire bonding. For this reason, even if the die sort is repeated many times and many scratches are generated on the die sort pad surface, the scratches will not remain. Thus, it is possible to provide a semiconductor device that does not have a pad with unevenness on the surface, and the reliability of the semiconductor device can be improved.
[0033]
Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS.
[0034]
As shown in FIG. 2, a transistor (not shown) is provided on the semiconductor substrate 1, a first interlayer insulating film 2 made of a TEOS film or the like is provided on the transistor, and the first interlayer insulating film 2 The internal wiring 3 connected to the transistor is provided.
[0035]
Further, a second interlayer insulating film 5 is provided on the internal wiring 3 and the first interlayer insulating film 2. Further, a first contact 4 connected to the internal wiring 3 is provided.
[0036]
Next, an electrode pad 6 for wire bonding made of, for example, an aluminum alloy or a copper alloy is provided on the second interlayer insulating film 5 so as to be connected to the first contact 4.
[0037]
A third interlayer insulating film 8 made of a TEOS film or the like is formed on the wire bonding electrode pad 6 and the second interlayer insulating film 5.
[0038]
In the case where a copper alloy is used for the wire bonding electrode pad 6, aluminum is vapor-deposited on the surface in order to increase the adhesiveness with the bonding wire to be bonded in a later step.
[0039]
Further, a second contact 7 connected to the wire bonding electrode pad 6 is formed in the third interlayer insulating film 8. Further, a die sort electrode pad 9 made of, for example, an aluminum alloy or a copper alloy is formed on the third interlayer insulating film 8 directly above the wire bonding electrode pad 6 so as to be connected to the second contact 7.
[0040]
Further, a passivation layer 11 is formed on the third interlayer insulating film 8 and the die sort electrode pad 9. Further, a part of the passivation layer 11 is removed to provide an opening 13 to expose a part of the upper surface of the die sort electrode pad 9.
[0041]
Here, the semiconductor substrate is not yet divided as a semiconductor chip to be each semiconductor device, and is in a semiconductor wafer state.
[0042]
Next, as shown in FIG. 3, a metal die sort probe 14 is brought into contact with the die sort electrode pad 9 in the opening 13 to perform die sort in a semiconductor wafer state. The die sort probe 14 and the internal wiring 3 are electrically connected via the die sort electrode pad 9, the second contact 7, the wire bonding electrode pad 6, and the first contact 4.
[0043]
Next, FIG. 4 shows a cross-sectional view of the semiconductor device at the stage where die sort in the semiconductor wafer state is completed. Here, a cross section of the state after the die sort probe 14 is removed from the die sort electrode pad 9 is shown. Scratches 16 are formed on the die sort electrode pad 9 exposed in the opening 13 after the die sort probe 14 is removed. As shown in FIG. 4, when the scratch 16 is formed deeply, the third interlayer insulating film 8 is exposed.
[0044]
Even when the scratches are deeply formed and reach the third interlayer insulating film 8, the third interlayer insulating film 8 in the portion is removed in a later process, so there is no problem.
[0045]
Next, FIG. 5 shows a cross section of the semiconductor device with the mask material 15 applied. As the mask material 15, a photosensitive resist or the like is used. The mask material 15 is patterned in accordance with the position of the opening 13 of the die sort electrode pad 9 by a light source such as i-line. At this time, post-processing is performed so that the mask material 15 does not remain on the scratch 16. Here, the post-processing is performed so that the mask material 15 does not remain on the scratches 16 because non-uniform etching is performed on the remaining portion of the mask material 15 in RIE (Reactive Ion Etching) in the next asher process. This is to prevent irregularities on the upper surface of the third interlayer insulating film 8 exposed in the opening.
[0046]
Next, as shown in FIG. 6, CDE (Chemical Dry Etching) or RIE etching is performed from the surface of the semiconductor wafer to provide an opening 10 in the die sort electrode pad 9. At this time, the surface of the third interlayer insulating film 8 is damaged by etching, but the damage does not reach the wire bonding electrode pad 6 under the surface. As described above, since the damage does not reach the wire bonding electrode pad 6, it is possible to maintain a good bonding property with the bonding wire in the subsequent process.
[0047]
In this step, even if the die sort electrode pad 9 is slightly over-etched, the third interlayer insulating film 8 below it is not removed. That is, the die sort electrode pad 9 and the third interlayer insulating film 8 can be removed separately by changing the chemicals used and the processing method. In this step, the entire die sort pad is not removed, but only a part is removed, so that the influence on the surrounding part due to variations in etching the opening can be eliminated.
[0048]
Next, as shown in FIG. 7, using the resist 15 as a mask, the third interlayer insulating film 8 exposed in the opening 10 is removed by CDE or RIE etching. Thus, a part of the upper surface of the wire bonding electrode pad 6 is exposed. At this time, although the wire bonding electrode pad 6 is slightly damaged by etching, the third interlayer insulating film 8 is not left on the surface. Here, the size of the opening 10 of the wire bonding electrode pad 6 to be formed is preferably larger than the size of the opening 13 of the die sort electrode pad 9 formed in FIG. By providing such a size relationship between the openings, the damaged portion 16 caused by the die sort probe 14 generated in the die sort electrode pad 9 can be completely removed.
[0049]
In this step, the etching damage on the surface of the bonding electrode pad 6 is controlled by adjusting the concentration of the mixed atmosphere used and the etching time when RIE is used. In addition, when CDE is used, the chemical concentration used and the etching time are adjusted. Further, when the third interlayer insulating film 8 is etched, the bonding electrode pad 6 is not melted even if the etching is performed slightly overly, so that the surface of the bonding electrode pad 6 is finally not damaged. Exposed.
[0050]
When the scratch 16 has reached the bonding electrode pad 6, when etching the surface, if the etching is advanced to the extent that the scratch 16 is eliminated, it is possible to eliminate the scratch.
[0051]
Here, if the third interlayer insulating film 8 partially remains on the wire bonding electrode pad 6, the insulating film is interposed between the bonding wire to be bonded in a later step and the wire bonding electrode pad 6. As a result, the bonding characteristics deteriorate significantly. In order to prevent such a state from occurring, for example, the upper surface of the wire bonding electrode pad 6 is removed to an extra depth of about 0.1 μm.
[0052]
Next, as shown in FIG. 8, the mask material 15 is removed to expose the upper surface of the passivation layer 11.
[0053]
Next, a plurality of semiconductor devices formed on the semiconductor wafer are individually diced and separated, and then bonding wires 12 made of, for example, gold are connected to the wire bonding electrode pads 6 as shown in FIG. The wire bonding electrode pad 6 and the bonding wire 12 are in good bonding. In other words, the die sorting electrode pad 9 and the wire bonding electrode pad 6 are separated and arranged so that the scratch 16 generated when the die sorting probe 14 contacts the die sorting electrode pad 9 is caused to the wire bonding electrode pad 6. Does not affect. That is, by providing the die sort electrode pad 9 and the wire bonding electrode pad 6 separately, even if the electrode pad is damaged by the contact of the die sort probe 14, the effect of not affecting the wire bonding property is obtained. Can do.
[0054]
Further, the die pad electrode pad 9 and the wire bonding electrode pad 6 are not arranged on the same plane, but are arranged as a layer structure in the vertical direction, so that the ratio of the electrode pad region in the semiconductor device can be reduced.
[0055]
Here, when the bonding wire 12 made of gold is used and the wire bonding electrode pad 6 made of aluminum is used, the contact surface of the wire bonding electrode pad 6 with the bonding wire 12 is made of aluminum and gold. An alloy layer is formed.
[0056]
Openings are provided between the passivation layer 11 and the die sort electrode pad 9, between the die sort electrode pad 9 and the third interlayer insulating film 8, and between the wire bonding electrode pad 6 and the second interlayer insulating film 5, respectively. If there is a possibility that corrosion will occur during the etching process of providing the portion, the reliability can be improved by covering the side surface exposed to the opening with a protective film such as a silicon nitride film. In the step shown in FIG. 6, this protective film is formed by depositing a silicon nitride film on the exposed surface after the opening 10 is formed. Further, in the step shown in FIG. 7, the silicon nitride film formed on the third interlayer insulating film 8 is removed together with the third interlayer insulating film 8 to expose the upper surface of the bonding electrode pad 6. It can be formed with minimal increase in number.
[0057]
Even when the bonding wire 12 bonded to the wire bonding electrode pad 6 comes into contact with the exposed side surface of the die sorting electrode pad 9, the die sorting electrode pad 9 and the wire bonding electrode pad 6 Since the bonding wire 12 has the same potential, there is no problem in its characteristics.
[0058]
In the step shown in FIG. 6, all of the die sort electrode pad 9 and the second contact 7 between the die sort electrode pad 9 and the bonding electrode pad 6 are removed, and the opening of the bonding electrode pad 6 is opened. 10 can also be formed larger.
[0059]
Further, in the step of FIG. 6, the die sort electrode pad 9 and the second contact 7 between the die sort electrode pad 9 and the bonding electrode pad 6 are all removed, and the position of the opening 10 is changed to the die sort opening 13. It can also be provided on the right side in FIG.
[0060]
The die sort electrode pads 9 formed in FIG. 1 do not need to be subjected to a die sort test, and the die sort probes 14 do not have to be in contact with all the die sort electrode pads 9. Such a die sort electrode pad 9 is not damaged on the surface by contact of the die sort probe 14.
[0061]
According to the present embodiment, the area of the electrode pad region on the surface of the semiconductor chip can be reduced by forming the electrode pad for die sorting and the electrode pad for wire bonding in a layered structure, and manufacturing a highly integrated semiconductor device Can provide a method. That is, it is possible to provide a method of manufacturing a semiconductor device in which the area of the die sort electrode pad is reduced as compared with the case where the die sort electrode pad and the wire bonding electrode pad are provided on the same plane as in the conventional example. it can.
[0062]
The exposed portion of the die sort electrode pad 9 is removed during wire bonding. For this reason, even if the die sort test is repeated many times and a large number of scratches 16 are generated on the surface of the electrode pad 9 for die sorting, the scratches 16 do not remain. Thus, it is possible to provide a method for manufacturing a highly reliable semiconductor device that does not have the wire bonding electrode pad 6 having irregularities on the surface.
[0063]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which improved the electrical characteristic of the bonding wire and the electrode pad for wire bonding, and its manufacturing method can be provided, without increasing the area of an electrode pad area | region.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a process of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating a step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a cross-sectional view illustrating a step of the method of manufacturing a semiconductor device according to the embodiment of the present invention.
FIG. 6 is a cross-sectional view illustrating a step of the method of manufacturing a semiconductor device according to the embodiment of the present invention.
FIG. 7 is a cross-sectional view illustrating a step of the method of manufacturing a semiconductor device according to the embodiment of the present invention.
FIG. 8 is a cross-sectional view illustrating a step of the method of manufacturing a semiconductor device according to the embodiment of the present invention.
9A is a cross-sectional view showing a state before wire bonding around an electrode pad of a conventional semiconductor device of the first technology, and FIG. 9B is a cross-sectional view of the conventional semiconductor device of the first technology. It is sectional drawing showing the state after wire bonding around an electrode pad.
FIG. 10A is a cross-sectional view showing a state in which a die sort test is performed around the electrode pad of the semiconductor device of the conventional first technique, and FIG. 10B is a diagram of the conventional first technique. It is sectional drawing showing the state after the wire bonding after the die sort test of the electrode pad periphery of a semiconductor device.
FIG. 11 is a sectional view showing the periphery of an electrode pad of a semiconductor device according to a second conventional technique.
12A is a cross-sectional view illustrating the periphery of an electrode pad of a semiconductor device according to a third conventional technique, and FIG. 12B is a top view illustrating the periphery of the electrode pad of a semiconductor device according to a third conventional technique. FIG.
13A is a cross-sectional view illustrating the periphery of an electrode pad of a semiconductor device according to a fourth conventional technique, and FIG. 13B is a top view illustrating the periphery of the electrode pad of a semiconductor device according to a fourth conventional technique. FIG.
[Explanation of symbols]
1 Semiconductor substrate
2 First interlayer insulating film
3 Internal wiring
4 First contact
5 Second interlayer insulating film
6 Electrode pads for wire bonding
7 Second contact
8 Third interlayer insulating film
9 Die sort electrode pads
10,13 opening
11 Passivation layer
12 Bonding wire
14 Probe for die sort
15 Mask material
16 wounds

Claims (7)

半導体基板と、この半導体基板上に設けられた第１層間絶縁膜と、この第１層間絶縁膜上の一部に設けられた配線層と、前記第１層間絶縁膜上及び前記配線層上に設けられた第２層間絶縁膜と、この第２層間絶縁膜を介して形成され、かつ、前記配線層に接続された第１電極パッドと、この第１電極パッド上及び前記第２層間絶縁膜上に設けられ、その一部に前記第１電極パッド表面を露出させる開口が設けられた第３層間絶縁膜と、この第３層間絶縁膜を介して形成され、前記第３層間絶縁膜の開口上に開口を有する第２電極パッドと、この第２電極パッド上及び前記第３層間絶縁膜上に形成され、前記第２電極パッドの開口上に開口を有するパッシベーション層と、を備えることを特徴とする半導体装置。A semiconductor substrate, a first interlayer insulating film provided on the semiconductor substrate, a wiring layer provided in a part on the first interlayer insulating film, and on the first interlayer insulating film and the wiring layer; A second interlayer insulating film provided; a first electrode pad formed through the second interlayer insulating film and connected to the wiring layer; the first electrode pad; and the second interlayer insulating film A third interlayer insulating film provided on the first electrode pad surface, and an opening for exposing the surface of the first electrode pad; and an opening of the third interlayer insulating film formed through the third interlayer insulating film. A second electrode pad having an opening thereon; and a passivation layer formed on the second electrode pad and the third interlayer insulating film and having an opening on the opening of the second electrode pad. A semiconductor device. 前記配線層と前記第１電極パッドとを接続する第１コンタクトと、前記第１電極パッドと前記第２電極パッドとを接続する第２コンタクトとをさらに備えることを特徴とする請求項１記載の半導体装置。2. The device according to claim 1, further comprising: a first contact that connects the wiring layer and the first electrode pad; and a second contact that connects the first electrode pad and the second electrode pad. Semiconductor device. 回路素子がその表面に形成された半導体基板と、この半導体基板上に形成された第1層間絶縁膜と、この第１層間絶縁膜上に形成され、前記回路素子に接続された内部配線層と、その内部配線層上と前記第１層間絶縁膜上に形成された第２層間絶縁膜と、その第２層間絶縁膜上に形成されたワイヤボンディング用電極パッドと、このワイヤボンディング用電極パッドと前記内部配線層とを接続する第１コンタクトと、前記ワイヤボンディング用電極パッド上に形成された第３層間絶縁膜と、この第３層間絶縁膜を介して、前記ワイヤボンディング用電極パッド上に形成されたダイソート用電極パッドと、このダイソート用電極パッドと前記ワイヤボンディング用電極パッドとの間に接続された第２コンタクトと、を備え、前記ダイソート用電極パッドはその一部に開口が設けられ、この開口下の前記第３層間絶縁膜に開口が設けられ、その前記第３層間絶縁膜の開口に前記ワイヤボンディング用電極パッド表面が露出していることを特徴とする半導体装置。A semiconductor substrate having a circuit element formed on the surface thereof; a first interlayer insulating film formed on the semiconductor substrate; an internal wiring layer formed on the first interlayer insulating film and connected to the circuit element; A second interlayer insulating film formed on the internal wiring layer and the first interlayer insulating film, a wire bonding electrode pad formed on the second interlayer insulating film, and the wire bonding electrode pad; A first contact connecting the internal wiring layer, a third interlayer insulating film formed on the wire bonding electrode pad, and formed on the wire bonding electrode pad via the third interlayer insulating film A die sort electrode pad, and a second contact connected between the die sort electrode pad and the wire bonding electrode pad, the die sort electrode An opening is provided in a part of the pad, an opening is provided in the third interlayer insulating film below the opening, and the surface of the electrode pad for wire bonding is exposed in the opening of the third interlayer insulating film A semiconductor device characterized by the above. 前記ダイソート用電極パッド及び前記ワイヤボンディング用電極パッドは、アルミニウム合金又は銅合金のいずれかから選択された材料により形成されていることを特徴とする請求項３記載の半導体装置。4. The semiconductor device according to claim 3, wherein the die sort electrode pad and the wire bonding electrode pad are formed of a material selected from either an aluminum alloy or a copper alloy. 半導体基板と、この半導体基板上に設けられた第１層間絶縁膜と、この第１層間絶縁膜上の一部に設けられた配線層と、前記第１層間絶縁膜上及び前記配線層上に設けられた第２層間絶縁膜と、この第２層間絶縁膜を介して形成され、かつ、前記配線層に接続された第１電極パッドと、この第１電極パッド上及び前記第２層間絶縁膜上に設けられ、その一部に前記第１電極パッド表面を露出させる開口が設けられた第３層間絶縁膜と、この第３層間絶縁膜を介して形成され、前記第３層間絶縁膜の開口上に開口を有する第２電極パッドと、この第２電極パッド上及び前記第３層間絶縁膜上に形成され、前記第２電極パッドの開口上に開口を有するパッシベーション層と、前記第１電極パッド上にワイヤボンディングされたボンディングワイヤと、を備えることを特徴とする半導体装置。A semiconductor substrate, a first interlayer insulating film provided on the semiconductor substrate, a wiring layer provided in a part on the first interlayer insulating film, and on the first interlayer insulating film and the wiring layer; A second interlayer insulating film provided; a first electrode pad formed through the second interlayer insulating film and connected to the wiring layer; the first electrode pad; and the second interlayer insulating film A third interlayer insulating film provided on the first electrode pad surface, and an opening for exposing the surface of the first electrode pad; and an opening of the third interlayer insulating film formed through the third interlayer insulating film. A second electrode pad having an opening thereon, a passivation layer formed on the second electrode pad and the third interlayer insulating film, and having an opening on the opening of the second electrode pad; and the first electrode pad Bonding wire wire bonded on top A semiconductor device characterized in that it comprises a. 半導体基板上に第１層間絶縁膜を形成する工程と、この第１層間絶縁膜上に内部配線を形成する工程と、この内部配線上及び前記第１層間絶縁膜上に第２層間絶縁膜を形成する工程と、この第２層間絶縁膜上に前記内部配線に接続された第１電極パッドを形成する工程と、この第１電極パッド上及び前記第２層間絶縁膜上に第３層間絶縁膜を形成する工程と、この第３層間絶縁膜上に前記第１電極パッドに接続された第２電極パッドを形成する工程と、この第２電極パッド上及び前記第３層間絶縁膜上にパッシベーション層を形成する工程と、このパッシベーション層の前記第２電極パッド上表面の少なくとも一部を露出させるように開口を設ける工程と、この開口中に露出した前記第２電極パッドにプローブを当てて、ダイソートテストを行なう工程と、前記露出した第２電極パッド及びこの露出した第２電極パッド下方の前記第３層間絶縁膜を除去して、前記第１電極パッド上表面を露出する工程と、この露出した前記第１電極パッド上表面にボンディングワイヤをワイヤボンディングする工程と、を備えることを特徴とする半導体装置の製造方法。Forming a first interlayer insulating film on the semiconductor substrate; forming an internal wiring on the first interlayer insulating film; and forming a second interlayer insulating film on the internal wiring and on the first interlayer insulating film. A step of forming, a step of forming a first electrode pad connected to the internal wiring on the second interlayer insulating film, and a third interlayer insulating film on the first electrode pad and the second interlayer insulating film Forming a second electrode pad connected to the first electrode pad on the third interlayer insulating film, and a passivation layer on the second electrode pad and on the third interlayer insulating film. Forming an opening so as to expose at least a part of the surface of the passivation layer on the second electrode pad, applying a probe to the second electrode pad exposed in the opening, To test Removing the exposed second electrode pad and the third interlayer insulating film below the exposed second electrode pad to expose the upper surface of the first electrode pad; and And a step of wire bonding a bonding wire to the upper surface of the first electrode pad. 前記露出した第２電極パッドを除去して、前記第１電極パッド上表面を露出する工程において、前記第２電極パッド及びこの第２電極パッド下部の前記第３層間絶縁膜に対してＣＤＥ又はＲＩＥのエッチングを行なうことを特徴とする請求項６記載の半導体装置の製造方法。In the step of removing the exposed second electrode pad and exposing the upper surface of the first electrode pad, CDE or RIE is performed on the second electrode pad and the third interlayer insulating film below the second electrode pad. The method of manufacturing a semiconductor device according to claim 6 , wherein the etching is performed.
JP2001271255A 2001-09-07 2001-09-07 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3856426B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001271255A JP3856426B2 (en) 2001-09-07 2001-09-07 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001271255A JP3856426B2 (en) 2001-09-07 2001-09-07 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2003086624A JP2003086624A (en) 2003-03-20
JP3856426B2 true JP3856426B2 (en) 2006-12-13

Family

ID=19096785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001271255A Expired - Fee Related JP3856426B2 (en) 2001-09-07 2001-09-07 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3856426B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5401817B2 (en) 2008-03-25 2014-01-29 富士通セミコンダクター株式会社 Semiconductor device manufacturing method and semiconductor device

Also Published As

Publication number Publication date
JP2003086624A (en) 2003-03-20

Similar Documents

Publication Publication Date Title
JP3616444B2 (en) Semiconductor device
KR100329407B1 (en) Electrode structure of semiconductor element
US7105917B2 (en) Semiconductor device having a fuse connected to a pad and fabrication method thereof
US20060267222A1 (en) Semiconductor element and manufacturing method thereof
JP2006210438A (en) Semiconductor device and its manufacturing method
US7429795B2 (en) Bond pad structure
JP3468188B2 (en) Semiconductor device and its manufacturing method.
TWI316741B (en) Method for forming an integrated cricuit, method for forming a bonding pad in an integrated circuit and an integrated circuit structure
US20070290204A1 (en) Semiconductor structure and method for manufacturing thereof
US9941236B2 (en) Semiconductor device having wire bonding connection and method for manufacturing the same
US20060180945A1 (en) Forming a cap above a metal layer
JPH09289224A (en) Semiconductor chip, manufacturing method thereof and wire bonding method
JP3856426B2 (en) Semiconductor device and manufacturing method thereof
KR20060078864A (en) Semiconductor device and method for fabricating the same
JP3599813B2 (en) Semiconductor device
JP3395747B2 (en) Manufacturing method of semiconductor integrated circuit
US20090014717A1 (en) Test ic structure
JP2949830B2 (en) Failure analysis method for semiconductor device
KR100339414B1 (en) Forming method of pad using semiconductor power line analsis
KR20040023311A (en) Method for forming pad of semiconductor drvice
KR100481832B1 (en) Method for forming a semiconductor device and a semiconductor formed thereof
JP2002373909A (en) Semiconductor circuit device and manufacturing method therefor
KR20010017176A (en) method for manufacturing semiconductor devices
KR20030061158A (en) Semiconductor device having bonding pads and method of fabricating the same
KR20040057516A (en) Method for forming a bonding pad in semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050401

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20050428

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20050606

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060607

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060613

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060809

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20060908

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20060911

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090922

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100922

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110922

Year of fee payment: 5

LAPS Cancellation because of no payment of annual fees