KR20010017176A - method for manufacturing semiconductor devices - Google Patents
method for manufacturing semiconductor devices Download PDFInfo
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- KR20010017176A KR20010017176A KR1019990032555A KR19990032555A KR20010017176A KR 20010017176 A KR20010017176 A KR 20010017176A KR 1019990032555 A KR1019990032555 A KR 1019990032555A KR 19990032555 A KR19990032555 A KR 19990032555A KR 20010017176 A KR20010017176 A KR 20010017176A
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- interlayer insulating
- insulating film
- metal
- metal wiring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
Abstract
Description
본 발명은 다층배선의 반도체소자 제조방법에 관한 것으로, 보다 상세하게는 패드부의 금속배선 두께를 증가하여 그 하부에 위치한 층간절연막의 노출이나 균열을 방지함으로써 패키지 제품의 신뢰성을 향상하도록 한 반도체소자 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device of a multi-layered wiring, and more particularly, to manufacturing a semiconductor device to improve the reliability of a packaged product by increasing the thickness of the metal wiring of the pad part to prevent exposure or cracking of the interlayer insulating film disposed thereunder. It is about a method.
일반적으로, 외부로부터의 입력신호 및 전원을 입력하거나 출력신호를 외부로 출력하는 패드부는 주로 반도체칩의 가장자리부에 배치되고, 필요에 따라 반도체칩의 중앙부에 배치되기도 한다.In general, a pad portion for inputting an input signal and power from outside or outputting an output signal to the outside is mainly disposed at the edge of the semiconductor chip, and may be disposed at the center portion of the semiconductor chip as necessary.
종래의 패드부에서는 도 1에 도시된 바와 같이, 도시되지 않은 게이트전극과 적층형 커패시터가 형성된 실리콘기판(10) 상에 평탄화용 층간절연막(11)이 적층되고, 층간절연막(11) 상에 금속배선(13)이 배치되고, 금속배선(13)에 층간절연막(15)의 비아홀(16)을 거쳐 패드(17)가 접속되고, 패드(17)를 노출하며 층간절연막(15) 상에 보호막(19)이 적층된다. 여기서, 패드(17)와 금속배선(13)이 알루미늄으로 이루어진다.In the conventional pad part, as shown in FIG. 1, a planarization interlayer insulating film 11 is stacked on a silicon substrate 10 on which a gate electrode and a multilayer capacitor, which are not shown, are formed, and a metal wiring is formed on the interlayer insulating film 11. 13 is disposed, the pad 17 is connected to the metal wiring 13 via the via hole 16 of the interlayer insulating film 15, the pad 17 is exposed, and the protective film 19 is disposed on the interlayer insulating film 15. ) Are stacked. Here, the pad 17 and the metal wiring 13 are made of aluminum.
이와 같이 구성된 패드부에서는 다층배선의 반도체소자에서는 패드(17)가 금속배선(13)에 직접 접속하므로 이들에 의한 알루미늄 금속층 두께가 두꺼우므로 웨이퍼 테스트를 위한 프로우빙(probing) 때에 하부의 층간절연막(11)이 잘 노출되지 않고 그 결과 후속의 와이어본딩공정 때에 본딩강도의 저하가 거의 발생하지 않는다. 그러나, 다층배선이 반도체소자에서 층간절연막(11)의 평탄화를 위한 기계화학적 연마(chemical mechanical polishing) 공정을 적용하기가 불가능하다.In the pad part configured as described above, in the semiconductor device of the multi-layered wiring, since the pad 17 is directly connected to the metal wiring 13, the thickness of the aluminum metal layer due to these is thick, so that the lower interlayer insulating film is formed during probing for wafer testing. 11) is not exposed well, and as a result, the reduction in bonding strength hardly occurs in the subsequent wire bonding process. However, it is impossible for a multilayer wiring to apply a chemical mechanical polishing process for planarization of the interlayer insulating film 11 in a semiconductor device.
그래서, 최근에는 층간절연막의 평탄화에 기계화학적 연마(chemical mechanical polishing) 공정을 적용 가능한 형태의 패드부가 도 2에 도시된 바와 같이 구성되어 왔다.Therefore, in recent years, a pad portion having a form in which a chemical mechanical polishing process can be applied to planarization of an interlayer insulating film has been constructed as shown in FIG.
즉, 도시되지 않은 게이트전극과 적층형 커패시터가 형성된 실리콘기판(10) 상에 평탄화용 층간절연막(11)이 적층되고, 층간절연막(11) 상에 금속배선(13)이 배치되고, 금속배선(13)에 평탄화된 층간절연막(15)의 비아홀들(16)을 거쳐 플러그(21)가 접속되고, 패드(17)가 플러그(21) 상에 배치되며 접속되고, 패드(17)를 노출하며 층간절연막(15) 상에 보호막(19)이 적층된다. 여기서, 패드(17)와 금속배선(13)은 알루미늄으로 이루어지고, 플러그(21)가 텅스텐으로 이루어진다.That is, the planarization interlayer insulating film 11 is stacked on the silicon substrate 10 on which the gate electrode and the multilayer capacitor (not shown) are formed, and the metal wiring 13 is disposed on the interlayer insulating film 11, and the metal wiring 13 is disposed. Plug 21 is connected via via holes 16 of planar interlayer insulating film 15, pad 17 is disposed on plug 21, is connected, exposes pad 17, and interlayer insulating film The protective film 19 is laminated | stacked on the 15. Here, the pad 17 and the metal wiring 13 are made of aluminum, and the plug 21 is made of tungsten.
이와 같이 구성되는 패드부를 갖는 반도체소자의 제조방법을 도 3 내지 도 5를 참조하여 살펴보면, 먼저, 도 3을 참조하면, 도시되지 않은 게이트전극과 적층형 커패시터가 형성된 실리콘기판(10)의 중앙부(A)와 패드부(B)에 층간절연막(11)을 적층한다. 이어서, 중앙부(A)와 패드부(B)의 층간절연막(11) 상에 원하는 패턴의 금속배선(13)을 형성한다.Referring to FIGS. 3 to 5, a method of fabricating a semiconductor device having a pad part configured as described above will first be described with reference to FIG. 3. First, referring to FIG. 3, a center portion A of a silicon substrate 10 having a gate electrode and a multilayer capacitor not shown is formed. ) And the interlayer insulating film 11 are laminated on the pad portion (B). Subsequently, the metal wiring 13 of a desired pattern is formed on the interlayer insulating film 11 of the center part A and the pad part B. As shown in FIG.
도 4를 참조하면, 그런 다음, 중앙부(A)와 패드부(B)의 금속배선(13)을 포함한 층간절연막(11) 상에 층간절연막(15)을 적층하고 이를 기계화학적 연마공정을 이용하여 평탄화한다.Referring to FIG. 4, the interlayer insulating film 15 is then laminated on the interlayer insulating film 11 including the metal wiring 13 of the central portion A and the pad portion B, and then subjected to a mechanical chemical polishing process. Flatten.
이후, 사진시각공정을 이용하여 중앙부(A)와 패드부(B)의 비아홀(16)을 위한 영역의 층간절연막(15)을 그 아래의 금속배선(13)이 노출될 때까지 식각하여 중앙부(A)와 패드부(B)의 금속배선(13) 상에 각각 층간절연막(15)의 비아홀(16)을 형성한다.Subsequently, the interlayer insulating layer 15 in the region for the via hole 16 of the center portion A and the pad portion B is etched by using a photovisual process until the metal wiring 13 underneath is exposed. Via holes 16 of the interlayer insulating film 15 are formed on the metal lines 13 of A) and pad portion B, respectively.
이어서, 중앙부(A)와 패드부(B)의 비아홀(16)을 완전히 채워질 정도의 두꺼운 두께로 텅스텐을 층간절연막(15)과 금속배선(13) 상에 적층하고 나서 기계화학연마공정을 이용하여 비아홀(16) 외측의 층간절연막(15) 상에 위치한 텅스텐을 전부 제거하고 비아홀(16) 내에만 텅스텐 플러그(21)를 남긴다.Subsequently, tungsten is deposited on the interlayer insulating film 15 and the metal wiring 13 to a thickness thick enough to completely fill the via hole 16 of the center portion A and the pad portion B, and then using a mechanical chemical polishing process. All tungsten on the interlayer insulating film 15 outside the via hole 16 is removed and only the tungsten plug 21 is left in the via hole 16.
도 5를 참조하면, 이후, 중앙부(A)와 패드부(B)의 텅스텐 플러그(21)를 포함한 층간절연막(15) 상에 알루미늄 재질의 금속을 적층하고 이를 사진식각공정에 의해 중앙부(A)와 패드부(B)의 플러그(21)에 각각 접속하는 금속배선(17a)과 패드(17)의 패턴으로 형성한다.Referring to FIG. 5, after that, an aluminum metal is laminated on the interlayer insulating layer 15 including the tungsten plug 21 of the center portion A and the pad portion B, and the center portion A is formed by a photolithography process. And a pattern of metal wiring 17a and pad 17 connected to the plug 21 of the pad portion B, respectively.
마지막으로, 패드(17)와 금속배선(17a)을 포함한 층간절연막(15) 상에 보호막(19)을 적층하고 패드(17)와 본딩와이어(도시 안됨)의 와이어본딩을 위한 개구부를 패드(17) 상의 보호막(19)에 형성한다.Finally, the passivation layer 19 is laminated on the interlayer insulating layer 15 including the pad 17 and the metal wiring 17a, and the opening 17 for wire bonding the pad 17 and the bonding wire (not shown) is formed. It is formed in the protective film 19 on ().
그러나, 이와 같이 구성된 패드부에서는 프로우빙 때에 패드를 구성하는 금속은 단층으로서 그 두께가 얇아 패드 하부의 층간절연막이 노출되기 쉽다. 이로써, 후속의 와이어본딩공정에서 본딩된 와이어가 패드의 표면 또는 층간절연막과 패드와의 접착강도 부족으로 와이어 인장 테스트 때에 이격되는 불량현상이 발생하거나, 와이어본딩될 때의 본딩충격으로 층간절연막 및 실리콘기판까지 균열이 발생하는 불량현상이 다발한다. 또한, 웨이퍼 테스트의 프로우빙 때에 프로우빙 깊이가 깊어지거나 여러번의 반복적인 프로우빙에 의해 패드 하부의 텅스텐 플러그나 층간절연막이 노출되므로 후속의 와이어본딩 때에 텅스텐 플러그나 층간절연막의 노출에 의한 본딩성이 취약해지는 불량현상이 다발한다. 이러한 불량현상들은 결국 반도체소자의 패키지 특성에 악영향을 주고 신뢰성을 저하를 가져온다.However, in the pad portion configured as described above, the metal constituting the pad at the time of probing is a single layer, and its thickness is thin so that the interlayer insulating film under the pad is easily exposed. As a result, in the subsequent wire bonding process, a defect occurs in which the bonded wire is spaced apart during the wire tension test due to the lack of adhesive strength between the surface of the pad or the interlayer insulating film and the pad, or the interlayer insulating film and the silicon due to the bonding shock when the wire is bonded. There are many defects that cause cracks to the substrate. In addition, since the depth of probing is increased during probing of wafer test or the repetitive probing of several times, the tungsten plug or interlayer insulating film under the pad is exposed. There are many defects that become vulnerable. These defects adversely affect the package characteristics of the semiconductor device and reduce the reliability.
따라서, 본 발명의 목적은 패드부에서의 층간절연막의 노출이나 균열을 방지하여 패키지 제품의 신뢰성을 향상하도록 한 반도체소자의 제조방법을 제공하는데 있다.Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device which improves the reliability of a package product by preventing exposure or cracking of the interlayer insulating film in the pad portion.
도 1은 종래 기술에 의한 패드부 구조를 나타낸 단면도.1 is a cross-sectional view showing a pad portion structure according to the prior art.
도 2는 종래 기술에 의한 다른 패드부 구조를 나타낸 단면도.Figure 2 is a cross-sectional view showing another pad portion structure according to the prior art.
도 3 내지 도 5는 도 2의 패드부 구조를 제조하는 방법을 나타낸 공정도.3 to 5 are process drawings showing a method of manufacturing the pad portion structure of FIG.
도 6 내지 도 8은 본 발명에 의한 반도체소자 제조방법을 나타낸 공정도.6 to 8 is a process chart showing a semiconductor device manufacturing method according to the present invention.
이와 같은 목적을 달성하기 위한 본 발명에 의한 반도체소자의 제조방법은The semiconductor device manufacturing method according to the present invention for achieving the above object is
반도체기판의 중앙부와 패드부에 금속배선을 각각 형성하는 단계;Forming metal wires on a center portion and a pad portion of the semiconductor substrate, respectively;
상기 중앙부와 패드부 상에 층간절연막을 적층하는 단계;Stacking an interlayer insulating film on the center portion and the pad portion;
상기 중앙부의 금속배선에 접속하도록 층간절연막의 비아홀 내에만 고융점 금속 재질의 플러그를 형성하는 단계; 그리고Forming a plug of a high melting point metal material only in the via hole of the interlayer insulating film so as to be connected to the metal wiring in the central portion; And
상기 패드부의 금속배선에 상기 층간절연막의 개구부를 거쳐 접속하는 패드를 형성함과 아울러 상기 플러그에 접속하는 금속배선을 각각 형성하는 단계를 포함하는 것을 특징으로 한다.And forming metal pads connected to the plugs through metal openings of the interlayer insulating layer in the metal wires of the pad unit.
바람직하게는 상기 패드를 형성함과 아울러 상기 플러그에 접속하는 금속배선을 각각 형성하는 단계는Preferably, the forming of the pads and the forming of the metal wires connected to the plugs may be performed.
상기 패드부의 금속배선을 노출하기 위한 상기 층간절연막의 개구부를 형성하는 단계;Forming an opening of the interlayer insulating film for exposing the metal wiring of the pad part;
상기 개구부 내의 금속배선과 상기 플러그에 접속하도록 상기 층간절연막의 전면에 금속을 적층하는 단계; 그리고Stacking a metal on the entire surface of the interlayer insulating film so as to be connected to the metal wiring in the opening and the plug; And
상기 사진식각공정을 이용하여 상기 금속을 상기 개구부 내의 금속배선에 접속하는 패드와, 상기 플러그에 접속하는 금속배선의 패턴으로 형성하는 단계를 포함한다.Using the photolithography process to form the metal in a pattern of a pad connecting the metal wiring in the opening and a metal wiring connecting the plug.
또한, 상기 패드가 연성 재질의 알루미늄과 구리 중 어느 하나로 이루어질 수 있다.In addition, the pad may be made of any one of aluminum and copper of the flexible material.
이하, 본 발명에 의한 반도체소자의 제조방법을 첨부된 도면을 참조하여 상세히 설명하기로 한다. 종래의 부분과 동일 구성 및 동일 작용의 부분에는 동일 부호를 부여한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. The same code | symbol is attached | subjected to the part of the same structure and the same action as the conventional part.
도 6 내지 도 8은 본 발명에 의한 반도체소자의 제조방법을 나타낸 단면공정도이다.6 to 8 are cross-sectional process diagrams illustrating a method of manufacturing a semiconductor device according to the present invention.
도 6을 참조하면, 먼저, 도시되지 않은 게이트전극과 적층형 커패시터가 형성된 반도체기판, 예를 들어 실리콘기판(10)의 중앙부(A)와 패드부(B)에 층간절연막(11)을 적층한다.Referring to FIG. 6, first, an interlayer insulating film 11 is laminated on a central portion A and a pad portion B of a semiconductor substrate, for example, a silicon substrate 10 on which a gate electrode and a multilayer capacitor, which are not shown, are formed.
그런 다음, 중앙부(A)와 패드부(B)의 층간절연막(11) 전면에 알루미늄이나 구리와 같은 연성 재질의 금속배선(13)을 형성하고, 중앙부(A)와 패드부(B)의 금속배선(13)을 포함한 층간절연막(11) 상에 층간절연막(15)을 적층하고 이를 기계화학적 연마공정을 이용하여 평탄화한다.Then, a metal wiring 13 of a flexible material such as aluminum or copper is formed on the entire surface of the interlayer insulating film 11 between the center portion A and the pad portion B, and the metal portion of the center portion A and the pad portion B is formed. The interlayer insulating film 15 is laminated on the interlayer insulating film 11 including the wiring 13 and planarized using a mechanical chemical polishing process.
이후, 사진식각공정을 이용하여 중앙부(A)의 비아홀(16)을 위한 영역의 층간절연막(15)을 그 아래의 금속배선(13)이 노출될 때까지 식각하여 중앙부(A)의 금속배선(13) 상에 층간절연막(15)의 비아홀(16)을 형성한다. 이때, 패드부(B)의 금속배선(13) 상에는 비아홀(16)을 전혀 형성하지 않는다.Subsequently, the interlayer insulating layer 15 in the region for the via hole 16 of the central portion A is etched by using a photolithography process until the metal wiring 13 below it is exposed to expose the metallic wiring of the central portion A ( The via hole 16 of the interlayer insulating film 15 is formed on the 13. At this time, no via hole 16 is formed on the metal wiring 13 of the pad portion B. FIG.
그 다음, 비아홀(16)을 완전히 채울 정도의 두꺼운 두께로 고융점 금속, 예를 들어 텅스텐을 층간절연막(15)과 금속배선(13) 상에 적층하고 나서 기계화학적 연마공정을 이용하여 비아홀(16) 외측의 층간절연막(15) 상에 위치한 텅스텐을 전부 제거하고 비아홀(16) 내에만 텅스텐 플러그(21)를 남긴다.Next, a high melting point metal, for example, tungsten, is deposited on the interlayer insulating film 15 and the metal wiring 13 to a thickness thick enough to completely fill the via hole 16, and then the via hole 16 is formed using a mechanical chemical polishing process. ) All of the tungsten on the interlayer insulating film 15 on the outside is removed and the tungsten plug 21 is left only in the via hole 16.
도 7을 참조하면, 이후, 사진식각공정을 이용하여 패드부(B)의 개구부(22)를 위한 영역의 층간절연막(15)을 그 아래의 금속배선(13)이 노출될 때까지 식각하여 패드부(B)의 금속배선(13) 상의 층간절연막(15)에 개구부(22)를 형성한다.Referring to FIG. 7, by using a photolithography process, the interlayer insulating film 15 in the region for the opening 22 of the pad part B is etched until the metal wiring 13 below it is exposed. Openings 22 are formed in the interlayer insulating film 15 on the metal wiring 13 in the portion (B).
이어서, 개구부(22)를 완전히 채울 정도의 두꺼운 두께로 알루미늄이나 구리와 같은 연성 재질의 금속을 플러그(21)와, 패드부(B)의 금속배선(13)을 포함한 층간절연막(15) 상에 적층하고 이를 사진식각공정에 의해 텅스텐 플러그(21)에 접속하는 금속배선(23a)과, 패드부(B)의 금속배선(13)에 접속하는 패드(23)의 패턴으로 형성한다.Subsequently, a flexible metal such as aluminum or copper is deposited on the interlayer insulating film 15 including the plug 21 and the metal wiring 13 of the pad part B to a thickness thick enough to completely fill the opening 22. It is laminated and formed into a pattern of the metal wiring 23a which connects to the tungsten plug 21 by the photolithography process, and the pad 23 which connects to the metal wiring 13 of the pad part B. As shown in FIG.
도 8을 참조하면, 마지막으로, 패드(23)와 금속배선(23a)을 포함한 층간절연막(15) 상에 보호막(19)을 적층하고 패드(23)와 본딩와이어(도시 안됨)의 와이어본딩을 위한 개구부를 패드(23) 상의 보호막(19)에 형성한다.Referring to FIG. 8, finally, a protective film 19 is laminated on the interlayer insulating film 15 including the pad 23 and the metal wiring 23a, and wire bonding of the pad 23 and a bonding wire (not shown) is performed. Openings are formed in the protective film 19 on the pad 23.
따라서, 본 발명은 패드와 그 아래의 금속배선을 직접 접속하여 패드부의 최상층 금속두께를 두껍게 형성함으로써 웨이퍼테스트를 위한 프로우빙 때에 발생하던 층간절연막의 노출을 방지하고 나아가 와이어본딩공정에서의 공정불량을 방지할 수 있다.Therefore, the present invention directly connects the pad and the metal wiring below to form the uppermost metal thickness of the pad part, thereby preventing the exposure of the interlayer insulating film generated during probing for wafer testing and further reducing the process defect in the wire bonding process. You can prevent it.
한편, 본 발명의 도면에서 도시되지 않았으나 다층의 금속배선이 비아홀을 거쳐 서로 접속되어 있을 수 있다.Meanwhile, although not shown in the drawings of the present invention, the multi-layered metal wires may be connected to each other via via holes.
이상에서 살펴본 바와 같이, 본 발명에 의하면, 기판의 중앙부와 패드부에 각각 금속배선을 형성하고, 중앙부와 패드부의 금속배선을 포함한 기판의 전면에 층간절연막을 적층, 평탄화하고, 중앙부의 금속배선 상에 위치한 층간절연막의 비아홀에만 텅스텐 플러그를 형성하고, 패드부의 금속배선 상에 위치한 층간절연막의 비아홀에 패드를 형성함과 아울러 텅스텐 플러그에 접속하는 금속배선을 형성한다.As described above, according to the present invention, a metal wiring is formed in the center portion and the pad portion of the substrate, and an interlayer insulating film is laminated and planarized on the entire surface of the substrate including the metal portion in the center portion and the pad portion. Tungsten plugs are formed only in the via holes of the interlayer insulating film located at the pads, and pads are formed in the via holes of the interlayer insulating film located on the metal wiring of the pad portion, and metal wires connected to the tungsten plugs are formed.
따라서, 본 발명은 패드용 금속이 그 하부 금속배선에 직접 접속하므로 이들금속의 총 두께가 두꺼워지는데 이는 포로우빙에 의한 층간절연막의 노출이나 균열을 방지하고 나아가 와이어본딩공정에서의 불량현상을 방지하여 결국 패키지 제품의 신뢰성을 향상한다.Therefore, in the present invention, since the pad metal is directly connected to the lower metal wiring, the total thickness of these metals becomes thick, which prevents the exposure or cracking of the interlayer insulating film due to the poring and further prevents the defect phenomenon in the wire bonding process. This improves the reliability of packaged products.
한편, 본 발명은 도시된 도면과 상세한 설명에 기술된 내용에 한정하지 않으며 본 발명의 사상을 벗어나지 않는 범위 내에서 다양한 형태의 변형도 가능함은 이 분야에 통상의 지식을 가진 자에게는 자명한 사실이다.On the other hand, the present invention is not limited to the contents described in the drawings and detailed description, it is obvious to those skilled in the art that various modifications can be made without departing from the spirit of the invention. .
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990032555A KR20010017176A (en) | 1999-08-09 | 1999-08-09 | method for manufacturing semiconductor devices |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990032555A KR20010017176A (en) | 1999-08-09 | 1999-08-09 | method for manufacturing semiconductor devices |
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| KR20010017176A true KR20010017176A (en) | 2001-03-05 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100763709B1 (en) * | 2005-12-28 | 2007-10-04 | 동부일렉트로닉스 주식회사 | Method for forming pad of semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100763709B1 (en) * | 2005-12-28 | 2007-10-04 | 동부일렉트로닉스 주식회사 | Method for forming pad of semiconductor device |
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