JP3049813B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to an interlayer insulating film of a multilayer wiring.

[0002]

2. Description of the Related Art A conventional semiconductor integrated circuit, for example, a gate array type integrated circuit, is divided into products having various functions by forming wirings. The production method of stocking with wiring is adopted. In the case of the conventional structure, even if defective stock is mixed in the stock, it is not possible to judge the quality of the stock until the end of the wiring process.

FIG. 3 is a sectional view showing an example of a conventional semiconductor integrated circuit.

As shown in FIG. 3, a high-concentration N-type buried layer 2 is selectively formed on a P-type silicon substrate 1, and the N-type buried layer 2 is formed.
Is formed by epitaxial growth of the N-type low concentration layer 3 on the surface containing. Next, an N-type low-concentration layer 3 is selectively oxidized to provide an element isolation layer 4 reaching the P-type silicon substrate 1 to divide an element formation region, and a silicon oxide film 5 is formed on the surface of the element formation region.
Is provided. Next, a P-type base region 6 is formed in the element formation region.
N-type emitter region 7 and N-type collector extraction region 8
To form an element (bipolar transistor).
Next, a contact hole is provided in the silicon oxide film 5 on the element, and a high-melting point metal film for preventing alloy spikes in a later step is provided on the surface including the contact hole and is patterned to connect to the element in the opening part; An element electrode 9 extending around the opening is formed. Next, a first layer wiring 10 is selectively formed by connecting to each of the device electrodes 9, and a silicon oxide film 11 is formed as an interlayer insulating film on the surface including the wiring 10. Next, an opening is formed in the silicon oxide film 11, and a second-layer wiring 12 connected to the wiring 10 in the opening is formed to form a logic circuit. Next, a silicon nitride film 1 for surface protection
3 is formed on the entire surface.

Here, a silicon nitride film or a silicon oxide film is mainly used as an interlayer insulating film, and usually a silicon oxide film is often used to reduce parasitic capacitance.
This silicon oxide film has the same properties as the silicon oxide film formed on the semiconductor substrate. In addition to the aluminum layer, an aluminum layer containing silicon or copper is used for the wiring. However, basically, the aluminum layer is mainly used, and a gold layer or a tungsten layer is used for some wirings.

The wiring formed on the semiconductor integrated circuit is formed with a wiring width of 2 to 3 μm and a wiring interval of 2 to 3 μm, and the element size is also large. At the time of manufacturing, the characteristics of the elements formed on the semiconductor substrate are monitored by the characteristic check elements formed in the wafer, and the characteristics are monitored by the measuring elements housed in the wafer even during the wiring process. Has been checked. In recent years, the scale of integrated circuits has become larger and larger, the wiring width and the wiring interval are about to fall below 1 μm, and the element size is also becoming finer.

[0007]

In a conventional semiconductor integrated circuit, the production yield in the wiring forming step is reduced due to the miniaturization and large scale of the elements, and the defective wiring is reproduced once the wiring is formed. If an attempt is made to remove the interlayer insulating film, there is a problem that the insulating film on the surface of the semiconductor substrate, which is the same material, is also removed, and a defective product in the wiring process cannot be reproduced.

[0008]

A semiconductor integrated circuit according to the present invention comprises a first insulating film provided on an element region provided on a semiconductor substrate, and a contact hole provided in the first insulating film.
And providing the contact hole and the contact hole so as to extend on the first insulating film.
An element electrode to be connected, a second insulating film provided on a surface including the element electrode, an opening provided in the second insulating film on the element electrode, and an opening provided in an upper layer of the element electrode;
A wiring connecting to the element electrode of the portion, and a table including the wiring
An interlayer insulating film provided on a surface, wherein the device electrode is
A second etching resistance, which is different from the etching resistance of the line.
The edge film has an etching resistance different from that of the interlayer insulating film.
Then, when performing the reproduction of the wiring, the wiring and the
When removing the interlayer insulating film, the device electrode and the second
Is used as an etching stopper.

[0009]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention.

As shown in FIG. 1, an N-type buried layer 2 and an N-type low-concentration layer 3 are provided on a P-type silicon substrate 1 by the same process as in the conventional example. And a base region 6, an emitter region 7, and a collector lead-out region 8 are provided in the element formation region, and a contact opening is provided in the silicon oxide film 5 provided on the element formation region. Next, a refractory metal layer such as titanium or platinum is deposited and patterned on the surface including the opening, and the device electrode 9 is brought into contact with each of the base region 6, the emitter region 7 and the collector extraction region 8 of the opening. To form Next, a polyimide-based resin film 14 is formed on the surface including the element electrode 9 and selectively opened to expose the element electrode 9. Next, an aluminum layer is deposited and patterned on the surface of the polyimide resin film 14 including the element electrode 9 and the wiring 10 is connected to the element.
To form Next, a silicon oxide film 11 is provided as an interlayer insulating film on the surface including the wiring 10, and a wiring 12 connected to the wiring 10 through a contact opening provided in the silicon oxide film 11 is formed on the silicon oxide film 11. Form. next,
A surface protection film made of a silicon nitride film 13 is formed on the surface including the wiring 12 to form a semiconductor integrated circuit.

Here, a defect occurs in the wiring forming step, and in order to regenerate the wirings 12 and 10, the silicon nitride film 13 and the
When the silicon oxide film 11 and the wirings 12 and 10 are removed with an etchant, the polyimide resin film 14 and the device electrode 9 function as an etching stopper to protect the silicon oxide film 5 and the surface of the device. Becomes possible. Therefore, the yield in the wiring forming process can be improved.

FIG. 2 is a sectional view of a semiconductor chip showing a second embodiment of the present invention.

As shown in FIG. 2, an aluminum layer 15 is deposited to a thickness of 0.3 to 0.4 μm on the surface including the device electrode 9 and selectively anodized to form an aluminum layer 15 other than on the device electrode 9. Is changed to an alumina layer 16, an insulating film is formed, and a wiring 10 connected to the element electrode 9 via the aluminum layer 5 is provided. , The alumina layer 16 and the device electrode 9 function as an etching stopper.

Here, in the first and second embodiments, it is possible to regenerate a defective wafer caused by a defect in the wiring forming step. Can not. However, if an aluminum wiring for connecting all the transistors in parallel is formed in advance and the characteristics of all the transistors are inspected, then the aluminum wiring for inspection is removed, and a method of forming the wiring only on a good wafer is adopted. It is also possible to further increase the efficiency of the wiring forming step including the reprocessing of the step.

[0016]

As described above, according to the present invention, a device electrode having an etching resistance different from that of a wiring provided in an upper layer and a second insulating film having an etching resistance different from the first insulating film provided on an element formation region are provided. Providing such an effect has the effect of enabling wiring to be regenerated for a wafer having a defect in the wiring forming step.

In addition, a gate array type integrated circuit, which is often used in recent years, is divided into products having various functions by a wiring forming process, so that a first-layer aluminum wiring is provided on a semiconductor wafer or a surface before wiring is applied. However, conventionally, even if 30% of defective products are mixed in the stock, it is not possible to determine the quality until the end of the wiring forming process. When the present invention is adopted, it is also possible to try a wafer with a predetermined check wiring pattern in advance and to remove a defective wafer, and selectively feed only a wafer having good characteristics to the wiring process. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor chip showing a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor chip showing an example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 Buried layer 3 N-type low concentration layer 4 Element isolation layer 5 Silicon oxide film 6 Base region 7 Emitter region 8 Collector extraction region 9 Element electrode 10, 12 Wiring 13 Silicon nitride film 14 Polyimide resin film 15 Aluminum layer 16 Alumina layer

Claims (1)

(57) [Claims] [1 claim: a first insulating film provided on the element region provided on the semiconductor substrate, provided on the first insulating film contactor
A contact hole , the contact hole and the contact hole being provided on the first insulating film so as to extend therethrough;
An element electrode connected to the element region; a second insulating film provided on a surface including the element electrode; an opening provided in the second insulating film on the element electrode; and an upper layer provided on the element electrode. ,
A wiring connected to the element electrode in the opening, and the wiring
The device electrode comprising an interlayer insulating film provided on a surface including
Has an etching resistance different from that of the wiring, and
The second insulating film is etched differently from the interlayer insulating film.
When the wiring is regenerated, the wiring and
And removing the interlayer insulating film, the device electrode and
A semiconductor integrated circuit, wherein the second insulating film is used as an etching stopper .