JP3135968B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit having a MIS capacitor and a plurality of circuit elements connected to the MIS capacitor in different regions of a semiconductor substrate. The present invention relates to a technique which is effective when applied to a method for manufacturing an apparatus.

[0002]

2. Description of the Related Art An MIS is provided in different regions of a semiconductor substrate.
A semiconductor integrated circuit device having a capacitor and a bipolar transistor, that is, a so-called bipolar linear IC is used.

The MIS capacitor is composed of a lower electrode formed of a semiconductor region and an upper electrode provided on the lower electrode via a dielectric film. The semiconductor region forming the lower electrode is provided on a main surface of the semiconductor substrate. An extraction electrode is connected to the lower electrode. This lead-out electrode is formed in the first-layer wiring forming step. This extraction electrode is made of, for example, an aluminum alloy film to which silicon is added.
The dielectric film is provided on a main surface of a semiconductor substrate.
This dielectric film is made of, for example, a silicon nitride film. The upper electrode is, similarly to the extraction electrode, a first electrode.
It is composed of an aluminum alloy film formed in the wiring forming step of the layer.

[0004] Electrodes are respectively connected to semiconductor regions constituting each of the emitter region, base region and collector region of the bipolar transistor. These electrodes are composed of an aluminum alloy film formed in the same step as the upper electrode and the extraction electrode.

The distance between each of the upper electrode and the extraction electrode of the MIS capacitor and each electrode of the bipolar transistor is:
The wiring is connected using a first-layer wiring and a second-layer wiring. The second-layer wiring is made of, for example, an aluminum alloy film, similarly to the first-layer wiring.

In the semiconductor integrated circuit device configured as described above, the dielectric breakdown of the dielectric film of the MIS capacitor with time (TDD) is performed.
B: T ime D ependent D ielectric B reakdown) becomes a problem. Therefore, it is necessary to detect a dielectric film that may lead to dielectric breakdown with time. As a method of detecting such a dielectric film, QCTEG within step (Q uali
The ty C heck T est E lementary G roup), checks the chip components at several points per semiconductor wafer, and finally there is a method to remove the initial failure in aging product.

[0007]

However, the present inventor has found the following problems as a result of studying the above prior art.

Aging is performed after connecting the MIS capacitor and the bipolar transistor, so that a voltage higher than the maximum rating of the bipolar transistor cannot be applied. Therefore, even if aging is performed, some of the dielectric films that may become an initial failure are not destroyed, and there is a problem that an initial failure occurs.

Therefore, although not a known technique, Japanese Patent Application No.
As described in JP-A-252286, prior to the first-layer wiring forming step, an upper electrode of the MIS capacitor and an extraction electrode are formed, and an inspection pad is formed.
A method has been proposed in which a connection is made between the inspection pad and the upper electrode, and between the inspection pad and the extraction electrode, and an overload is applied to the dielectric film via the inspection pad. By overloading the dielectric film, the dielectric film that may become an initial failure is destroyed. After that, the broken dielectric film is detected by inspecting the dielectric film using the inspection pad. Next, the upper electrode, the extraction electrode, the inspection pad, the connection between the upper electrode and the inspection pad, and the connection between the extraction electrode and the inspection pad are removed by etching. Thereafter, there has been proposed a conventional method of forming each of the first-layer wiring and the second-layer wiring. But,
In the process of removing the wiring of the same layer as the inspection pad,
Since the surface of the dielectric film of the MIS capacitor is also etched,
There is a problem that the film quality of the dielectric film is deteriorated and the dielectric strength of the dielectric film is reduced.

As another method, which is not a known technique, as described in Japanese Patent Application No. 3-333601, a semiconductor integrated circuit for connecting a MIS capacitor and a MISFET with a single-layer wiring is disclosed. In the method of manufacturing a circuit device, a wiring layer forming step is divided into two steps, and an upper electrode, a lead-out electrode, and a test pad of a MIS capacitor are formed in a first wiring forming step, and an upper electrode and a test pad are formed. A method has been proposed in which a connection is made between the test pad and the lead-out electrode and the test pad, and an overload is applied to the dielectric film via the test pad. Overloading the dielectric film destroys the dielectric film, which can lead to initial failure. Next, after detecting a dielectric film that may cause an initial failure, the MIS capacitor and the MISF
Connect to ET. However, in this case, there is a problem that the number of steps increases because the number of steps of forming the wiring increases substantially once.

An object of the present invention is to provide a technique capable of improving the yield in a method of manufacturing a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of improving reliability in the method of manufacturing a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of reducing the number of steps in the method of manufacturing a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) An MIS capacitor in which an upper electrode is provided on a lower electrode composed of a semiconductor region via a dielectric film in each of different regions of the same semiconductor substrate, and a plurality of MIS capacitors connected to the MIS capacitor. Each of the circuit elements of
Each of the distance between the IS capacitor and the circuit element and between the circuit elements is 2
In a method for manufacturing a semiconductor integrated circuit device connected by wiring of layers, M
Forming the lower electrode of the IS capacitor, the dielectric film, and each of the plurality of circuit elements;
Forming an upper electrode of S capacitance, forming a connection between the upper electrode and a first inspection pad, a connection between the lower electrode and a second inspection pad, and a part of a connection between the plurality of circuit elements. Performing an overload on the dielectric film of the MIS capacitor by applying a predetermined voltage to the first and second test pads; and an upper electrode of the MIS capacitor and the first test pad. A connection between the MIS capacitor and a plurality of circuit elements, and a step of disconnecting each of the connection between the lower electrode and the second inspection pad. Forming the remaining connection between the circuit elements.

(2) The upper electrode of the MIS capacitor is
And a part of the connection between the upper electrode and the first inspection pad, the connection between the lower electrode and the second inspection pad, and a part of the connection between a plurality of circuit elements. The wiring of the second layer above the wiring of the layer, the connection between the MIS capacitor and the plurality of circuit elements, and the rest of the connection between the plurality of circuit elements are respectively formed in the third layer above the wiring of the second layer. It is formed by wiring.

[0018]

According to the above-mentioned means (1) or (2), the step of removing the wiring of the first layer formed on the dielectric film can be eliminated, so that the dielectric strength of the dielectric film is reduced by etching. Can be prevented. Thereby, the yield of the semiconductor integrated circuit device can be improved. Further, reliability can be improved.

Also, since the connection between the upper electrode and the inspection pad and the connection between the lower electrode and the inspection pad are formed by also using the step of forming the first layer wiring or the second layer wiring, The number can be reduced.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and a repeated description thereof will be omitted.

Embodiment 1 A method for manufacturing a semiconductor integrated circuit device according to Embodiment 1 of the present invention will be described with reference to FIG. 1 (flow chart).

First, an n-type impurity is introduced into the main surface of the p − type semiconductor substrate 1. Thereafter, an n − -type epitaxial layer 3 is formed on the main surface of the p − -type semiconductor substrate 1. In this step, a buried n + type semiconductor region 2 is formed below the main surface of the p − type semiconductor substrate 1 and the n − type epitaxial layer 3. The n − -type epitaxial layer 3 forms a collector region of the bipolar transistor Tr and a lower electrode of the MIS capacitor C.

Next, a p-type impurity is introduced into the inactive region of the n − -type epitaxial layer 3 to
To form This p − type semiconductor region 4 forms an isolation region. Thereafter, each of the p-type semiconductor region 5 forming the base region and the n-type semiconductor region 6 forming the emitter region of the bipolar transistor Tr is formed on the main surface of the n − -type epitaxial layer 3 in the active region.

Next, an insulating film 7 is formed on the main surface of the n − -type epitaxial layer 3. Thereafter, an opening is formed in the insulating film 7 in a region where the MIS capacitor C is formed.

Next, the dielectric film 8 of the MIS capacitor C is formed <101>. The dielectric film 8 is formed, for example, by depositing a silicon nitride film and then patterning the silicon nitride film by photolithography and etching. Thereafter, an opening is formed in the insulating film 7 on the lower electrode of the MIS capacitor C and on each operation region of the bipolar transistor Tr.

Next, a conductive film, for example, an aluminum alloy film to which silicon is added is deposited. This aluminum alloy film forms the first layer wiring. Thereafter, the aluminum alloy film is patterned by photolithography and etching. As a result of this patterning step, as shown in FIG. 2 (a cross-sectional view of a main part of a part of the process) and FIG. 3 (a plan view of a main part of a part of the process), an upper electrode 10U and a lower electrode , An emitter electrode 10E, a base electrode 10B, and a collector electrode 10C of the bipolar transistor are formed. In FIG. 3, mainly the MIS capacitance C
Since the formation region is illustrated, the bipolar transistor Tr is not illustrated. At the same time, a connection 11A between the first inspection pad 12A and the upper electrode 10U and a connection 11B between the second inspection pad 12B and the extraction electrode 10L (lower electrode) are formed. At the same time,
As shown in FIG. 3, the electrodes 10 of the circuit element other than the MIS capacitor C and a part of the connection 11 between the electrodes 10 are formed.
02>.

Next, the first and second inspection pads 1
For example, a voltage of about 80 V is applied to each of 2A and 12B,
Apply for about 1 second to overload dielectric film 8 <103
>. In this step, the quality of the dielectric film 8 is poor,
Since the one having a low withstand voltage is destroyed, the dielectric film 8 which may lead to the initial failure is destroyed.

Next, the first and second inspection pads 1
A probe needle of a wafer prober is pressed against each of 2A and 12B to detect a broken dielectric film 8 <104.
>. For example, laser marking is performed on the semiconductor chip having the detected defective MIS capacitance C. Also,
The position of a semiconductor chip having a defective MIS capacity may be stored in a storage medium.

Next, as shown in FIG. 4 (a cross-sectional view of a main part showing a part of the process) and FIG. 5 (a plan view of a main part showing a part of the process), for example, a photoresist film 15 (FIG. (Not shown) as a mask, the connection 11A between the upper electrode 10U and the first inspection pad 12A, and the extraction electrode 10
The connection 11B between L (lower electrode) and the second inspection pad 12B is etched to be disconnected <105>. Alternatively, the connections 11A and 11B may be disconnected by a laser. In addition, in order to make it non-connection, connection 11A, 11B
6 is removed, as shown in FIG. 6 (a modification of the manufacturing method of the first embodiment and a plan view of a main part of a part of the process).
Substantially, electrodes 10U and 10L, inspection pads 12A and 12
Only the portion B may be left.

Next, an interlayer insulating film 17 is formed. After that, the electrode 10 (10U, 1
(0L, 10E, 10B, 10C) are formed.

Next, a conductive film such as an aluminum alloy film is deposited. This aluminum alloy film forms the second-layer wiring. Thereafter, the aluminum alloy film is patterned by a photolithography technique and an etching technique to form a second-layer wiring 18. This second layer wiring 1
Reference numeral 8 denotes each electrode 10 of the bipolar transistor Tr.
E, 10B, 10C or other circuit element electrodes 10 and M
Connection with the electrodes 10U and 10L of the IS capacitor C, between the electrodes 10E, 10B and 10C of the bipolar transistor Tr, and the electrodes 10E, 10B and 10C of the bipolar transistor.
And the rest of the connection between the electrode and the electrode 10 of another circuit element is formed <
106>.

Next, a surface protection film (not shown) is formed on the second-layer wiring 18, thereby completing the semiconductor integrated circuit device of the first embodiment.

As described above, in the method of manufacturing a semiconductor integrated circuit device according to the first embodiment, the n − -type epitaxial layer 3 is provided in each of the mutually different regions of the p − -type semiconductor substrate 1.
MIS capacitor C provided with an upper electrode 10U via a dielectric film 8 on a lower electrode composed of: a circuit element (for example, a bipolar transistor Tr) connected to the MIS capacitor C
Are formed, and each of the MIS capacitor C and the circuit element and between the circuit elements are connected by two-layer wirings (10, 18). Forming a lower electrode (n − -type epitaxial layer 3) of the MIS capacitor C, a dielectric film 8, and a circuit element (for example, a bipolar transistor Tr) in each of the mutually different regions; In the wiring 10 of
While forming the upper electrode 10U of the MIS capacitor C,
The connection 11A between the upper electrode 10U and the first inspection pad 12A, and the extraction electrode 10 connected to the lower electrode
Forming a part of a connection 11B between the L and the second inspection pad 12B and a connection 11 between the circuit elements;
Applying a predetermined voltage to the second inspection pads 12A and 12B to overload the dielectric film 8 of the MIS capacitor C; and an upper electrode 10U of the MIS capacitor C and the first inspection pad. 11A, the lead electrode 10L connected to the lower electrode, and the second inspection pad 12
B: a step of disconnecting each of the connections 11B to B, and a step of forming a connection between the MIS capacitor C and the circuit element and a remaining connection between the circuit elements with the wiring 18 of the second layer. . According to this configuration, since the step of peeling off the upper electrode 10U formed on the dielectric film 8 can be eliminated, a decrease in the dielectric strength of the dielectric film 8 due to etching can be prevented. Thereby, the yield of the semiconductor integrated circuit device can be improved. Further, reliability can be improved.

The upper electrode 10U and the first inspection pad 12A are also used for the process of forming the first layer wiring 10.
11A, and a connection 11B between the extraction electrode 10L connected to the lower electrode and the second inspection pad 12B.
Is formed, the number of steps can be reduced.

Although FIG. 3 shows an example in which the extraction electrode 10L connected to the lower electrode of the MIS capacitor C and the second inspection pad 12B are connected by the connection 11B, a plurality of MIS capacitors C are connected. When the n − -type epitaxial layers 3 constituting the lower electrode of the capacitor C are electrically connected to each other, FIG. As shown in (plan view), a common lead-out electrode 10LC is formed on the lower electrodes of the plurality of MIS capacitors C, and the common lead-out electrode 10LC and the second inspection pad 12B are connected by a connection 11B. You may.

[Embodiment 2] FIGS. 9 to 12 are cross-sectional views showing a part of a process of a semiconductor integrated circuit device according to a second embodiment of the present invention. This will be described with reference to FIG.

First, the steps up to the step of depositing the aluminum alloy film forming the first layer wiring are performed in the same manner as in the first embodiment. Thereafter, the conductive film is patterned to form an upper electrode 10U of the MIS capacitor C, an extraction electrode 10L connected to the lower electrode, an emitter electrode 10E of the bipolar transistor Tr, and a base electrode 10 as shown in FIG.
B and each of the collector electrodes 10C are formed. In this step, only the upper electrode 10U and the extraction electrode 10L are formed. At the same time, the electrodes 10 of the circuit element other than the MIS capacitor C and a part of the connection 11 between the electrodes are formed.

Next, an interlayer insulating film 17 is formed. After that, the electrode 10 (10U, 1
0L, 10E, 10B, and 10C) are formed.

Next, a conductive film, for example, an aluminum alloy film is deposited. This aluminum alloy film forms the second-layer wiring. Thereafter, the aluminum alloy film is patterned by a photolithography technique and an etching technique to form a second-layer wiring 18 as shown in FIG. By forming the wiring 18 of the second layer, the first wiring 18 is formed.
18A between the test pad and the upper electrode 10U,
Second inspection pad and extraction electrode 10L (lower electrode)
A connection 18B is formed. The wiring 18 of the second layer is formed of a circuit element other than the MIS capacitor C, for example, each electrode 10E, 10B, 10C of the bipolar transistor Tr.
Connected to. Then, after overloading the dielectric film 8 via each of the first and second test pads, the MIS capacitor C having the defective dielectric film 8 is detected.

Next, as shown in FIG. 11, for example, using the photoresist film 19 as a mask, the upper electrode 10U
18A between the electrode and the first inspection pad, the extraction electrode 1
Connection 18B between 0L (lower electrode) and second inspection pad
Is etched to make no connection.

Next, an interlayer insulating film 20 is formed. Thereafter, a connection hole for exposing the surface of the wiring 18 of the second layer is formed in the interlayer insulating film 20.

Next, a conductive film, for example, an aluminum alloy film is deposited. Thereafter, the aluminum alloy film is patterned by a photolithography technique and an etching technique to form a third-layer wiring 21. The wiring 21 of the third layer is connected to each electrode 10 of the bipolar transistor Tr.
E, 10B, 10C or other circuit element electrodes 10 and M
Connection of electrodes 10U and 10L of IS capacitance C, between electrodes 10E, 10B and 10C of bipolar transistor Tr, electrodes 10E, 10B and 10C of bipolar transistor Tr
And other circuit elements, and between the other circuit elements, respectively.

Next, a surface protection film (not shown) is formed on the third layer wiring 21 to complete the semiconductor integrated circuit device of the second embodiment.

As described above, according to the method of manufacturing the semiconductor integrated circuit device of the second embodiment, the MIS capacitor C and the circuit element connected thereto (for example, a bipolar transistor) are provided in different regions of the same semiconductor substrate. Tr), the yield and reliability can be improved, and the number of steps can be reduced, as in the first embodiment, in a semiconductor integrated circuit device connected with three layers of wirings (10, 17, 21).

Third Embodiment A method of manufacturing a semiconductor integrated circuit device according to a third embodiment of the present invention will be described with reference to FIG. 13 (a plan view showing some steps).

As shown in FIG. 13, in the third embodiment, a plurality of MIS capacitors C are provided in a predetermined area A (an area surrounded by a two-dot chain line) in the semiconductor chip 100. According to this configuration, in the first embodiment, within the region A,
Connection 11A between first inspection pad 12A and upper electrode 10U, second inspection pad 12B and extraction electrode 1
Connection 11B to 1LC (lower electrode) can be dedicated. That is, in the area other than the area A, the inspection pads 12A, 1
The wiring 11 not connected to 2B can be arranged in the same manner as in the related art.

[Fourth Embodiment] A method of manufacturing a semiconductor integrated circuit device according to a fourth embodiment of the present invention will be described with reference to FIGS.

As shown in FIG. 14, in the fourth embodiment, an opening 23 is formed in the interlayer insulating film 20 formed on the second-layer wiring 18 in the first embodiment. According to this configuration, in the region within the opening 23, the connection 11A between the first inspection pad and the upper electrode 10U, the second inspection pad and the extraction electrode 10L (lower electrode) are formed by using a laser. Of the connection 11B can be unconnected. Accordingly, in the step of etching the connection lines 11A and 11B to disconnect the connection lines in the first embodiment, the lower interlayer insulating film 17 is not damaged, so that the reliability can be further improved. The connection holes 23 are filled by forming a surface protection film (not shown) after the connection lines 11A and 11B are disconnected by a laser.

Although the present invention has been described in detail with reference to the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments and can be variously modified without departing from the scope of the invention. .

[0050]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

In a method of manufacturing a semiconductor integrated circuit device,
The yield can be improved.

In the method of manufacturing a semiconductor integrated circuit device, reliability can be improved.

In the method of manufacturing a semiconductor integrated circuit device, the number of steps can be reduced.

[Brief description of the drawings]

FIG. 1 is a flowchart of a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is an essential part cross sectional view showing the semiconductor integrated circuit device in a part of steps.

FIG. 3 is an essential part plan view showing the semiconductor integrated circuit device in part of a process;

FIG. 4 is an essential part cross sectional view showing the region shown in FIG. 2 as a part of the process;

FIG. 5 is an essential part plan view showing the region shown in FIG. 3 as a part of the process;

FIG. 6 shows a modification of the manufacturing method according to the first embodiment;
FIG. 4 is a plan view of a main part showing the region shown in FIG.

FIG. 7 is an essential part cross sectional view showing the region shown in FIG. 2 as a part of the process;

FIG. 8 shows a modification of the manufacturing method of the first embodiment;
FIG. 4 is a plan view of a main part showing the region shown in FIG.

FIG. 9 is an essential part cross sectional view showing a part of a process of a semiconductor integrated circuit device of a second embodiment of the present invention;

FIG. 10 is an essential part cross sectional view showing the region shown in FIG. 9 as a part of the process;

FIG. 11 is an essential part cross sectional view showing the region shown in FIG. 9 as a part of the process;

FIG. 12 is an essential part cross sectional view showing the region shown in FIG. 9 as a part of the process;

FIG. 13 shows a semiconductor integrated circuit device according to a third embodiment of the present invention;
FIG. 4 is a plan view illustrating a part of a process.

FIG. 14 illustrates a semiconductor integrated circuit device according to a fourth embodiment of the present invention.
Sectional drawing of the principal part shown in a part of process.

[Explanation of symbols]

1 ... p- type semiconductor substrate, 2 ... n + type semiconductor region, 3 ... n-
Type epitaxial layer, 4 ... p + type semiconductor region, 5 ... p type semiconductor region, 6 ... n type semiconductor region, 7 ... insulating film, 8 ... dielectric film, 10E ... emitter electrode, 10B ... base electrode,
10C: collector electrode, 10U: upper electrode, 10L: lead-out electrode, 10: electrode, 11, 11A, 11B: connection, 12A, 12B: inspection pad

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuhiro Tsurumaru 111 Nishiyokote-cho, Takasaki-shi, Gunma Co., Ltd. Inside the Takasaki Plant of Hitachi, Ltd. (72) Inventor Akira Ueno 111-111 Nishiyokote-cho, Takasaki-shi, Gunma Co., Ltd. (56) References JP-A-4-130748 (JP, A) JP-A-1-105569 (JP, A) (58) Fields studied (Int. Cl. ⁷ , DB name) H01L 21 / 822 H01L 21/8222-21/8228 H01L 21/8232 H01L 27 / 04,27 / 06 H01L 27 / 08,27 / 082

Claims (2)

(57) [Claims] An MIS capacitor having an upper electrode provided on a lower electrode formed of a semiconductor region via a dielectric film in each of mutually different regions of the same semiconductor substrate, and a plurality of MIS capacitors connected to the MIS capacitor. In a method of manufacturing a semiconductor integrated circuit device, each of circuit elements is formed, and each of the MIS capacitor and the circuit element and between the circuit elements are connected by two-layer wiring.
Forming a lower electrode and a dielectric film of a MIS capacitor, and a plurality of circuit elements in each of the mutually different regions of the semiconductor substrate; and forming an upper electrode of the MIS capacitor by a first layer wiring Forming a part of a connection between the upper electrode and a first inspection pad, a connection between the lower electrode and a second inspection pad, and a connection between the plurality of circuit elements; Applying a predetermined voltage to a second inspection pad to apply an overload to the dielectric film of the MIS capacitor; connecting the upper electrode of the MIS capacitor to the first inspection pad; Disconnecting each of the connections between the MIS capacitor and the plurality of circuit elements, and forming a connection between the MIS capacitor and the plurality of circuit elements and a remaining connection between the circuit elements with the wiring of the second layer. Semiconductor integrated circuit, comprising the steps of: Method of manufacturing location. 2. An upper electrode of the MIS capacitor is formed by a first-layer wiring, and a connection between the upper electrode and a first inspection pad, a connection between the lower electrode and a second inspection pad, Each of a part of the connection between the circuit elements is formed by a wiring of a second layer above the wiring of the first layer, and a connection between the MIS capacitor and a plurality of circuit elements and a remaining part of a connection between the plurality of circuit elements. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein each of the semiconductor integrated circuit devices is formed by a third layer of wiring above the second layer of wiring.