JPH05218310A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the number of processes while improving the yield and the reliability. CONSTITUTION:A lower electrode and a dielectric film 8 in a MIS capacity C and a plurality of circuit elements are formed respectively. By a first layer wiring, an upper electrode 10U in the MIS capacity C, a connection 11A between the upper electrode 10U and a first pad 12A for test, a connection 11B between the lower electrode (electrode 10L for lead-out) and a second pad 12B for test, and a part of a connection 11 between a plurality of the circuit elements are formed. Then, a predetermined voltage is applied to the pads 12A and 12B for test and an overload is given to the dielectric film 8, and the connections 11A and 11B are unconnected respectively. By a second layer wiring, a connection between the MIS capacity C and a plurality of the circuit elements, and the remaining connections between the circuit elements are formed. Thus, an etching process on the surface of the dielectric film 8 can be eliminated, and the connections 11A and 11B can be formed together with the process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit having MIS capacitors and a plurality of circuit elements connected to the MIS capacitors in different regions of a semiconductor substrate. The present invention relates to a technique effectively applied to a device manufacturing method.

[0002]

2. Description of the Related Art MIS is formed in different regions of a semiconductor substrate.
A so-called bipolar-linear IC, which is a semiconductor integrated circuit device including a capacitor and a bipolar transistor, is used.

The MIS capacitor is composed of a lower electrode composed of a semiconductor region and an upper electrode provided on the lower electrode via a dielectric film. The semiconductor region forming the lower electrode is provided on the main surface portion of the semiconductor substrate. An extraction electrode is connected to the lower electrode. This extraction electrode is formed in the wiring forming process of the first layer. The extraction electrode is formed of, for example, an aluminum alloy film to which silicon is added.
The dielectric film is provided on the main surface of the semiconductor substrate.
This dielectric film is composed of, for example, a silicon nitride film. The upper electrode is similar to the extraction electrode in the first electrode.
It is composed of an aluminum alloy film formed in the wiring forming process of the layer.

Electrodes are connected to the semiconductor regions forming the emitter region, base region and collector region of the bipolar transistor, respectively. These electrodes are composed of an aluminum alloy film formed in the same step as the upper electrode and the extraction electrode.

Between the upper electrode and the extraction electrode of the MIS capacitor and each electrode of the bipolar transistor,
It is connected by using the wiring of the first layer and the wiring of the second layer. The second-layer wiring is made of, for example, an aluminum alloy film, like the first-layer wiring.

In the semiconductor integrated circuit device having the above-described structure, the dielectric breakdown film (TDD) of the MIS capacitor dielectric film with time elapses.
B: T ime D ependent D ielectric B reakdown) becomes a problem. Therefore, it is necessary to detect a dielectric film that may cause dielectric breakdown over time. As a method of detecting such a dielectric film, QCTEG within step (Q uali
The ty C heck T est E lementary G roup), checks the chip components at several points per semiconductor wafer, and finally there is a method to remove the initial failure in aging product.

[0007]

However, as a result of examining the above-mentioned prior art, the present inventor has found the following problems.

Since aging is performed after connecting the MIS capacitor and the bipolar transistor, it is impossible to apply a voltage higher than the maximum rating of the bipolar transistor. Therefore, even if the aging is performed, some of the dielectric films that may be in initial failure may not be destroyed, and there is a problem that initial failure occurs.

Therefore, although it is not a known technique, Japanese Patent Application No. 2-
As described in No. 252286, prior to the first layer wiring formation step, the upper electrode of the MIS capacitor and the extraction electrode are formed, and the inspection pad is formed.
A method has been proposed in which the inspection pad and the upper electrode, and the inspection pad and the extraction electrode are connected to each other so as to overload the dielectric film through the inspection pad. By overloading the dielectric film, the dielectric film, which may be initially defective, is destroyed. After that, the dielectric film is inspected using the inspection pad to detect the destroyed dielectric film. Next, each of the upper electrode, the extraction electrode, the inspection pad, the connection between the upper electrode and the inspection pad, and the connection between the extraction electrode and the inspection pad are removed by etching. After that, a method of forming each of the conventional first-layer wiring and second-layer wiring is proposed. But,
In the process of removing the wiring on the same layer as the inspection pad,
Since the surface of the dielectric film of the MIS capacitor is also etched,
There is a problem that the film quality of the dielectric film deteriorates and the dielectric strength of the dielectric film decreases.

As another method, which is not a known technique, as described in Japanese Patent Application No. 3-333601, a semiconductor integrated circuit in which a MIS capacitor and a MISFET are connected by a single layer wiring In the method of manufacturing a circuit device, the wiring layer forming step is divided into two steps, and in the first wiring forming step, the upper electrode of the MIS capacitor, the lead-out electrode, and the inspection pad are formed, and the upper electrode and the inspection are formed. A method has been proposed in which the dielectric film is overloaded via the inspection pad by connecting the extraction pad and the inspection pad to each other. Overloading the dielectric film destroys the dielectric film, which can lead to initial failure. Next, after detecting a dielectric film that may cause an initial failure, in the second wiring formation process, the MIS capacitance and the MISF are reduced.
Connect with ET. However, in this case, there is a problem that the number of steps is increased because the number of steps for forming the wiring is substantially increased once.

An object of the present invention is to provide a technique capable of improving yield in a method of manufacturing a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of improving reliability in the method of manufacturing a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of reducing the number of steps in the method for manufacturing a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0015]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

(1) A MIS capacitor in which an upper electrode is provided on a lower electrode formed of a semiconductor region via a dielectric film in each of different regions of the same semiconductor substrate, and a plurality of MIS capacitors are connected to the MIS capacitor. Each of the circuit elements of
2 between the IS capacitance and the circuit element and between the circuit element, respectively.
In a method of manufacturing a semiconductor integrated circuit device in which wirings of different layers are used, M of each region of the semiconductor substrate is different from each other.
The step of forming each of the lower electrode of the IS capacitor and the dielectric film, and the plurality of circuit elements, and the wiring of the first layer,
An upper electrode of S capacitance is formed, and a connection between the upper electrode and the first inspection pad, a connection between the lower electrode and the second inspection pad, and a part of the connection between the plurality of circuit elements are formed. A step of applying a predetermined voltage to the first and second inspection pads to overload the dielectric film of the MIS capacitor with the upper electrode of the MIS capacitor and the first inspection pad. Connection between the MIS capacitor and the plurality of circuit elements in the second layer wiring, and a step of disconnecting each of the connection between the lower electrode and the second inspection pad Forming a remaining connection between the circuit elements.

(2) The upper electrode of the MIS capacitor has a first
The upper electrode and the first inspection pad, the lower electrode and the second inspection pad, and a part of the connection between a plurality of circuit elements. The wiring of the second layer, which is an upper layer than the wiring of the second layer, is connected to the MIS capacitor and a plurality of circuit elements, and each of the remaining portions of the wiring between the plurality of circuit elements is a third layer which is an upper layer of the wiring of the second layer. It is formed by wiring.

[0018]

According to the above-mentioned means (1) or (2), the step of peeling the wiring of the first layer formed on the dielectric film can be eliminated, so that the dielectric strength of the dielectric film is lowered by etching. Can be prevented. As a result, the yield of the semiconductor integrated circuit device can be improved. In addition, reliability can be improved.

Further, since the wiring of the first layer or the wiring of the second layer is also used, the connection between the upper electrode and the inspection pad and the connection between the lower electrode and the inspection pad are formed. The number can be reduced.

[0020]

Embodiments of the present invention will be specifically described below with reference to the drawings. In all the drawings for explaining the embodiments, parts having the same functions are designated by the same reference numerals, and the repeated description thereof will be omitted.

[First Embodiment] A method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention will be described with reference to FIG. 1 (flow chart).

First, an n-type impurity is introduced into the main surface portion of the p--type semiconductor substrate 1. Then, the n − type epitaxial layer 3 is formed on the main surface of the p − type semiconductor substrate 1. In this step, the buried n + type semiconductor region 2 is formed in the main surface portion of the p − type semiconductor substrate 1 and under the n − type epitaxial layer 3. The n − type epitaxial layer 3 constitutes the collector region of the bipolar transistor Tr and the lower electrode of the MIS capacitor C, respectively.

Next, p-type impurities are introduced into the non-active region of the n-type epitaxial layer 3 to form the p-type semiconductor region 4
To form. The p − type semiconductor region 4 constitutes an isolation region. Then, the p-type semiconductor region 5 forming the base region of the bipolar transistor Tr and the n-type semiconductor region 6 forming the emitter region are formed on the main surface portion of the n − type epitaxial layer 3 in the active region.

Next, an insulating film 7 is formed on the main surface of the n − type epitaxial layer 3. After that, an opening is formed in the insulating film 7 in the formation region of the MIS capacitor C.

Next, the dielectric film 8 of the MIS capacitor C is formed <101>. The dielectric film 8 is formed, for example, by depositing a silicon nitride film and then patterning the silicon nitride film by a photolithography technique and an etching technique. After that, an opening is formed in the insulating film 7 on the lower electrode of the MIS capacitor C and on each operation region of the bipolar transistor Tr.

Next, a conductive film, for example, an aluminum alloy film containing silicon is deposited. This aluminum alloy film constitutes the first layer wiring. After that, this aluminum alloy film is patterned by the photolithography technique and the etching technique. As a result of this patterning process, as shown in FIG. 2 (partial sectional view showing a part of the process) and FIG. 3 (plan view showing a main part of the process), the upper electrode 10U and the lower electrode of the MIS capacitor C are shown. The extraction electrode 10L, the emitter electrode 10E of the bipolar transistor, the base electrode 10B, and the collector electrode 10C that are connected to each other are formed. In FIG. 3, the MIS capacitance C is mainly used.
, The bipolar transistor Tr is not shown. At the same time, a connection 11A between the first inspection pad 12A and the upper electrode 10U and a connection 11B between the second inspection pad 12B and the extraction electrode 10L (lower electrode) are formed. At the same time,
As shown in FIG. 3, part of the electrode 10 of the circuit element other than the MIS capacitance C and the connection 11 between the electrodes 10 is formed <1.
02>.

Next, the first and second inspection pads 1
For example, a voltage of about 80V is applied to each of 2A and 12B.
Apply for about 1 second to overload the dielectric film 8 <103
>. In this step, the film quality of the dielectric film 8 is poor,
Since a material having a low withstand voltage is destroyed, the dielectric film 8 which may lead to initial failure is destroyed.

Next, the first and second inspection pads 1
The probe needle of the wafer prober is pressed against each of 2A and 12B to detect the destroyed dielectric film 8 <104
>. For example, laser marking is applied to the semiconductor chip having the detected defective MIS capacitance C. Also,
The position of the semiconductor chip having the defective MIS capacity may be stored in the storage medium.

Next, as shown in FIG. 4 (partial sectional view showing a part of the process) and FIG. 5 (plan view of a main part showing a part of the process), for example, a photoresist film 15 (in FIG. 5, is shown). (Not shown) as a mask, the connection 11A between the upper electrode 10U and the first inspection pad 12A, the extraction electrode 10
The connection 11B between L (lower electrode) and the second inspection pad 12B is etched to be non-connection <105>. Alternatively, the connection lines 11A and 11B may be unconnected with a laser. In addition, in order not to connect, the connection 11A, 11B
At the time of removing, as shown in FIG. 6 (a plan view of a main part showing a modified example of the manufacturing method of Example 1 and showing a part of the process),
Almost electrodes 10U, 10L, inspection pads 12A, 12
You may make it leave only the part of B.

Next, the interlayer insulating film 17 is formed. After that, the electrode 10 (10U, 1
0L, 10E, 10B, 10C) to form a connection hole exposing the surface.

Next, a conductive film such as an aluminum alloy film is deposited. This aluminum alloy film constitutes the second layer wiring. After that, this aluminum alloy film is patterned by photolithography and etching techniques to form the wiring 18 of the second layer. This second layer wiring 1
8 denotes each electrode 10 of the bipolar transistor Tr.
Electrodes 10 and M of E, 10B, 10C or other circuit elements
Connection with the electrodes 10U, 10L of the IS capacitance C, between the electrodes 10E, 10B, 10C of the bipolar transistor Tr and the electrodes 10E, 10B, 10C of the bipolar transistor
And the remaining part of the connection between the electrode 10 of another circuit element and
106>.

Next, a surface protection film (not shown) is formed on the second layer wiring 18 to complete the semiconductor integrated circuit device of the first embodiment.

As described above, in the method of manufacturing the semiconductor integrated circuit device according to the first embodiment, the n − type epitaxial layer 3 is formed in each of the different regions of the p − type semiconductor substrate 1.
A MIS capacitor C in which an upper electrode 10U is provided on the lower electrode constituted by a dielectric film 8 and a circuit element connected to the MIS capacitor C (for example, a bipolar transistor Tr).
In the method of manufacturing a semiconductor integrated circuit device, wherein the MIS capacitor C and the circuit element and the circuit element are connected by two layers of wirings (10, 18). A step of forming a lower electrode (n − type epitaxial layer 3) of the MIS capacitor C and a dielectric film 8 and a circuit element (for example, a bipolar transistor Tr) in each of different regions of 1; Wiring 10 of
While forming the upper electrode 10U of the MIS capacitor C,
Connection 11A between the upper electrode 10U and the first inspection pad 12A, and the extraction electrode 10 connected to the lower electrode
Forming a part of the connection 11B between the L and the second inspection pad 12B and the connection 11 between the circuit elements;
And a step of applying a predetermined voltage to the second inspection pads 12A and 12B to overload the dielectric film 8 of the MIS capacitor C, and the upper electrode 10U of the MIS capacitor C and the first inspection pad. 11A for connection to 12A, electrode 10L for extraction connected to the lower electrode, and second inspection pad 12
The method includes the step of unconnecting each of the connections 11B with B, and the step of forming the connection between the MIS capacitance C and the circuit element and the remaining connection between the circuit elements with the wiring 18 of the second layer. .. According to this configuration, the step of peeling the upper electrode 10U formed on the dielectric film 8 can be eliminated, so that the dielectric breakdown voltage of the dielectric film 8 can be prevented from lowering due to etching. As a result, the yield of the semiconductor integrated circuit device can be improved. In addition, reliability can be improved.

The upper electrode 10U and the first inspection pad 12A are also used for the step of forming the wiring 10 of the first layer.
11A between the second inspection pad 12B and the extraction electrode 10L connected to the lower electrode.
Since it is formed, the number of steps can be reduced.

Although FIG. 3 shows an example in which the lead-out electrode 10L connected to the lower electrode of the MIS capacitor C and the second inspection pad 12B are connected by the connection line 11B, a plurality of MISs are shown. When the n − -type epitaxial layer 3 forming the lower electrode of the capacitor C is electrically connected, FIG. 8 (a modified example of the manufacturing method of the first embodiment, showing a part of the process) As shown in the plan view), a common extraction electrode 10LC is formed on the lower electrodes of a plurality of MIS capacitors C, and the common extraction electrode 10LC and the second inspection pad 12B are connected by a connection wire 11B. You may.

[Embodiment 2] A method for manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention will be described with reference to FIGS. 9 to 12 (a main part sectional view showing a part of the process of the semiconductor integrated circuit device of the second embodiment). Will be explained.

First, the steps up to the step of depositing the aluminum alloy film forming the first layer wiring are performed in the same manner as in the first embodiment. After that, the conductive film is patterned, and as shown in FIG. 9, the upper electrode 10U of the MIS capacitor C, the extraction electrode 10L connected to the lower electrode, the emitter electrode 10E of the bipolar transistor Tr, and the base electrode 10 are formed.
B and the collector electrode 10C are formed respectively. In this step, only the upper electrode 10U and the extraction electrode 10L are formed. At the same time, the electrodes 10 of the circuit elements other than the MIS capacitance C and a part of the connection 11 between the electrodes are formed.

Next, the interlayer insulating film 17 is formed. After that, the electrode 10 (10U, 1
0L, 10E, 10B, 10C) to expose the surface of the connection hole is formed.

Next, a conductive film such as an aluminum alloy film is deposited. This aluminum alloy film constitutes the second layer wiring. After that, this aluminum alloy film is patterned by a photolithography technique and an etching technique to form a second layer wiring 18, as shown in FIG. By forming the wiring 18 of the second layer,
Connection 18A between the inspection pad and the upper electrode 10U,
Second inspection pad and extraction electrode 10L (lower electrode)
A connection line 18B between and is formed. The wiring 18 of the second layer is a circuit element other than the MIS capacitance C, for example, the electrodes 10E, 10B, 10C of the bipolar transistor Tr.
Connected to. Then, after overloading the dielectric film 8 via each of the first and second inspection pads, the MIS capacitance C having the defective dielectric film 8 is detected.

Next, as shown in FIG. 11, for example, using the photoresist film 19 as a mask, the upper electrode 10U is formed.
18A for connecting the first inspection pad and the drawing electrode 1
Connection 18B between 0L (lower electrode) and the second inspection pad
Is etched to make non-connection.

Next, the interlayer insulating film 20 is formed. After that, a connection hole exposing the surface of the wiring 18 of the second layer is formed in the interlayer insulating film 20.

Next, a conductive film such as an aluminum alloy film is deposited. Then, the aluminum alloy film is patterned by photolithography and etching techniques to form the wiring 21 of the third layer. The wiring 21 of the third layer is used for each electrode 10 of the bipolar transistor Tr.
Electrodes 10 and M of E, 10B, 10C or other circuit elements
Connection of electrodes 10U, 10L of IS capacitance C, between electrodes 10E, 10B, 10C of bipolar transistor Tr, electrodes 10E, 10B, 10C of bipolar transistor Tr
And other circuit elements, and between the other circuit elements, respectively.

Next, a surface protective film (not shown) is formed on the third-layer wiring 21 to complete the semiconductor integrated circuit device of the second embodiment.

As described above, according to the method of manufacturing the semiconductor integrated circuit device of the second embodiment, the MIS capacitor C and the circuit element (eg, bipolar transistor) connected to the MIS capacitor C are formed in different regions of the same semiconductor substrate. In the semiconductor integrated circuit device in which three layers of wirings (10, 17, 21) are connected to Tr), yield and reliability can be improved and the number of steps can be reduced as in the first embodiment.

[Embodiment 3] A method for manufacturing a semiconductor integrated circuit device according to Embodiment 3 of the present invention will be described with reference to FIG. 13 (a plan view showing a part of the process).

As shown in FIG. 13, in the third embodiment, a plurality of MIS capacitors C are collectively provided in a predetermined area A (area surrounded by a chain double-dashed line) in the semiconductor chip 100. According to this configuration, in the first embodiment, within the area A,
Connection 11A between first inspection pad 12A and upper electrode 10U, second inspection pad 12B and lead-out electrode 1
The connection 11B with 1LC (lower electrode) can be dedicated. That is, in the areas other than the area A, the inspection pads 12A, 1
The wiring 11 that is not connected to 2B can be arranged in the same manner as the conventional one.

[Embodiment 4] A method for manufacturing a semiconductor integrated circuit device according to Embodiment 4 of the present invention will be described with reference to FIG. 14 (a cross-sectional view of an essential part showing part of the process).

As shown in FIG. 14, in the fourth embodiment, an opening 23 is formed in the interlayer insulating film 20 formed on the wiring 18 of the second layer in the first embodiment. According to this configuration, in the region within the opening 23, the laser is used to connect the first inspection pad and the upper electrode 10U to the connection 11A, the second inspection pad and the extraction electrode 10L (lower electrode). Each of the connection lines 11B can be unconnected. Therefore, in the step of etching the connection lines 11A and 11B in the first embodiment to make them non-connection, the lower interlayer insulating film 17 is not damaged, and therefore the reliability can be further improved. The connection holes 23 are filled by forming the surface protection film (not shown) after the connection lines 11A and 11B are not connected with a laser.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention. ..

[0050]

The effects obtained by the representative ones of the inventions disclosed in this application will be briefly described as follows.

In the method of manufacturing a semiconductor integrated circuit device,
The yield can be improved.

In the method of manufacturing a semiconductor integrated circuit device, reliability can be improved.

In the method of manufacturing the semiconductor integrated circuit device, the number of steps can be reduced.

[Brief description of drawings]

FIG. 1 is a flowchart of a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a principal portion showing the semiconductor integrated circuit device as part of a process.

FIG. 3 is a plan view of a principal portion showing the semiconductor integrated circuit device as part of a process.

FIG. 4 is a cross-sectional view of an essential part showing the region shown in FIG. 2 as a part of the process.

FIG. 5 is a plan view of an essential part showing the region shown in FIG. 3 as a part of the process.

FIG. 6 shows a modified example of the manufacturing method of the first embodiment, and FIG.
FIG. 4 is a plan view of a main part showing the region shown in FIG.

FIG. 7 is a cross-sectional view of an essential part showing the region shown in FIG. 2 as a part of the process.

FIG. 8 shows a modified example of the manufacturing method of the first embodiment, and FIG.
FIG. 4 is a plan view of a main part showing the region shown in FIG.

FIG. 9 is a main-portion cross-sectional view showing a semiconductor integrated circuit device in Embodiment 2 of the present invention in a part of the process.

FIG. 10 is a cross-sectional view of an essential part showing the region shown in FIG. 9 as a part of the process.

FIG. 11 is a cross-sectional view of an essential part showing the region shown in FIG. 9 as a part of the process.

FIG. 12 is a cross-sectional view of an essential part showing the region shown in FIG. 9 as a part of the process.

FIG. 13 shows a semiconductor integrated circuit device according to a third embodiment of the present invention,
The top view shown in a part of process.

FIG. 14 shows a semiconductor integrated circuit device according to a fourth embodiment of the present invention,
Sectional drawing of the principal part shown in some processes.

[Explanation of symbols]

1 ... p-type semiconductor substrate, 2 ... n + type semiconductor region, 3 ... n-
Type epitaxial layer, 4 ... p + type semiconductor region, 5 ... p type semiconductor region, 6 ... n type semiconductor region, 7 ... insulating film, 8 ... dielectric film, 10E ... emitter electrode, 10B ... base electrode,
10C ... Collector electrode, 10U ... Upper electrode, 10L ... Extraction electrode, 10 ... Electrode, 11, 11A, 11B ... Connection, 12A, 12B ... Inspection pad

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kazuhiro Tsurumaru, Inventor 111 Nishiyokote-cho, Takasaki-shi, Gunma Hitachi Ltd. Takasaki Plant (72) Inventor Akira Ueno 111 Nishiyote-cho, Takasaki-shi, Gunma Hitachi, Ltd. Takasaki Factory

Claims (2)

[Claims] 1. A MIS capacitor in which an upper electrode is provided on a lower electrode formed of a semiconductor region via a dielectric film in each of different regions of the same semiconductor substrate, and a plurality of MIS capacitors connected to the MIS capacitor are provided. A method for manufacturing a semiconductor integrated circuit device, comprising forming each of circuit elements, and connecting the MIS capacitor and the circuit element and between the circuit elements with a two-layer wiring,
Forming a lower electrode and a dielectric film of a MIS capacitor and a plurality of circuit elements in different regions of the semiconductor substrate, and forming an upper electrode of the MIS capacitor by a first layer wiring And forming a part of the connection between the upper electrode and the first inspection pad, the connection between the lower electrode and the second inspection pad, and the connection between the plurality of circuit elements; And applying a predetermined voltage to the second inspection pad to overload the dielectric film of the MIS capacitor, the connection between the upper electrode of the MIS capacitor and the first inspection pad, the lower electrode And connecting the second inspection pad to each other, and forming a connection between the MIS capacitor and a plurality of circuit elements and a remaining connection between the circuit elements with the second layer wiring. And a semiconductor integrated circuit Method of manufacturing location. 2. The upper electrode of the MIS capacitor is formed by a wiring of a first layer, the upper electrode and the first inspection pad are connected, the lower electrode and the second inspection pad are connected, Part of each of the wirings between the circuit elements is formed by the wiring of the second layer above the wiring of the first layer, and the MIS capacitor and the wirings of the plurality of circuit elements and the remaining portion of the wirings between the plurality of circuit elements are formed. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein each of the wirings is formed by a wiring of a third layer above the wiring of the second layer.