KR100439835B1 - Multi-probing pad and fabricating method thereof to form stable pad contact and avoid decrease of adhesion in wire bonding process - Google Patents

Multi-probing pad and fabricating method thereof to form stable pad contact and avoid decrease of adhesion in wire bonding process Download PDF

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KR100439835B1
KR100439835B1 KR1019970032573A KR19970032573A KR100439835B1 KR 100439835 B1 KR100439835 B1 KR 100439835B1 KR 1019970032573 A KR1019970032573 A KR 1019970032573A KR 19970032573 A KR19970032573 A KR 19970032573A KR 100439835 B1 KR100439835 B1 KR 100439835B1
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pad
layer
metal layer
metal
polysilicon
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KR1019970032573A
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KR19990009973A (en
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이동훈
김원철
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: A multi-probing pad is provided to form a stable pad contact and avoid a decrease of adhesion in a wire bonding process by forming a polysilicon layer on a tungsten plug functioning as a contact before a final metal layer is deposited. CONSTITUTION: A predetermined semiconductor device is formed on a semiconductor substrate(10). The first metal layer(20) is formed on a pad region of the semiconductor substrate. An insulation layer(30) is formed on the first metal layer, having several via holes from the upper part of the insulation layer to the first metal layer under the insulation layer. The via holes are filled with tungsten plugs(22). A polysilicon layer is stacked on the insulation layer to expose at least one tungsten plug. The second metal layer(24) is formed to cover the polysilicon layer and the exposed tungsten plug.

Description

멀티-플로빙용 패드 및 그 제조방법Multi-Flobbing Pad and Manufacturing Method Thereof

본 발명은 멀티-플로빙용 패드에 관한 것으로, 특히 로직(LOGIC)과 메모리가 하나의 칩으로 구성된 MDL(Merged DRAM & LOGIC)제품에 적용되는 멀티-플로빙용 패드 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-floving pad, and more particularly, to a multi-floving pad and a method for manufacturing the same, which are applied to a MDL (Merged DRAM & LOGIC) product in which a logic and a memory are composed of one chip.

MDL제품은 다중 메탈 구조의 가지고 있다. 따라서, 그 제조공정상 메탈의 정확한 패턴을 얻기 위해서 각 층간의 심한 단차를 보상하기 위한 CMP(Chemical Mechanical Polishing) 평탄화 공정을 필요로 하게 되었다. 이러한 평탄화 공정의 적용에 따라 콘택의 종횡비(Aspect Ratio)가 커지게 되어 이전의 알루미늄 플로우(Flow) 방식으로는 정확한 콘택을 얻을 수 없기 때문에 이를 극복하기 위한 텅스텐플러그 방식을 채택하게 되었다.MDL products have a multi-metal structure. Therefore, in order to obtain an accurate pattern of the metal in the manufacturing process, a chemical mechanical polishing (CMP) planarization process is required to compensate for the severe step between layers. As the planarization process is applied, the aspect ratio of the contact increases, and thus, a tungsten plug method for overcoming this is adopted because an accurate contact cannot be obtained by the aluminum flow method.

도 1를 참조하여 종래 MDL 제품의 패드 제조공정을 구체적으로 설명하면 다음과 같다.A pad manufacturing process of a conventional MDL product will be described in detail with reference to FIG. 1.

소정의 반도체 소자가 형성된 반도체 기판(10)의 패드 영역 상에 메탈-1(20)을 증착 및 패터닝한 후, 그 위에 절연막(30)을 침적하고 상부로부터 메탈-1(20)이 노출되도록 선택적으로 상기 절연막을 식각하여 복수개의 비아홀을 형성한 다음, 그 결과물 상에 텅스텐을 침적 및 CMP를 이용 평탄화하여 비아홀 내에 텅스텐플러그들(22)을 형성한다. 그런 다음 상기 결과물 상에 메탈-2(24)를 증착 및 패터닝하게 된다.After depositing and patterning the metal-1 20 on the pad region of the semiconductor substrate 10 on which the predetermined semiconductor element is formed, the insulating layer 30 is deposited thereon, and the metal-1 20 is selectively exposed from the top. After the insulating film is etched to form a plurality of via holes, tungsten is deposited on the resultant and planarized using CMP to form tungsten plugs 22 in the via holes. The metal-2 24 is then deposited and patterned on the resultant.

이러한 종래 MDL 제품은 CMP 공정의 도입에 따라 패드의 메탈 두께가 얇아지게 된다.The conventional MDL product has a thin metal thickness of the pad with the introduction of the CMP process.

한편, MDL 제품은 로직(LOGIC)과 메모리가 한 칩으로 되어 있기 때문에 로직과 메모리에 대하여 ESD(ElectroStatic Discharge) 테스트를 각각 실행하여야 한다. 따라서, 기존 메모리 제품의 경우 ESD 진행시 최대 3회의 플로빙(Probing)이 가해지게 되는데 반하여, MDL 제품의 경우 동일 패드에 4회 내지 6회 이상의 플로빙이 가해지게 된다.On the other hand, MDL products have one logic and one chip, so each electrostatic discharge (ESD) test must be performed on the logic and memory. Therefore, in the conventional memory products, up to three probing is applied during ESD, while in the case of MDL products, four to six or more provings are applied to the same pad.

따라서, CMP 공정으로 얇아진 패드의 메탈에 4회 이상의 멀티-플로빙이 가해지게 되어 플로빙 충격에 의해 메탈 하부의 절연막(산화막)이 노출될 가능성 매우 크고, 또한 산화막 노출로 인하여 와이어 본딩시 본딩와이어가 산화막에 닿게되어 접착력이 저하되므로, 결국 제품 신뢰성에 영향을 미치게 된다.Therefore, four or more multi-flovings are applied to the metal of the pad, which is thinned by the CMP process, and the insulating film (oxide) under the metal is very likely to be exposed by the floating impact, and the bonding wire during wire bonding due to the oxide film exposure. The contact with the oxide film lowers the adhesive force, which eventually affects the product reliability.

본 발명의 목적은 멀티-플로빙시의 패드 손상으로 인해 하부의 절연막이 노출되거나 이로인해 와이어 본딩시 접착력이 저하되는 것을 방지할 수 있는 멀티-플로빙용(Multi-probing) 패드 및 그 제조방법을 제공하는 데에 있다.Disclosure of Invention An object of the present invention is to provide a multi-probing pad and a method for manufacturing the same, which can prevent the lower insulating film from being exposed due to damage to the pad during multi-floving or thereby degrading the adhesive strength during wire bonding. It's there.

상기 본 발명의 목적을 달성하기 위한 멀티-플로빙용 패드는, 소정의 반도체 소자가 형성된 반도체 기판과, 상기 기판의 패드 영역 상부에 형성되는 제 1 메탈층과, 상기 제 1 메탈층의 상부에 형성되며 상부로부터 하부 제 1메탈층까지 수개의 비아홀이 형성되는 절연막과, 상기 비아홀 내에 충진되는 텅스텐플러그들과, 상기 절연막의 상부에 적어도 한 개 이상의 텅스텐플러그가 노출되도록 적층되는 폴리실리콘층과, 상기 폴리실리콘층과 노출된 텅스텐플러그가 덮히도록 형성되는 제 2 메탈층을 포함하는 데에 그 특징이 있다.A multi-floating pad for achieving the object of the present invention is formed on a semiconductor substrate formed with a predetermined semiconductor element, a first metal layer formed on the pad region of the substrate, and an upper portion of the first metal layer. And an insulating film in which several via holes are formed from an upper portion to a lower first metal layer, tungsten plugs filled in the via holes, a polysilicon layer stacked to expose at least one tungsten plug on the insulating film, and It is characterized by including a second metal layer formed to cover the polysilicon layer and the exposed tungsten plug.

또한 멀티-플로빙용 패드의 제조방법은, 소정의 반도체 소자가 형성된 반도체 기판의 패드 영역 상부에 제 1 메탈층과 절연막을 순차적으로 적층하는 단계와, 상기 절연막 상부로부터 제 1 메탈층이 노출되도록 복수개의 비아홀을 형성하는 단계와, 상기 결과물 상에 텅스텐을 침적하고 평탄화하여 비아홀 내에 텅스텐 플러그를 형성하는 단계와, 상기 결과물 상에 폴리실리콘을 침적하고 패드 영역을 제외한 부분을 식각하여 제거하는 단계와, 상기 결과물 상에 제 2 메탈층을 증착하고 패터닝하는 단계를 포함하는 데에 그 특징이 있다.In addition, a method of manufacturing a multi-floating pad may include sequentially stacking a first metal layer and an insulating layer on a pad region of a semiconductor substrate on which a semiconductor device is formed, and exposing a plurality of first metal layers from an upper portion of the insulating layer. Forming two via holes, depositing and planarizing tungsten on the resultant to form a tungsten plug in the via hole, depositing polysilicon on the resultant, and etching and removing portions except the pad region; And depositing and patterning a second metal layer on the resultant.

도 1은 종래 MDL(Merged DRAM & LOGIC) 제품의 패드 구조를 보인 단면도.1 is a cross-sectional view showing a pad structure of a conventional MDL (Merged DRAM & LOGIC) product.

도 2 내지 도 7은 본 발명에 따른 멀티-플로빙용 패드의 제조공정순 구조 단면도.2 to 7 is a cross-sectional view of the manufacturing process of the multi-floving pad in accordance with the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

10 : 실리콘 기판 20 : 메탈-110 silicon substrate 20 metal-1

22 : 텅스텐플러그 24 : 메탈-222: tungsten plug 24: metal-2

30 : 절연막 40 : 패시베이션막30 insulating film 40 passivation film

100 : 포토레지스트100: photoresist

이하, 본 발명의 바람직할 실시예를 첨부된 도면을 참조하여 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

도 2 내지 도 6은 본 발명에 따른 멀티-플로빙용 패드의 제조공정순 구조 단면도이다.2 to 6 are cross-sectional views showing the manufacturing process of the multi-floving pad according to the present invention.

도 2를 참조하면, 실리콘 기판(10) 상부에 소정의 반도체 소자를 형성하고, 패드 영역 상에 하부배선으로 메탈-1(20)을 증착 및 패터닝한 후 절연막(30)을 침적한다.Referring to FIG. 2, a predetermined semiconductor device is formed on the silicon substrate 10, the metal-1 20 is deposited and patterned on the pad area with a lower wiring, and the insulating film 30 is deposited.

다음 도 3에서와 같이, 상기 절연막(30) 상에 비아 패턴을 형성하기 위하여 포토레지스트(100)을 침적한 후 사진 공정으로 패터닝하고, 이를 식각 마스크로 사용하여 절연막(30)상에 메탈-1(20)이 노출되도록 복수개의 비아홀을 형성한다.Next, as shown in FIG. 3, the photoresist 100 is deposited to form a via pattern on the insulating layer 30, and then patterned by a photolithography process, and the metal-1 on the insulating layer 30 is used as an etching mask. A plurality of via holes are formed to expose 20.

다음 도 4와 같이, 상기 결과물 상부에 스퍼터링 방식으로 텅스텐(W)을 증착하고, CMP(Chemical Mechanical Polishing) 방법을 사용, 평탄화하여 절연막(30) 상부의 텅스텐층을 제거하여 절연막(30)의 비아홀에 텅스텐플러그(22)를 형성한다.Next, as shown in FIG. 4, tungsten (W) is deposited on the resultant by sputtering, and planarized by using a CMP (Chemical Mechanical Polishing) method to remove the tungsten layer on the insulating film 30 to form a via hole in the insulating film 30. A tungsten plug 22 is formed in the hole.

다음 도 5와 같이, 상기 결과물 상부에 폴리실리콘을 침적한 후 패드 영역 이외의 폴리실리콘을 제거하여, 바람직하게는 상기 텅스텐플러그(22)가 적어도 1개 이상 노출되도록 패터닝하여 폴리실리콘층(60)을 형성한다. 이때에 상기 폴리실리콘층(60)은 패드의 멀티-플로빙시 메탈 파손을 방지하기 위한 것으로, 플라즈마 방법으로 500∼1000Å 두께로 침적하는 것이 좋다.Next, as shown in FIG. 5, polysilicon is deposited on the resultant, and then polysilicon other than the pad region is removed, and preferably, the tungsten plug 22 is patterned to expose at least one polysilicon layer 60. To form. At this time, the polysilicon layer 60 is to prevent metal breakage during the multi-floving of the pad, and is preferably deposited to a thickness of 500 to 1000 kPa by the plasma method.

다음 도 6에서와 같이, 상기 결과물 상에 배리어메탈(도면에는 도시하지 않음) 및 메탈을 증착하고 하부의 폴리실리콘층(60)과 텅스텐플러그(22)가 모두 덮히도록 패터닝하여 메탈-2(24)을 형성한다. 여기서 미설명부호 40은 패시베이션막(40) 이다.Next, as shown in FIG. 6, a barrier metal (not shown) and a metal are deposited on the resultant, and patterned to cover both the polysilicon layer 60 and the tungsten plug 22 below. ). Here, reference numeral 40 is a passivation film 40.

이상에서 상세히 설명한 바와 같이, 본 발명에 따른 멀티-플로빙용 패드는 최종 메탈층의 침적 전에 콘택으로 작용하는 텅스텐플러그 위에 폴리실리콘층을 형성하여 멀티-플로빙으로 인해 최악의 경우 발생할 수 있는 메탈 손상에 의한 절연막의 노출가능성을 없앰으로써 안정된 패드 콘택을 얻을 수 있음은 물론 와이어 본딩시의 접착력 저하를 방지할 수 있는 것이다.As described in detail above, the pad for multi-floving according to the present invention forms a polysilicon layer on a tungsten plug which acts as a contact before deposition of the final metal layer, thereby causing the worst case metal damage due to multi-floving. By eliminating the possibility of exposure of the insulating film by the above-described method, a stable pad contact can be obtained as well as a reduction in adhesion force during wire bonding can be prevented.

Claims (4)

소정의 반도체 소자가 형성된 반도체 기판과, 상기 기판의 패드 영역 상부에 형성되는 제 1 메탈층과, 상기 제 1 메탈층의 상부에 형성되며 상부로부터 하부 제 1메탈층까지 수개의 비아홀이 형성되는 절연막과, 상기 비아홀 내에 충진되는 텅스텐플러그들과, 상기 절연막의 상부에 적어도 한 개 이상의 텅스텐플러그가 노출되도록 적층되는 폴리실리콘층과, 상기 폴리실리콘층과 노출된 텅스텐플러그가 덮히도록 형성되는 제 2 메탈층을 포함하는 멀티-플로빙용 패드.A semiconductor substrate having a predetermined semiconductor element formed thereon, an insulating layer having a first metal layer formed over the pad region of the substrate, and a plurality of via holes formed over the first metal layer and formed from an upper portion to a lower first metal layer. And a tungsten plug filled in the via hole, a polysilicon layer stacked to expose at least one tungsten plug on the insulating layer, and a second metal formed to cover the polysilicon layer and the exposed tungsten plug. A pad for multi-floving comprising a layer. 제 1 항에 있어서, 상기 폴리실리콘층은 두께가 500∼1000Å인 것을 특징으로 하는 멀티-플로빙용 패드.The multi-floating pad of claim 1, wherein the polysilicon layer has a thickness of 500 to 1000 microseconds. 소정의 반도체 소자가 형성된 반도체 기판의 상부에 제 1 메탈층과 절연막을 순차적으로 적층하는 단계와, 상기 절연막 상부로부터 제 1 메탈층이 노출되도록 복수개의 비아홀을 형성하는 단계와, 상기 결과물 상에 텅스텐을 침적하고 평탄화하여 비아홀 내에 텅스텐 플러그를 형성하는 단계와, 상기 결과물 상에 폴리실리콘을 침적하고 패드 영역을 제외한 부분을 식각하여 제거하는 단계와, 상기 결과물 상에 제 2 메탈층을 증착하고 패터닝하는 단계를 포함하는 멀티-플로빙용 패드의 제조방법.Sequentially stacking a first metal layer and an insulating layer on a semiconductor substrate on which a predetermined semiconductor element is formed, forming a plurality of via holes to expose the first metal layer from an upper portion of the insulating layer, and tungsten on the resultant Depositing and planarizing to form a tungsten plug in the via hole, depositing polysilicon on the resultant, etching and removing portions other than the pad area, and depositing and patterning a second metal layer on the resultant. Method for producing a pad for multi-floving comprising the step. 제 3 항에 있어서, 상기에서 폴리실리콘은 플라즈마 방법으로 침적하는 것임을 특징으로 하는 멀티-플로빙용 패드의 제조방법.The method of claim 3, wherein the polysilicon is deposited by a plasma method.
KR1019970032573A 1997-07-14 1997-07-14 Multi-probing pad and fabricating method thereof to form stable pad contact and avoid decrease of adhesion in wire bonding process KR100439835B1 (en)

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JPS61100951A (en) * 1984-10-22 1986-05-19 Nec Corp Semiconductor device
JPS63198346A (en) * 1987-02-13 1988-08-17 Matsushita Electronics Corp Semiconductor integrated circuit
JPH05121542A (en) * 1991-10-28 1993-05-18 Matsushita Electron Corp Semiconductor device
KR19990008511A (en) * 1997-07-01 1999-02-05 문정환 Test pattern pad structure and its formation method

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JPS61100951A (en) * 1984-10-22 1986-05-19 Nec Corp Semiconductor device
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JPH05121542A (en) * 1991-10-28 1993-05-18 Matsushita Electron Corp Semiconductor device
KR19990008511A (en) * 1997-07-01 1999-02-05 문정환 Test pattern pad structure and its formation method

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