JP2006332444A - Method of manufacturing semiconductor wafer and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent inter-wiring short circuit caused by separation of a conductive film remaining in a groove of an accessory pattern, with respect to the accessory pattern to be formed on a scribing line region. <P>SOLUTION: A dummy conductive layer 34a for covering a slit-like groove 28 forming the accessory pattern 50 formed in the scribing line region 13 is formed. The dummy conductive layer 34a covers a sidewall-like conductive film 30 remaining in the groove 28 of the accessory pattern 50 after a process such as CMP (chemical mechanical polishing) for forming a conductive plug in a contact hole 28 of an element forming region 12, thereby preventing the inter-wiring short circuit caused by the separation of a conductive film including the sidewall-like conductive film 30 in a subsequent process. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor wafer and a semiconductor device, and in particular, a semiconductor wafer having an accessory pattern such as a slit-shaped or hole-shaped alignment mark or an alignment accuracy measurement mark on a scribe line region, and such a semiconductor device. It relates to the manufacturing method.

  With the demand for higher integration of semiconductor integrated circuits such as LSIs, CMP (Chemical Mechanical Polishing) technology is used as one of planarization techniques for realizing higher integration. For example, when a conductive plug is formed inside a contact hole or a via hole (this specification is collectively referred to as a contact hole) formed in an insulating film, insulation including the inside of the contact hole is included. Tungsten or polysilicon is formed on the entire surface of the film, and then CMP is performed until the insulating film is exposed. As a result, a plug such as blanket tungsten or polysilicon is formed inside the fine contact hole, and the surface of the plug and the insulating film is flattened.

  By the way, when manufacturing a semiconductor device such as a semiconductor integrated circuit device using a semiconductor substrate, in general, an alignment mark or a reference for positioning in various processing steps applied to the semiconductor substrate is used. A semiconductor substrate that is different from an element formation region of a semiconductor substrate for forming a semiconductor device as a product by using an accessory pattern such as a positioning accuracy measurement pattern that becomes a reference for measuring the positioning accuracy after patterning It is formed in the scribe line region. Such an accessory pattern is formed in the same process as these films when an insulating film or a conductive film constituting the semiconductor device is formed.

  8A and 8B are a plan view and a cross-sectional view illustrating one process step of a conventional accessory pattern formed in a scribe line region of a semiconductor substrate, respectively. FIGS. 9A and 9B are a plan view and a cross-sectional view showing process steps in the scribe line region subsequent to FIGS. 8A and 8B, respectively. In these drawings, reference numeral 12 denotes an element formation region, and reference numeral 13 denotes a scribe line region.

  As shown in FIGS. 8A and 8B, in the accessory pattern 50 on the scribe line region 13, the contact hole 28 constituting the accessory pattern 50 is exposed on the surface before and after the formation of the thin conductive film. Thus, it is formed as a groove having a slit shape or the like having a width of, for example, several μm to several tens of μm, which is larger than the fine-sized contact hole formed in the element formation region. For this reason, when a contact hole is formed in the element formation region 12, a conductive film made of, for example, a blanket tungsten layer is deposited, and a contact plug is formed by CMP polishing, the scribe line region 13 is dished during CMP polishing. As a result, blanket tungsten or the like may remain as the sidewall-like conductive film 30 on the side wall of the slit-shaped contact hole constituting the accessory pattern. In some cases, it may be left in the form of scrap from the bottom to the side wall.

  As described above, the conductive film 30 left on the side wall of the slit-shaped contact hole 28 has low adhesion with the side wall of the contact hole. In the element forming region 12, an upper wiring layer made of aluminum wiring or the like is formed, and at the same time, an upper wiring layer such as aluminum wiring is directly deposited in the contact hole 28 constituting the accessory pattern. Then, etching is performed almost over the entire accessory pattern. At this time, in general, excessive etching is performed on the slit-shaped contact hole 28 formed in the scribe line region 13. As a result, a conductive film such as blanket tungsten and aluminum wiring for forming a contact plug is left in a sidewall shape on the side wall portion of the accessory pattern 50, and the sidewall-shaped conductive film, the slit-shaped contact hole 28, The adhesion between the two is further reduced.

Patent Document 1 and Patent Document 2 describe the technique for forming an accessory pattern such as TEG in the scribe line region.
JP-A-6-295054 JP 2003-332270 A

  In the steps of FIGS. 8A and 8B, an upper wiring layer 34 is deposited, and after the etching step of patterning the wiring layer 34, as shown in FIGS. As a result, a pattern of the conductive film 340 including the conductive film 30 and the upper wiring layer 34 is left, and the remaining pattern is peeled off from the side wall of the contact hole 28 in a later process. The peeled conductive film 340 penetrates into the element formation region 12 and becomes dust, causing a reduction in the yield of the semiconductor device such as short-circuiting between the wirings.

  In view of the problem of the accessory pattern in the above-described conventional semiconductor device, the present invention prevents the peeling of the conductive film formed in a sidewall shape in the accessory pattern, and thus a semiconductor wafer having a high yield, and such a semiconductor wafer. An object of the present invention is to provide a semiconductor device manufacturing method capable of manufacturing a semiconductor wafer.

To achieve the above object, a semiconductor wafer of the present invention is a semiconductor wafer in which a plurality of element formation regions and a scribe line region that partitions the plurality of element formation regions are formed.
The scribe line region is formed in the same layer as the insulating layer in the element forming region, and has an insulating layer pattern in which a groove having a larger cross-sectional area than a contact hole in the element forming region is formed, and at least the groove A first conductive layer left on the surface of the side wall portion, and a dummy conductive layer pattern formed on the same layer as the wiring layer in the element formation region, covering at least the surface of the groove together with the first conductive layer. An accessory pattern is provided.

In addition, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a plurality of element forming regions and a scribe line region that partitions the plurality of element forming regions are formed on a semiconductor wafer.
Depositing an insulating layer on the element formation region and the scribe line region;
Patterning the insulating layer to form a contact hole in the insulating layer in the element formation region, and forming an accessory pattern having a groove having a larger cross section than the contact hole in the insulating layer in the scribe line region; When,
Depositing a conductive layer on at least the insulating layer including the inside of the contact hole and on the accessory pattern;
Processing the conductive layer by CMP or etchback to form a contact plug that fills the contact hole;
Depositing a wiring layer on at least the insulating layer, the contact plug, and the accessory pattern;
Patterning the wiring layer to form a wiring pattern in the element formation region, and forming a dummy conductive layer pattern covering at least the groove and the conductive layer portion remaining in the groove. And

  According to the semiconductor wafer of the present invention and the semiconductor device manufacturing method of the present invention, the conductive layer and the wiring layer left in the groove are covered by covering the groove and the conductive layer left in the groove with the dummy conductive layer pattern. Since the portion is prevented from being peeled off from the side wall of the groove, it is possible to prevent a short circuit between wirings due to the peeled-off conductive layer and the like, and there is an effect that a semiconductor wafer can be manufactured with a high manufacturing yield.

  Here, in the semiconductor wafer of the present invention, the accessory pattern is configured as, for example, an alignment mark, a positioning accuracy measurement mark, or a TEG.

  In a preferred aspect of the semiconductor wafer of the present invention, the dummy conductive layer pattern is partially etched away on the insulating layer pattern outside the groove. In this case, the stress acting between the dummy conductive layer pattern and the insulating layer pattern is reduced, and cracks and the like generated in the insulating layer pattern can be prevented.

  Instead of the above configuration, it is also possible to adopt a mode in which the dummy conductive layer pattern is formed substantially uniformly on the insulating layer pattern including the inside and outside of the groove. In this case, the shape of the mask for patterning the accessory pattern is simplified.

  When the semiconductor wafer of the present invention is applied to an accessory pattern having a particularly large shape in which the cross section of the groove has a slit shape, the effect is great.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view showing a part of a semiconductor wafer 10 according to an embodiment of the present invention. Normally, in the manufacture of semiconductor devices, as shown in FIG. 1, a semiconductor wafer 10 is formed by sequentially laminating patterns formed of various materials such as a metal film, a semiconductor film, and an insulator film on a semiconductor substrate 11. The element formation region 12 in which a fine semiconductor element such as is formed and the adjacent element formation region 12 are divided into a scribe line region 13 that divides each element formation region 12 and surrounds each element formation region 12. In the scribe line region 13, an accessory pattern formation region 14 in which accessory patterns such as alignment marks, alignment accuracy measurement marks, and TEG (Test Element Group) are formed without increasing the chip area.

  2 to 5 sequentially show the steps for manufacturing the semiconductor wafer of the above embodiment, and FIG. 2A is a partial sectional view of an element formation region 12 for forming a semiconductor device as a product. FIGS. 2B and 2C are a plan view and a cross-sectional view of the scribe line region 13, respectively. Note that FIG. (A) is omitted in some of the process steps.

In each drawing of FIG. 2, reference numeral 20 denotes a semiconductor substrate made of P-type silicon, and an interlayer insulating film 21, a first wiring layer 25, and a photoresist mask 26 are sequentially formed on the semiconductor substrate 20. These laminated structures are similarly formed in the accessory pattern forming region 14 formed in the scribe line region 13. The interlayer insulating film 21 is made of, for example, a SiO ₂ film, a TEOS (Tetra Ethyl Ortho Silicate) film, a BPSG (Borophospho Silicate Glass) film, etc., and has a thickness of about 4300 nm to 4800 nm. In the element formation region 12, the interlayer insulating film 21 is composed of an interlayer insulating film of at least three layers such as an interlayer insulating film that insulates the semiconductor element, the word line, and the bit line from each other, although not shown. The semiconductor elements, word lines, and bit lines are formed only in the element formation region 12, and semiconductor elements such as transistors are not formed in the scribe line region 13 including the accessory pattern formation region 14. Reference numeral 15 denotes the center of the scribe line region 13. In this embodiment, the accessory pattern is formed in a width region that is ½ of the width of the scribe line region 12.

  The first upper wiring layer 25 includes a barrier metal layer 22 made of a Ti / TiN wiring layer having a thickness of about 20 nm and 30 nm, an aluminum wiring layer 23 having a thickness of about 270 nm, and a TiN wiring having a thickness of about 50 nm. The antireflection film 24 is composed of layers. 2A shows a state in which the photoresist mask 26 in the element formation region 12 is patterned so as to have a predetermined wiring layer pattern. FIGS. 2B and 2C show the pattern in the scribe line region 13. FIG. This shows a state in which all of the photoresist is removed. As shown in these drawings, a circuit pattern including the first upper wiring layer 25 only in the element formation region 12 by patterning the first upper wiring layer 25 using photolithography technology and etching technology. Form.

Next, as shown in FIGS. 3A to 3C, an insulating film (for example, HDP: High Density Plasma film or the like) having a thickness of about 1000 nm is deposited on the entire surface and flattened by using a CMP (Chemical Mechanical Polishing) technique. Then, an interlayer insulating film 27 is formed by depositing an oxide film (for example, Plasma SiO ₂ film) having a thickness of about 300 nm thereon. At this time, the thickness of the interlayer insulating film 27 is about 700 nm. Further, in the element formation region 12, the diameter of the element formation region 12 is set to be electrically connected to each other by using the photolithography technique and the etching technique, and the second upper layer wiring layer 34 to be formed later. A contact hole 28 of about 0.3 μm is formed. At the same time, a plurality of slit-shaped contact holes 28 having, for example, a width of about 6 μm and a length of about 40 μm are formed at predetermined positions in the scribe line region 13.

  Subsequently, a barrier metal layer 29 made of a TiN wiring layer and having a thickness of about 50 nm and a blanket tungsten layer 30 having a thickness of about 300 nm are sequentially deposited on the entire surface, thereby completely forming the contact hole 28 formed in the element formation region 12. Embed in. At this time, the blanket tungsten layer 30 cannot completely fill the slit pattern 28 in the accessory pattern formation region 14 having a sufficiently large diameter as compared with the film thickness. It is formed in an uneven pattern.

  Next, as shown in FIGS. 4A to 4C, the blanket tungsten 30 deposited on the interlayer insulating film 27 is removed by using etch back by CMP technique or anisotropic dry etching technique. As a result, a contact plug 30 filling the contact hole 28 is formed in the element formation region 12. At this time, the same etching process is also performed on the contact hole 28 constituting the alignment mark 50 at the same time. However, the blanket tungsten 30 in the alignment mark 50 which is relatively shallow and has a width (cross-sectional area) as large as several μm to several tens of μm is the side wall of the contact hole 28 constituting the slit pattern by dishing during CMP polishing. It remains in the form of trash from the bottom to the bottom. When plug formation is performed by etch back, a part of the blanket tungsten 30 is left as a sidewall-like conductive film on the side wall portion of the contact hole 28 formed of a slit pattern.

  As shown in FIGS. 4A to 4C, a barrier metal layer 31 comprising a Ti / TiN wiring layer having a thickness of about 30 and 100 nm and constituting the second upper wiring layer 34 is then formed. An antireflection film 33 composed of an aluminum wiring layer 32 having a thickness of about 800 nm and a TiN wiring layer having a thickness of about 25 nm is sequentially deposited. Further, after a photoresist film is applied on the entire surface, a mask pattern 35 having a circuit pattern is formed in the element formation region 12 by photolithography. At the same time, a lid-like mask pattern 35 having an overlap margin of about 2.5 to 5 μm is formed in the scribe line region 13 to cover the entire surface of the accessory pattern 50 including the inside of the contact hole 28. To do.

  Next, as shown in FIGS. 5A to 5C, the barrier metal layer 31, the aluminum wiring layer 32, and the antireflection film 33 are patterned by an etching technique using the mask pattern 35 to form an element. In the region 12, a circuit pattern composed of the second upper wiring layer 34 is formed, and in the accessory pattern formation region 14, a protective pattern 34 a for the alignment mark 50 and the like is formed.

  In the conventional method, as shown in FIGS. 8A and 8B, since the contact hole 28 constituting the accessory pattern 50 is exposed, an element pattern formed of the second upper wiring layer 34 is used. When forming, the contact hole 28 is excessively etched. This is because a certain amount of over-etching is required to prevent short-circuiting between the wiring patterns due to etching residue. As a result, the adhesion of the sidewall-like conductive film 340 (the blanket tungsten 30 and the second upper wiring layer 34) formed in the slit-shaped contact hole 28 in the scribe line region 13 is reduced, In the peeling process, the residual film on the fuse, the antireflection film on the bonding PAD for assembly, and the etching process for the purpose of removing the passivation film, generation of dust due to pattern peeling of the sidewall-like conductive film 340 There have been drawbacks such as a reduction in yield due to short-circuit between wires.

  In the above-described embodiment, the entire slit-shaped contact hole 28 constituting the accessory pattern 50 such as an alignment mark formed at a predetermined position in the scribe line region 13 is covered with the protective pattern 34a patterned by the photoresist technique. It has a structure. Thereby, without adding the number of conventional steps, the side wall-like conductive film 30 formed on the side wall portion of the slit-shaped contact hole 28, or the waste shape left on the side wall from the bottom of the contact hole 28 It is possible to prevent pattern peeling of the conductive film 30 and the like, and to easily prevent a decrease in yield in the semiconductor device manufacturing process.

  FIGS. 6B and 6C are a plan view and a cross-sectional view showing one step in the manufacturing method of the modified example from the manufacturing method of the embodiment, respectively, and FIGS. 4B and 4C of the embodiment. It is shown as a process step corresponding to the process step shown in FIG. FIGS. 7B and 7C are views showing process steps subsequent to the process steps shown in FIGS. 6B and 6C, respectively, and FIGS. 5B and 5C in the above embodiment. It is shown as a process step corresponding to the process step shown in FIG.

  In this modification, the mask pattern 35 for patterning the second upper wiring layer 34 is the same as the mask pattern 35 of the above embodiment in the element formation region 12, but in the scribe line region 13, FIG. As shown to (c), the structure which covers not only the whole accessory pattern 50 but the part is employ | adopted. Specifically, in this modification, as shown in FIG. 6, the mask pattern 35 is formed so as to individually cover each contact hole 28 and its periphery. Therefore, in the step of patterning the second wiring layer 34, etching is performed using the mask pattern 35, whereby the protective pattern 34a shown in FIGS. 7B and 7C is obtained. This protective pattern prevents the side wall-like conductive film 30 and the like from being peeled off, similarly to the structure obtained by the manufacturing method of the above embodiment. Further, since each contact hole 28 is individually covered, it is possible to reduce the stress generated between the protective conductive film 34a and the interlayer insulating film 27 as compared with the above embodiment, and the interlayer caused by the stress can be reduced. The generation of cracks in the insulating film 27 is prevented.

  As described above, in the method for manufacturing a semiconductor device of the present invention, the entire region of the accessory pattern 50 having a plurality of slit-shaped or hole-shaped grooves formed in the scribe line region 13 or a part thereof. A structure is intentionally covered with the conductive film (second wiring layer) 34 in the subsequent semiconductor device manufacturing process. This prevents peeling of the sidewall-like conductive film 340 left on the groove sidewall of the accessory pattern 50 in the process of forming a plug in a relatively shallow contact hole of, for example, about 500 nm to 1000 nm by CMP, etch back, or the like. . In particular, as shown in the above-described modification, the protective conductive film 34a and the lower layer for the purpose of preventing peeling are formed by covering only a part of the accessory pattern 50 (the slit pattern portion or the hole pattern portion and its vicinity). It is possible to reduce the stress generated between the interlayer insulating film 27, prevent the occurrence of cracks due to the stress, and prevent the side wall-like conductive film from peeling off.

  In the present invention, an alignment mark, an alignment accuracy measurement mark, or the like, which is a slit-shaped or hole-shaped accessory pattern 50 formed at a predetermined position on the scribe line region 13 without particularly adding the number of conventional processes. Pattern peeling of the sidewall-like conductive film 340 or the like generated from the side wall of the substrate can be prevented. For this reason, it is possible to prevent a decrease in yield due to a short circuit between wirings in a later process.

  In the above-described embodiment, the alignment mark is described as an example of the accessory pattern, but the present invention is an accessory pattern other than the alignment mark, for example, an alignment pattern such as a positioning accuracy measurement mark or a TEG, The present invention can be applied to an accessory pattern having a groove (hole) having a larger cross-sectional area than a contact hole in an element formation region.

  The semiconductor device manufacturing method of the present invention can be applied to general manufacturing of semiconductor integrated circuit devices including memory devices such as DRAMs and SRAMs.

1 is a plan view showing a part of a semiconductor wafer according to an embodiment of the present invention. FIGS. 2A to 2C are cross-sectional views of an element formation region and a plane of a scribe line region, respectively, illustrating steps of a manufacturing process according to an embodiment of the present invention for manufacturing the semiconductor wafer of FIG. The figure and sectional drawing of a scribe area | region. FIG. 3 is a diagram illustrating a process step subsequent to FIG. 2 of the manufacturing process according to an embodiment of the present invention for manufacturing the semiconductor wafer of FIG. 1, wherein (a) to (c) are cross-sectional views of an element formation region, The top view of a scribe line area | region, and sectional drawing of a scribe area | region. FIG. 4 is a diagram illustrating a process step subsequent to FIG. 3 of the manufacturing process according to the embodiment of the present invention for manufacturing the semiconductor wafer of FIG. 1, wherein (a) to (c) are cross-sectional views of an element formation region, The top view of a scribe line area | region, and sectional drawing of a scribe area | region. FIGS. 5A to 5C are cross-sectional views of an element formation region, each showing a process step subsequent to FIG. 4 of the manufacturing process according to the embodiment of the present invention for manufacturing the semiconductor wafer of FIG. The top view of a scribe line area | region, and sectional drawing of a scribe area | region. FIGS. 2A and 2B are diagrams showing one step of a manufacturing process of a modified example from the embodiment for manufacturing the semiconductor wafer of FIG. 1, and FIGS. 2B and 2C are a plan view and a sectional view of a scribe line region, respectively. FIGS. FIGS. 7A and 7B are diagrams showing a process step subsequent to FIG. 6 of the process of manufacturing the semiconductor wafer of FIG. 1, and FIGS. 7B and 7C are a plan view and a cross-sectional view of a scribe line region, respectively. FIGS. It is a figure which shows the 1 process step of the process which manufactures the conventional semiconductor wafer, (a) And (b) is the top view and sectional drawing of an accessory pattern, respectively. FIGS. 9A and 9B are diagrams illustrating a process step subsequent to FIG. 8 of a process for manufacturing a conventional semiconductor wafer, in which FIGS.

Explanation of symbols

10 Semiconductor wafer 11 Substrate
12 Element formation region 13 Scribe line region 14 Accessory pattern formation region
15 Scribe line area center line 20 Silicon substrate (semiconductor substrate)
21 Interlayer insulating films 22 and 31 Barrier metal layer (Ti / TiN)
23, 32 Aluminum wiring layers 24, 33 Antireflection film (TiN)
25, 34 Upper wiring layer 34a Protection pattern (for etching)
26, 35 Photoresist mask 27 Interlayer insulating film 28 Contact hole 29 Barrier metal layer (TiN)
30 Blanket tungsten layer (Side-walled conductive film)
340 Side wall-like conductive film 50 Accessory pattern (alignment mark, alignment accuracy measurement mark, etc.)

Claims (6)

In a semiconductor wafer in which a plurality of element formation regions and a scribe line region that partitions the plurality of element formation regions are formed,
The scribe line region is formed in the same layer as the insulating layer in the element forming region, and has an insulating layer pattern in which a groove having a larger cross-sectional area than a contact hole in the element forming region is formed, and at least the groove A first conductive layer left on the surface of the side wall portion, and a dummy conductive layer pattern formed on the same layer as the wiring layer in the element formation region, covering at least the surface of the groove together with the first conductive layer. A semiconductor wafer comprising an accessory pattern.   The semiconductor wafer according to claim 1, wherein the insulating layer pattern constitutes an alignment mark.   The semiconductor wafer according to claim 1, wherein a part of the dummy conductive layer pattern is etched away on an insulating layer pattern outside the groove.   The semiconductor wafer according to claim 1, wherein the dummy conductive layer pattern is formed substantially uniformly on an insulating layer pattern including the inside and outside of the groove.   The semiconductor wafer according to claim 1, wherein a cross section of the groove has a slit shape. In a method for manufacturing a semiconductor device, wherein a plurality of element formation regions and a scribe line region that partitions the plurality of element formation regions are formed on a semiconductor wafer.
Depositing an insulating layer on the element formation region and the scribe line region;
Patterning the insulating layer to form a contact hole in the insulating layer in the element formation region, and forming an accessory pattern having a groove having a larger cross section than the contact hole in the insulating layer in the scribe line region; When,
Depositing a conductive layer on at least the insulating layer including the inside of the contact hole and on the accessory pattern;
Processing the conductive layer by CMP or etchback to form a contact plug that fills the contact hole;
Depositing a wiring layer on at least the insulating layer, the contact plug, and the accessory pattern;
Patterning the wiring layer to form a wiring pattern in the element formation region, and forming a dummy conductive layer pattern covering at least the groove and the conductive layer portion remaining in the groove. A method for manufacturing a semiconductor device.

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