KR100597087B1 - Method for fabricating semiconductor device - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor device that can secure a process margin in a via hole forming process by minimizing a step between a capacitor region and a logic region.

A method of manufacturing a semiconductor device according to a first embodiment of the present invention includes the steps of forming a first interlayer insulating film on a semiconductor substrate; and forming a trench by partially etching the first interlayer insulating film; Stacking a first metal layer on the first interlayer insulating film so as to fill it sufficiently, and then planarizing the first interlayer insulating film to form a lower electrode of the capacitor in the trench; and forming a dielectric film of the capacitor on the lower electrode. And stacking a second metal layer on the entire surface of the substrate including the dielectric layer; and selectively patterning the second metal layer to simultaneously pile dummy wiring on the upper electrode and the lower electrode of the capacitor on the dielectric layer. Forming an interlayer insulating film on an entire surface of the substrate including the upper electrode and the dummy wiring; Etching the constant region, including the step of forming a via hole exposing the upper electrode and the dummy wiring is characterized in that formed.

Capacitor, MIM

Description

Method for fabricating semiconductor device {Method for fabricating semiconductor device}             

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

Description of the main parts of the drawing

201: semiconductor substrate 202: first interlayer insulating film

206: first barrier metal layer 207a: lower electrode

207b: first contact plug 208: dielectric film

209: second barrier metal layer 210a: upper electrode

210b: dummy wiring 210c: first metal wiring

212: second interlayer insulating film 214: second contact plug

215: second metal wiring

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device that can secure a process margin in a via hole forming process by minimizing a step between a capacitor region and a logic region.

Capacitors are one of the most important parts of mixed signal ICs and RF applications. Capacitors in mixed-signal integrated circuits mainly use PIP (Poly-Silicon / Insulator / Poly-Silicon) capacitors, but PIP capacitors are not suitable for devices requiring very low power supply (Vcc), such as high frequency applications. In place of these PIP capacitors, recent MIM (Metal / Insulator / Metal) capacitors have been proposed. MIM capacitors can guarantee low power supply (Vcc) and have a high electrostatic density of 1fF / μm ² or more.

The technology for implementing such a MIM capacitor is as follows. 1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

First, as shown in FIG. 1A, a semiconductor substrate 101 is prepared. The semiconductor substrate 101 is largely defined as a capacitor region and a logic region. Although not shown in the figure, an analog element such as a transistor or the like is previously formed in the logic region. In this state, the first interlayer insulating film 102 is stacked on the entire surface of the substrate 101, and a predetermined portion of the first interlayer insulating film 102 is etched and removed to expose a lower device such as a transistor in the logic region. First via holes 103 are formed. Then, the first contact plug 104 is formed through the metal layer in the first via hole 103.

Subsequently, as illustrated in FIG. 1B, the first metal layer 105, the dielectric film 106, and the second metal layer are sequentially stacked. Then, the second metal layer is selectively patterned using a predetermined photoresist pattern to complete the upper electrode 107, which is one element constituting the capacitor. Subsequently, as shown in FIG. 1C, the dielectric layer 106 and the first metal layer 105 are selectively patterned using another photoresist layer pattern to form the upper electrode 107, the dielectric layer 106, and the lower electrode in the capacitor region. Completing a capacitor formed in the logic region is formed a first metal wiring electrically connected to the first contact plug 104.

In this state, as shown in FIG. 1D, a second interlayer insulating film is laminated on the entire surface of the substrate 101. Thereafter, the second interlayer insulating layer 108 is selectively patterned to expose predetermined portions of the upper electrode 107, the lower electrode 105a, and the first metal wire 105b, thereby forming a plurality of second via holes 109. To form. Then, the plurality of second contact plugs 110 connected to the upper electrode 107, the lower electrode 105a, and the first metal wire 105b, respectively, through the metal layers in the plurality of second via holes 109. When the second metal wiring 111 is formed on the second interlayer insulating layer 108 to be electrically connected to the second contact plug 110, the semiconductor device manufacturing method according to the related art is completed.

In the related art, the second via hole forming process of selectively etching and removing the second interlayer insulating film to expose the upper electrode, the lower electrode, and the first metal wiring may include: The depth of the second via holes is different from each other due to the step between the upper electrode and the first metal wire.

Accordingly, in the process of forming the second via hole by etching the second interlayer insulating layer, the upper electrode of the capacitor region located on the upper side is exposed in advance than the lower electrode of the capacitor region or the first metal wiring of the logic region, and thus the upper electrode of the capacitor region. This etching damages the problem occurs. In order to solve this problem, the conventional technology is to form a second via hole such as a first etching process exposing the upper electrode of the capacitor region and a second etching process exposing the lower electrode of the capacitor region and the first metal wiring of the logic region. A plurality of interlayer insulating film etching processes are employed.

However, as the plurality of second via hole forming processes are individually performed, the same process is performed twice because the contact mask, the contact manufacturing, and the mask removing process are separately performed in each region by separating the capacitor region and the analog circuit region. Since there is a problem that the number of manufacturing processes increases.                         

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can secure a process margin during the via hole forming process by minimizing the step difference between the capacitor region and the logic region.

A method of manufacturing a semiconductor device according to a first embodiment of the present invention for achieving the above object comprises the steps of: forming a first interlayer insulating film on a semiconductor substrate; and forming a trench by partially etching the first interlayer insulating film Stacking a first metal layer on the first interlayer insulating film to sufficiently fill the trench, and then planarizing the first interlayer insulating film to form a lower electrode of a capacitor in the trench; and the lower electrode Forming a dielectric film of a capacitor on the substrate; and stacking a second metal layer on the entire surface of the substrate including the dielectric film; and selectively patterning the second metal layer to form an upper electrode and a lower electrode of the capacitor on the dielectric film. Simultaneously forming a dummy wiring on an electrode; and stacking an interlayer insulating film on an entire surface of the substrate including the upper electrode and the dummy wiring. And forming a via hole exposing the upper electrode and the dummy wiring by etching a predetermined portion of the interlayer insulating layer.

A method of manufacturing a semiconductor device according to a second embodiment of the present invention includes forming a first interlayer insulating film on a semiconductor substrate; forming a trench by partially etching the first interlayer insulating film; and Stacking an insulating film for a first metal layer and a dielectric film on the first interlayer insulating film so as to sufficiently fill it, and then planarizing the first interlayer insulating film to form a lower electrode and a dielectric film of a capacitor in the trench; Stacking a second metal layer on the entire surface of the substrate; and selectively patterning the second metal layer to simultaneously form an upper electrode of a capacitor and a dummy wiring on the lower electrode on the dielectric layer; Stacking an interlayer insulating film on the entire surface of the substrate including electrodes and dummy wiring; and etching a predetermined portion of the interlayer insulating film to It characterized in that comprises a step of forming a via hole for exposing the upper electrode and the dummy wiring lines.

Preferably, the dielectric film may be formed to a thickness of 500 to 1000 GPa.

Preferably, the first metal layer may be composed of a tungsten layer.

Preferably, the second metal layer may be formed of an aluminum-copper alloy.

According to an aspect of the present invention, an upper electrode formed on the dielectric layer may be formed by forming a lower electrode or lower electrode constituting a capacitor and an interlayer dielectric layer in which a contact plug of a logic region is formed in a trench partially etched. Since the step and the metal wiring are hardly generated, the over-etching problem of the upper electrode can be prevented in the subsequent via hole forming process exposing the upper electrode and the metal wiring.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings. 2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention, and FIGS. 3A through 3F illustrate a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention. It is a process cross section.

In the manufacturing process of the semiconductor device according to the first embodiment of the present invention, first, as shown in FIG. 2A, a semiconductor substrate 201 defined by a capacitor region and a logic region is prepared. Although not shown, elements such as the logic region MOS transistor and the like are formed. In this state, a first interlayer insulating film 202 is laminated on the semiconductor substrate 201. The first interlayer insulating film 202 may be formed by using a TEOS-based oxide film such as low pressure tetra ethyl ortho silicate (LP-TEOS), O ₃ -TEOS, d-TEOS, or high density plasma CVD (High Density Plasma CVD). It can be formed using a layer of Fluorine Silicate Glass (FSG), Undoped Silicate Glass (USG) or SiH ₄ film or BPSG.

Thereafter, a photosensitive film is coated on the first interlayer insulating film 202 and is selectively patterned to expose the first interlayer insulating film 202 at a portion corresponding to the first via hole 204 region, thereby forming a first photosensitive film pattern 203. To form. Subsequently, by using the first photoresist pattern 203 as an etching mask, a predetermined portion of the first interlayer insulating layer 202 may be etched and removed to expose a lower device (not shown) such as a transistor in the logic region. One via hole 204 is formed.

In the state where the first via hole 204 is formed, as shown in FIG. 2B, a photosensitive film is coated on the entire surface of the substrate 201 and the first interlayer insulating film 202 of the portion corresponding to the trench 205 region is exposed. It is selectively patterned to form a second photoresist pattern. Next, the trench 205 is formed by etching and removing the first interlayer insulating layer 202 of the capacitor region by a predetermined thickness using the second photoresist pattern as an etching mask. The thickness of the first interlayer insulating film 202 is etched corresponds to the thickness of the lower electrode 207a of the capacitor formed by the subsequent process. Accordingly, the depth of the trench 205 is fluid, depending on the thickness of the lower electrode 207a of the capacitor, but is preferably about 3000 to 7000 Pa.

In this state, the first barrier metal layer 206 is stacked on the entire surface of the substrate 201 including the trench 205 and the first via hole 204. The first barrier metal layer 206 may be formed of a single layer of Ti or a double layer of Ti / TiN. In case of forming a dual layer of Ti / TiN, Ti layer deposition and metal organic chemical vapor deposition (hereinafter referred to as IMP) method or collimator sputtering method (Metal Organic Chemical Vapor Deposition) TiN deposition by the MOCVD method is performed sequentially. Thereafter, a first metal layer is deposited on the first barrier metal layer 206 to sufficiently fill the trench 205 and the first via hole 204. Here, a tungsten layer may be used as the first metal layer, and the thickness of the first metal layer may be 1.5 times or more than the diameter of the first via hole 204. Subsequently, the first metal layer is flattened on the first interlayer insulating film 202 by using a chemical mechanical polishing process or the like. Accordingly, a first contact plug 207b is formed in the first via hole 204 of the logic region, and a lower electrode 207a of the capacitor is completed in the trench 205 of the capacitor region.

In the state where the first contact plug 207b and the lower electrode 207a of the capacitor are completed, the dielectric film 208 is stacked on the entire surface of the substrate 201 as shown in FIG. 2C. The dielectric layer 208 may use a single layer such as a silicon oxide layer (SiO ₂ ), a silicon nitride layer (SiN _x ), a silicon oxynitride layer (SiON), or the like, and may also be configured as a double layer of a silicon nitride layer / silicon oxynitride layer. In addition, the dielectric film 208 is preferably laminated to a thickness of 500 ~ 1000Å.

In this state, the dielectric film 208 is selectively patterned so as to remain only at a predetermined portion of the lower electrode 207a of the capacitor, thereby completing the dielectric film 208 as one element constituting the capacitor. Then, the second barrier metal layer 209 and the second metal layer 210 are sequentially stacked on the entire surface of the substrate 201 including the patterned dielectric layer 208. Here, the second barrier metal layer 209 may be formed of a single layer of Ti or a double layer structure of Ti / TiN, like the first barrier metal layer 206, and the second metal layer 210 may be formed of aluminum-copper ( Al-Cu layer is preferable, and in addition to the aluminum-copper layer, platinum (Pt), ruthenium (Ru), iridium (Ir), and rhodium (Rt), which are weak in reactivity with the dielectric film 208 and have a high work function, are preferred. Metals such as Rh), osmium (Os) and the like can be used.

In this state, as shown in FIG. 2D, a photosensitive film is coated on the second metal layer 210, and then selectively patterned to form the upper electrode 210a of the capacitor, the first metal wiring 210c of the logic region, and A second photoresist pattern 211 defining a dummy wiring 210b electrically connected to the lower electrode 207a is formed. Subsequently, the exposed second metal layer 210 and the second barrier metal layer 209 other than the region defined above are etched and removed using the second photoresist pattern 211 as an etching mask. Accordingly, in the capacitor region, a dummy wiring for electrically connecting the second contact plug 214 and the lower electrode 207a to which the upper electrode 210a constituting the capacitor is completed and formed in a subsequent process ( 210b) is formed. The first metal wire 210c is formed in the logic region to be electrically connected to the first contact plug 207b.

As shown in the drawing, a step is almost generated between the upper electrode 210a, the dummy wiring 210b, and the first metal wiring 210c formed by the patterning of the second metal layer 210 and the second barrier metal layer 209. I never do that. This is because the lower electrode 207a is formed in the trench 205 formed by etching the first interlayer insulating layer 202.

In this state, as shown in FIG. 2E, a second interlayer insulating film 212 is laminated on the entire surface of the substrate 201 including the upper electrode 210a, the dummy wiring 210b, and the first metal wiring 210c. do. The second interlayer insulating film 212 may be made of a material usable for the first interlayer insulating film 202. Thereafter, a predetermined portion of the second interlayer insulating film 212 is etched and removed to form a plurality of second via holes 213. The upper electrode 210a, the dummy wiring 210b, and the first metal wiring 210c are exposed by the plurality of second via holes 213. Here, the heights of the respective second via holes 213 exposing the upper electrode 210a, the dummy wiring 210b, and the first metal wiring 210c as described above in the process of forming the second via hole 213 ( Since d1, d2, and d3 are almost similar, the upper electrode 210a is less likely to be overetched before the dummy wiring 210b or the first metal wiring 210c is exposed.

In the state where the plurality of second via holes 213 are formed, as shown in FIG. 2F, the metal layers are stacked on the second interlayer insulating film 212 to sufficiently fill the plurality of second via holes 213. A plurality of second contact plugs 214 are formed by planarizing the second interlayer insulating film 212. Subsequently, when the second metal wiring 215 is formed on the second interlayer insulating film 212 to be electrically connected to the second contact plug 214, the method of manufacturing a semiconductor device according to the first embodiment of the present invention Is done.

A method of manufacturing a semiconductor device according to a second embodiment of the present invention is as follows.

First, as shown in FIG. 3A, a semiconductor substrate 201 defined by a capacitor region and a logic region is prepared. Although not shown, elements such as the logic region MOS transistor and the like are formed. In this state, a first interlayer insulating film 202 is laminated on the semiconductor substrate 201. Next, as shown in FIG. 2A of the first embodiment of the present invention, first via holes 204 and trenches 205 are formed in the logic region and the capacitor region, respectively.

Then, as shown in FIG. 3B, a first barrier metal layer 206, a first metal layer, and a dielectric film 208 are formed on the first interlayer insulating film 202 including the trench 205 and the first via hole 204. Laminated sequentially. In this case, the dielectric film 208 is to be interposed in the trench 205 by a predetermined thickness, and thus, the first barrier metal layer 206, the first metal layer, and the dielectric film 208 stacked in the trench 205 are formed. The thickness must be taken into account. In this state, the dielectric film 208, the first metal layer, and the first barrier metal layer 206 are planarized on the first interlayer insulating film 202 by using a chemical mechanical polishing process or the like. Accordingly, a first electrode plug 207b is formed in the first via hole 204, and a lower electrode 207a including the first metal layer and the first barrier metal layer 206 is formed in the trench 205. The dielectric layer 208 constituting the capacitor is formed on the lower electrode 207a. Here, the materials constituting the first barrier metal layer 206, the first metal layer, and the dielectric film 208 may use the materials described in the first embodiment of the present invention.

In this state, as shown in FIG. 3C, the second barrier metal layer 209 and the second metal layer 210 are sequentially stacked on the entire surface of the substrate 201. In this case, the second barrier metal layer 209 and the second metal layer 210 may also be made of any one of the materials described in the first embodiment of the present invention. Then, as shown in FIG. 3D, a photoresist film is coated on the second metal layer 210, and then selectively patterned to form the upper electrode 210a of the capacitor, the first metal wiring 210c of the logic region, and the lower portion of the capacitor. A photosensitive film pattern defining a dummy wiring 210b electrically connected to the electrode 207a is formed. Subsequently, the exposed second metal layer 210 and the second barrier metal layer 209 other than the region defined above are etched and removed using the photoresist pattern as an etching mask. Accordingly, in the capacitor region, the dummy wiring for electrically connecting the second contact plug 214 and the lower electrode 207a, which is completed by the upper electrode 210a constituting the capacitor and formed by a subsequent process, is formed. 210b is formed. The first metal wire 210c is formed in the logic region to be electrically connected to the first contact plug 207b.

As shown in the drawing, the step is the same between the upper electrode 210a, the dummy wiring 210b, and the first metal wiring 210c formed by the patterning of the second metal layer 210 and the second barrier metal layer 209. . This is because the lower electrode 207a and the dielectric film 208 of the capacitor are formed in the trench 205 formed by etching the first interlayer insulating film 202.

In this state, as shown in FIG. 3E, a second interlayer insulating film 212 is laminated on the entire surface of the substrate 201 including the upper electrode 210a, the dummy wiring 210b, and the first metal wiring 210c. do. The second interlayer insulating film 212 may be made of a material usable for the first interlayer insulating film 202. Thereafter, a predetermined portion of the second interlayer insulating film 212 is etched and removed to form a plurality of second via holes 213. The upper electrode 210a, the dummy wiring 210b, and the first metal wiring 210c are exposed by the plurality of second via holes 213. Here, the heights of the respective second via holes 213 exposing the upper electrode 210a, the dummy wiring 210b, and the first metal wiring 210c as described above in the process of forming the second via hole 213 ( Since d1, d2, and d3 are the same, there is no possibility that the upper electrode 210a is overetched before the dummy wiring 210b or the first metal wiring 210c is exposed.

In the state where the plurality of second via holes 213 are formed, as shown in FIG. 2F, the metal layers are stacked on the second interlayer insulating film 212 to sufficiently fill the plurality of second via holes 213. A plurality of second contact plugs 214 are formed by planarizing the second interlayer insulating film 212. Subsequently, when the second metal wiring 215 is formed on the second interlayer insulating film 212 to be electrically connected to the second contact plug 214, the method of manufacturing a semiconductor device according to the second embodiment of the present invention Is done.

The method of manufacturing a semiconductor device according to the present invention has the following effects.

The lower electrode or lower electrode constituting the capacitor and the dielectric film are formed in the trench where the contact plugs of the logic regions are formed in the partially etched trench, whereby the upper electrodes formed on the dielectric films hardly generate a step with the metal wiring of the logic region. In this case, the over-etching problem of the upper electrode may be prevented in a subsequent via hole forming process exposing the upper electrode and the metal wiring. Accordingly, it is possible to secure a process margin in the manufacturing process of the semiconductor device.

Claims (5)

Forming a first interlayer insulating film on the semiconductor substrate; Partially etching the first interlayer dielectric layer to form a trench; Stacking a first metal layer on the first interlayer insulating film to sufficiently fill the trench, and then planarizing the first interlayer insulating film to form a lower electrode of the capacitor in the trench; Forming a dielectric film of a capacitor on the lower electrode; Depositing a second metal layer on an entire surface of the substrate including the dielectric layer; Selectively patterning the second metal layer to simultaneously form a dummy wiring on an upper electrode and a lower electrode of a capacitor on the dielectric layer; Stacking an interlayer insulating film on an entire surface of the substrate including the upper electrode and the dummy wiring; And forming a via hole for exposing the upper electrode and the dummy wiring by etching a predetermined portion of the interlayer insulating film. Forming a first interlayer insulating film on the semiconductor substrate; Partially etching the first interlayer dielectric layer to form a trench; Stacking an insulating film for a first metal layer and a dielectric film on the first interlayer insulating film so as to sufficiently fill the trench, and then planarizing the first interlayer insulating film to form a lower electrode and a dielectric film of the capacitor in the trench; Depositing a second metal layer on an entire surface of the substrate including the dielectric layer; Selectively patterning the second metal layer to simultaneously form a dummy wiring on an upper electrode and a lower electrode of a capacitor on the dielectric layer; Stacking an interlayer insulating film on an entire surface of the substrate including the upper electrode and the dummy wiring; And forming a via hole for exposing the upper electrode and the dummy wiring by etching a predetermined portion of the interlayer insulating film. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the dielectric film is formed to a thickness of 500 to 1000 GPa. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the first metal layer comprises a tungsten layer. The method of claim 1, wherein the second metal layer is formed of an aluminum-copper alloy.

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