KR20040022627A - Method for forming contact hole of a semiconductor - Google Patents
Method for forming contact hole of a semiconductor Download PDFInfo
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- KR20040022627A KR20040022627A KR1020020054235A KR20020054235A KR20040022627A KR 20040022627 A KR20040022627 A KR 20040022627A KR 1020020054235 A KR1020020054235 A KR 1020020054235A KR 20020054235 A KR20020054235 A KR 20020054235A KR 20040022627 A KR20040022627 A KR 20040022627A
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- contact hole
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- insulating film
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- interlayer insulating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
Abstract
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 콘택홀 또는 비아홀 형성하기 위해 층간 절연막 상에 도포되는 포토레지스트의 클랙(crack) 현상을 방지할 수 있는 반도체 소자의 콘택홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming contact holes in semiconductor devices capable of preventing cracks in photoresist applied on an interlayer insulating film for forming contact holes or via holes. will be.
일반적으로 반도체 소자의 제조 공정에서 반도체 기판 상에 1층만의 배선에서는 배선 패턴 설계상의 자유도가 작아, 실질적인 배선이 길어짐으로써 반도체 기판 내 소자의 레이아웃에도 큰 제약이 가해진다.In general, only one layer of wiring on a semiconductor substrate in the manufacturing process of a semiconductor device has a small degree of freedom in designing a wiring pattern, and since the actual wiring becomes long, a great restriction is placed on the layout of the elements in the semiconductor substrate.
이것에 반해서 금속 배선을 다층화하면 아주 효율이 높은 설계가 가능하다. 즉, 반도체 칩 위에 배선을 통과시키는 스페이스를 고려하지 않고 각 반도체 소자가 레이아웃 되기 때문에 집적도 및 밀도가 향상되어 반도체 칩 사이즈가 축소된다. 그리고, 배선의 자유도가 증가하고, 패턴 설계가 용이해짐과 함께 배선 저항이나 전류 용량 등의 설정을 여유를 가지고할 수 있게 된다.On the other hand, multi-layered metal wiring enables a highly efficient design. That is, since each semiconductor element is laid out without considering the space for allowing wiring to pass on the semiconductor chip, the degree of integration and density are improved and the size of the semiconductor chip is reduced. This increases the degree of freedom in wiring, facilitates pattern design, and allows setting of wiring resistance, current capacity, and the like with a margin.
최근, 반도체 집적회로의 고집적화, 고성능화에 따라서 새로운 미세 가공 기술이 개발되고 있다. 화학기계연마법도 그 일예이고, LSI 제조공정, 특히 다층배선 형성공정에서의 층간 절연막의 평탄화, 금속플러그 형성, 매립배선형성에 있어서 빈번하게 이용되는 기술이다. 이 기술은, 예컨대 미국특허 제4,944,836호 공보에 개시되어 있다.Recently, new microfabrication technologies have been developed in accordance with high integration and high performance of semiconductor integrated circuits. Chemical mechanical polishing is one example, and is a technique frequently used in planarization of interlayer insulating films, metal plug formation, and buried wiring formation in LSI manufacturing processes, particularly in the formation of multilayer wirings. This technique is disclosed, for example, in US Pat. No. 4,944,836.
이하, 첨부된 도면을 참조하여 종래의 반도체 소자의 금속 배선 형성 방법을 설명한다. 도 1a 내지 도 1d는 종래 기술에 의한 반도체 소자의 금속 배선을 형성하는 방법을 순차적으로 나타내는 공정 단면도로서, 여기에서는 금속 배선을 수직으로 연결하는 콘택홀의 제조 공정에 대해 설명한다.Hereinafter, a metal wire forming method of a conventional semiconductor device will be described with reference to the accompanying drawings. 1A to 1D are cross-sectional views sequentially illustrating a method of forming a metal wiring of a semiconductor device according to the prior art, and a manufacturing process of a contact hole for vertically connecting a metal wiring will be described.
도 1a에 도시된 바와 같이, 반도체 기판(1) 상부 전면에 층간 절연막(3)을 증착하고, 화학 기계적 연마(chemical mechanical polishing, CMP)에 의해 평탄화한다. 이때, 반도체 기판(1)에는 STI(shallow trench isolation) 방법이나 LOCOS(local oxidation of silicon) 방법 등에 의한 필드 산화막과 반도체 소자가 형성될 활성 영역(active area)을 정의되어 있으며, 정의된 반도체 기판(1)의 활성영역에는 반도체 소자 제조 공정에 따라 게이트 전극(G), 소스 전극(S), 드레인 전극(D)을 포함하는 반도체 소자(2)가 형성되어 있다.As shown in FIG. 1A, an interlayer insulating film 3 is deposited on the entire upper surface of the semiconductor substrate 1 and planarized by chemical mechanical polishing (CMP). In this case, the semiconductor substrate 1 defines a field oxide film and an active area in which the semiconductor device is to be formed by a shallow trench isolation (STI) method, a local oxidation of silicon (LOCOS) method, or the like. In the active region of 1), a semiconductor device 2 including a gate electrode G, a source electrode S, and a drain electrode D is formed in accordance with a semiconductor device manufacturing process.
여기서, 반도체 기판(1) 상부에 증착되는 층간 절연막(3)으로는 PMD(pre-metal dielectric)막 또는 IMD(inter-metal dielectric)막이 있다.Here, the interlayer insulating film 3 deposited on the semiconductor substrate 1 includes a pre-metal dielectric (PMD) film or an inter-metal dielectric (IMD) film.
도 1b에 도시된 바와 같이, 층간 절연막(3) 상부에 콘택(contact) 패턴(4)을 형성하고, 콘택 패턴(4)에 맞추어 반도체 기판(1)의 상부 드러나도록 층간 절연막(3)을 식각하여 콘택홀을 형성한다.As shown in FIG. 1B, a contact pattern 4 is formed on the interlayer insulating film 3, and the interlayer insulating film 3 is etched to expose the upper portion of the semiconductor substrate 1 in accordance with the contact pattern 4. To form contact holes.
이후 도 1c에 도시된 바와 같이, 콘택홀이 형성된 층간 절연막(3) 상부에 장벽 금속막(5)으로서 Ti막(5a) 및 TiN막(5b)을 적층해서 형성한다. 이때, 장벽 금속막(5)은 물리적기상증착(Physical Vapor Deposition : 이하 PVD라 함) 공정 또는 화학적기상증착(Chemical Vapor Deposition : 이하 CVD라 함) 공정으로 형성될 수 있으나 대개 PVD인 스퍼터링(sputtering) 방식으로 형성된다.Subsequently, as shown in FIG. 1C, a Ti film 5a and a TiN film 5b are stacked as a barrier metal film 5 on the interlayer insulating film 3 on which contact holes are formed. At this time, the barrier metal film 5 may be formed by a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process, but is usually a PVD sputtering process. Is formed in a manner.
도 1d에 도시된 바와 같이, 콘택홀이 형성된 반도체 기판(1) 상부 전면에 화학 기상 증착(chemical vapor deposition)으로 텅스텐 박막을 증착하여 콘택홀을 매립하고, 이를 화학 기계적 연마하여 텅스텐 플러그를 형성함으로써 반도체 소자(2)의 각 전극과 금속 배선을 전기적으로 접속하기 위한 콘택(6)을 형성한다.As shown in FIG. 1D, a tungsten thin film is deposited by chemical vapor deposition on the entire upper surface of the semiconductor substrate 1 on which the contact holes are formed, and the contact holes are buried, and chemical mechanical polishing is performed to form a tungsten plug. The contact 6 for electrically connecting each electrode of the semiconductor element 2 and a metal wiring is formed.
최근 들어 반도체 소자의 고집적화(콘택 또는 비아홀 사이가 최소화)에 따라포토레지스트의 두께는 얇아지고, 포토레지스트로 사용되는 물질도 다양하게 개발되고 있다. 포토레지스트의 두께가 얇아짐에 따라 포토레지스트가 산화막으로 이루어진 층간 절연막의 표면 상태에 따라 클랙(crack) 현상이 발생되며, 이러한 클랙 현상에 의해서 반도체 수율이 떨어지는 문제점이 있다.In recent years, as the semiconductor device is highly integrated (minimized between contacts or via holes), the thickness of the photoresist is thinned, and various materials used as the photoresist have been developed. As the thickness of the photoresist decreases, a crack phenomenon occurs according to the surface state of the interlayer insulating layer in which the photoresist is formed of an oxide film, and the semiconductor yield decreases due to the crack phenomenon.
본 발명의 목적은 이와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 층간 절연막의 상부에 라이너 질화막을 형성하여 포토레지스트의 클랙 현상을 방지할 수 있는 반도체 소자의 콘택홀 형성 방법을 제공하고자 한다.An object of the present invention is to solve the problems of the prior art, to provide a method for forming a contact hole in a semiconductor device that can prevent the crack phenomenon of the photoresist by forming a liner nitride film on the interlayer insulating film.
상기와 같은 목적을 달성하기 위하여 본 발명은, 콘택홀(또는 비아홀)을 형성하는 방법에 있어서, 반도체 소자가 형성된 반도체 기판 상에 층간 절연막 및 라이너 절연막을 순차적으로 형성하는 단계와, 상기 라이너 절연막의 상부에 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트 패턴에 맞추어서 상기 라이너 질화막과 층간 절연막의 일부만을 식각하는 단계와, 상기 콘택 패턴을 제거한 후, 결과물에 식각 공정을 실시하여 상기 라이너 질화막을 제거함과 함께 상기 층간 절연막을 식각하여 콘택홀(또는 비아홀)을 형성하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method for forming a contact hole (or via hole), the method comprising the steps of sequentially forming an interlayer insulating film and a liner insulating film on a semiconductor substrate on which a semiconductor element is formed; Forming a photoresist pattern thereon, etching only a portion of the liner nitride film and the interlayer insulating film in accordance with the photoresist pattern, removing the contact pattern, and then etching the resultant to remove the liner nitride film. And etching the interlayer insulating layer to form contact holes (or via holes).
도 1a 내지 도 1d는 종래 기술에 의한 반도체 소자의 금속 배선 형성 방법을 도시한 공정 단면도이고,1A to 1D are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the prior art;
도 2a 내지 2e는 본 발명의 바람직한 실시 예에 따른 반도체 소자의 금속 배선 형성 방법을 도시한 공정 단면도.2A to 2E are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device in accordance with a preferred embodiment of the present invention.
＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>
100 : 반도체 기판 101 : 반도체 소자100 semiconductor substrate 101 semiconductor device
102 : 층간 절연막 103 : 라이너 산화막102 interlayer insulating film 103 liner oxide film
104 : 포토레지스트 패턴 105 : 콘택홀104: photoresist pattern 105: contact hole
106 : 장벽 금속막 107 : 콘택106: barrier metal film 107: contact
본 발명의 실시 예는 다수개가 존재할 수 있으며, 이하에서 첨부한 도면을 참조하여 바람직한 실시 예에 대하여 상세히 설명하기로 한다. 이 기술 분야의 숙련자라면 이 실시 예를 통해 본 발명의 목적, 특징 및 이점들을 잘 이해할 수 있을 것이다.There may be a plurality of embodiments of the present invention, and a preferred embodiment will be described in detail below with reference to the accompanying drawings. Those skilled in the art will be able to better understand the objects, features and advantages of the present invention through this embodiment.
도 2a 내지 도 2e는 본 발명의 일실시 예에 반도체 소자의 금속 배선 형성 과정을 순차적으로 도시한 공정도이다. 여기에서는 금속 배선을 수직으로 연결하는 콘택홀의 제조 공정에 대해 설명한다.2A through 2E are process diagrams sequentially illustrating a process of forming metal wirings in a semiconductor device according to an embodiment of the present invention. Here, the manufacturing process of the contact hole which vertically connects a metal wiring is demonstrated.
도 2a에 도시된 바와 같이, 반도체 기판(100) 상부에 층간 절연막(102) 및 라이너 절연막(103)을 순차 증착한다. 이때, 반도체 기판(100)에는 반도체 소자가 형성될 활성 영역(active area)을 정의되어 있으며, 정의된 반도체 기판(100)의 활성영역에는 반도체 소자 제조 공정에 따라 게이트 전극(G), 소스 전극(S), 드레인 전극(D)을 포함하는 반도체 소자(101)가 형성되어 있다.As shown in FIG. 2A, an interlayer insulating film 102 and a liner insulating film 103 are sequentially deposited on the semiconductor substrate 100. In this case, an active area in which the semiconductor device is to be formed is defined in the semiconductor substrate 100, and the gate electrode G and the source electrode are defined in the defined active area of the semiconductor substrate 100 according to a semiconductor device manufacturing process. The semiconductor element 101 including S) and the drain electrode D is formed.
여기서, 라이너 절연막(103)은 질화막으로 이루어져 후술되는 공정에서 상부에 도포되는 포토레지스트의 클랙을 방지하며, 콘택홀을 형성하기 위한 식각 공정 시에 식각 마스크로 이용된다. 층간 절연막(102)은 실리콘 산화막으로 이루어진다.Here, the liner insulating layer 103 is formed of a nitride film to prevent the crack of the photoresist applied to the upper portion in the process described later, it is used as an etching mask during the etching process for forming a contact hole. The interlayer insulating film 102 is made of a silicon oxide film.
이후 도 2b에 도시된 바와 같이, 라이너 절연막(103) 상부에 감광막을 도포하여 노광 및 현상 공정을 통해 포토레지스트 패턴(104)을 형성한다.Thereafter, as shown in FIG. 2B, a photoresist film is coated on the liner insulating layer 103 to form a photoresist pattern 104 through an exposure and development process.
도 2c에 도시된 바와 같이, 라이너 절연막(103)의 상부에 포토레지스트 패턴(104)에 맞추어서 층간 절연막(102) 및 라이너 절연막(103)을 식각하여 층간 절연막(102)을 패터닝하는데, 이때 층간 절연막(102)을 반도체 소자(101)가 드러나도록 식각하는 것이 아니라 층각 절연막(102)의 일부만을 식각한다.As shown in FIG. 2C, the interlayer insulating film 102 and the liner insulating film 103 are etched in accordance with the photoresist pattern 104 on the liner insulating film 103 to pattern the interlayer insulating film 102. Instead of etching 102 to expose the semiconductor device 101, only a portion of the layered insulating film 102 is etched.
도 2d에 도시된 바와 같이, 포토레지스트 패턴(104)을 제거한 후에 라이너 절연막(103)을 식각 마스크로 하여 블랭킷(blanket) 식각을 실시하여 라이너 절연막(103)을 제거함과 함께 패터닝된 층간 절연막(102 )도 반도체 소자(101)가 드러나도록 같이 식각되어 층간 절연막 내에 콘택홀(105)을 형성한다.As shown in FIG. 2D, after the photoresist pattern 104 is removed, a blanket etching is performed using the liner insulating film 103 as an etching mask to remove the liner insulating film 103 and the patterned interlayer insulating film 102. ) Is also etched to expose the semiconductor device 101 to form a contact hole 105 in the interlayer insulating film.
이후 도 2e에 도시된 바와 같이, 콘택홀(105)이 형성된 층간 절연막(102 ) 상부에 장벽 금속막(106)을 형성한 후, 콘택홀(105)이 형성된 반도체 기판(100) 상부 전면에 화학 기상 증착(chemical vapor deposition)으로 금속층을 증착하여 콘택홀(105)을 매립하고, 이를 화학 기계적 연마하여 텅스텐 플러그를 형성함으로써 반도체 소자(101)의 각 전극과 금속 배선을 전기적으로 접속하기 위한 콘택(107)을 형성한다.Thereafter, as shown in FIG. 2E, the barrier metal layer 106 is formed on the interlayer insulating layer 102 on which the contact hole 105 is formed, and then a chemical is formed on the entire upper surface of the semiconductor substrate 100 on which the contact hole 105 is formed. By depositing a metal layer by chemical vapor deposition to fill the contact hole 105, and chemical mechanical polishing to form a tungsten plug, a contact for electrically connecting each electrode and the metal wiring of the semiconductor device 101 ( 107).
본 발명의 바람직한 실시 예에 따라 반도체 소자의 콘택홀 형성 방법은 라이너 절연막을 이용하여 콘택홀 형성을 위해 도포된 포토레지스트의 클랙을 방지하였지만, 다른 콘택홀 형성 방법으로는 포토레지스트 패턴을 형성하지 않고 질화막으로 이루어진 라이너 절연막과 산화막으로 이루어진 층간 절연막의 식각 선택비를 이용하여 층간 절연막에 콘택홀을 형성할 수 있다.According to a preferred embodiment of the present invention, the method of forming a contact hole in a semiconductor device prevents cracking of a photoresist applied for forming a contact hole using a liner insulating film, but does not form a photoresist pattern using another contact hole forming method. A contact hole may be formed in the interlayer insulating layer by using an etching selectivity between the liner insulating layer formed of a nitride film and the interlayer insulating layer formed of an oxide film.
이상 설명한 바와 같이, 본 발명은 층간 절연막의 상부에 라이너 절연막을 증착하여 콘택홀 형성을 위해 도포된 포토레지스트의 클랙을 방지함으로써, 콘택 저항의 안정화 및 반도체 수율을 향상시킬 수 있다.As described above, the present invention can prevent the cracking of the photoresist applied for forming the contact hole by depositing a liner insulating film on the interlayer insulating film, thereby improving the stability of the contact resistance and the semiconductor yield.
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020054235A KR20040022627A (en) | 2002-09-09 | 2002-09-09 | Method for forming contact hole of a semiconductor |
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| KR1020020054235A KR20040022627A (en) | 2002-09-09 | 2002-09-09 | Method for forming contact hole of a semiconductor |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0485928A (en) * | 1990-07-30 | 1992-03-18 | Sony Corp | Dry etching method |
| KR970018055A (en) * | 1995-09-26 | 1997-04-30 | 김광호 | Manufacturing Method of Semiconductor Device |
| KR19990079274A (en) * | 1998-04-03 | 1999-11-05 | 김영환 | How to Form Contact Holes |
| JP2002261082A (en) * | 2001-03-01 | 2002-09-13 | Nec Corp | Method of manufacturing semiconductor device |
-
2002
- 2002-09-09 KR KR1020020054235A patent/KR20040022627A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0485928A (en) * | 1990-07-30 | 1992-03-18 | Sony Corp | Dry etching method |
| KR970018055A (en) * | 1995-09-26 | 1997-04-30 | 김광호 | Manufacturing Method of Semiconductor Device |
| KR19990079274A (en) * | 1998-04-03 | 1999-11-05 | 김영환 | How to Form Contact Holes |
| JP2002261082A (en) * | 2001-03-01 | 2002-09-13 | Nec Corp | Method of manufacturing semiconductor device |
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