TW202036791A - Metal interconnect structure by subtractive process - Google Patents

Abstract

A metal interconnect structure of an integrated circuit may be fabricated by forming one or more vias subsequent to formation of two contiguous metallization layers. The one or more vias are fully aligned with a first metallization layer and a second metallization layer. Hardmask material or other insulating material is left on top of the first metallization layer and the second metallization layer during fabrication of the metal interconnect structure. Some of the hardmask material or other insulating material is etched and subsequently backfilled with electrically conductive material to form the one or more vias, where the one or more vias are contained within a space that does not overlap with surrounding dielectric material.

Description

Metal interconnect structure formed by reduction process

The present invention relates to a metal interconnection structure formed by a reduction process.

The interconnection structure added in an integrated circuit (IC) includes one or more layers of metal wires to connect the electronic devices of the IC to each other and to the external connection portion. The metal wire layers can be insulated from each other through one or more intervening layers of dielectric material. The interconnect structure can be formed by additive patterning technology or subtractive patterning technology. Additive patterning techniques can include damascene or dual damascene processes, which can be used to fabricate interconnect structures with metals such as copper or cobalt. Etching trenches and/or holes in the dielectric material, depositing metal in the trenches and/or holes, and using chemical mechanical planarization (CMP) to remove excess portions. However, in the reduction patterning technique, a metal cap layer is deposited and etched to form trenches and/or holes in the metal, and a dielectric material is deposited in the trenches and/or holes.

The prior art description provided here is to generally introduce the background of the present invention. The achievements of the inventors listed in this case within the scope described in this chapter of the prior art, and the implementation of the specification of the prior art at the time of application, are not intentionally or implicitly recognized as opposed to the present invention The prior art.

This article provides a method of manufacturing a metal interconnect structure. The method includes: forming a patterned metal line of a first layer on a substrate by reduction patterning; and forming a pattern of a second layer over the patterned metal line of the first layer by reduction patterning化metal wire. The method further includes: after forming the patterned metal lines of the second layer, forming one or more electrical interconnections between the patterned metal lines of the first layer and the patterned metal lines of the second layer Via a via window, thereby forming the metal interconnection structure.

In some embodiments, the step of forming the one or more vias includes: forming one or more via openings through at least the patterned metal line of the second layer to the patterned metal of the first layer Line; and filling the one or more via openings with a conductive material. In some embodiments, the method further includes: forming a plurality of first insulating features on the patterned metal line of the first layer; and after forming the plurality of first insulating features, adjacent to the first layer A first dielectric material is formed in the gap between the metal lines. The method further includes: forming a plurality of second insulating features on the patterned metal lines of the second layer; and after forming the plurality of second insulating features, in the gaps between adjacent metal lines of the second layer A second dielectric material is formed. In some embodiments, the step of forming the one or more vias includes: etching through one or more second insulating features; etching through the patterned metal lines of the second layer; etching through one or more The first insulating feature forms one or more via openings to expose the patterned metal lines of the first layer; and depositing conductive material in the one or more via openings to expose the exposed The one or more vias are formed on the patterned metal line of the first layer. In some embodiments, the method further includes: forming a via mask over the plurality of second insulating features and the second dielectric material; and patterning one or more vias in the via mask Holes, wherein each of the one or more holes has a diameter or width larger than the critical dimension (CD) of the patterned metal line of the second layer and/or the patterned metal line of the first layer. The one or more porous holes each have a diameter or width that is up to about 100% larger than the CD of the patterned metal line of the second layer and/or the patterned metal line of the first layer. In some embodiments, the step of depositing the conductive material includes: using the conductive material to fill the previously etched portions of the first insulating features and the patterned metal lines of the second layer. In some embodiments, each of the patterned metal lines of the first layer, the patterned metal lines of the second layer, and the conductive material includes molybdenum (Mo), ruthenium (Ru), aluminum (Al), Or tungsten (W). In some embodiments, the one or more vias are completely aligned with the patterned metal lines of the first layer and the patterned metal lines of the second layer. In some embodiments, the step of forming the patterned metal line of the first layer includes: depositing a first metal on the substrate; depositing a first mask layer on the first metal; Etching to form a plurality of first insulating features on the first metal; and etching the first metal to form patterned metal lines of the first layer defined by the plurality of first insulating features. In some embodiments, the step of forming the patterned metal line of the second layer includes: depositing a second metal over the patterned metal line of the first layer; depositing a second mask layer over the second metal; Etching the second mask layer to form a plurality of second insulating features over the second metal; and etching the second metal to form the second insulating feature defined by the second metal Layer of patterned metal lines.

Another aspect relates to a metal interconnection structure for integrated circuits. The metal interconnection structure includes: patterned metal lines of a first layer; a plurality of first insulating features located on at least some of the patterned metal lines in the first layer; and patterned metal lines of the second layer located on the Above the patterned metal lines of the first layer; a plurality of second insulating features located on at least some of the patterned metal lines in the second layer; and one or more vias that provide patterning of the first layer The electrical interconnection between the metal line and the patterned metal line of the second layer, wherein the one or more vias are completely connected to the patterned metal line of the first layer and the patterned metal line of the second layer. alignment.

In some embodiments, the one or more vias extend through the first insulating features so that the patterned metal lines of the first layer are in contact with the patterned metal lines of the second layer. In some embodiments, the metal interconnection structure further includes: a first dielectric material that surrounds the patterned metal line of the first layer and the plurality of first insulating features; and a second dielectric material that surrounds The second layer of patterned metal lines and the plurality of second insulating features. In some embodiments, the metal interconnection structure further includes: a third dielectric material located above the recessed via metal filling of the one or more vias. In some embodiments, each of the first dielectric material and the second dielectric material includes a low-k dielectric material, wherein each of the plurality of first insulating features and the plurality of second insulating features has Different etch selectivity from this low-k dielectric material. In some embodiments, the one or more vias include a conductive material, wherein each of the patterned metal lines of the first layer, the patterned metal lines of the second layer, and the conductive material includes Mo , Ru, Al, or W.

These and other implementation aspects are further described below with reference to the drawings.

In this disclosure, the terms "semiconductor wafer", "wafer", "substrate", "wafer substrate", and "partially processed integrated circuit" are used interchangeably. Those with ordinary knowledge in the field will understand that the term "partially processed integrated circuit" can refer to silicon wafers during any of the many stages of integrated circuit processing. Wafers or substrates used in the semiconductor device industry generally have a diameter of 200 mm, or 300 mm, or 450 mm. The following detailed description assumes that the present disclosure is implemented on a wafer. However, the embodiment is not so limited. The workpiece can be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that can use the present disclosure include various objects, such as printed circuit boards. Preface

Advances in integrated circuit technology involve shrinking to smaller and smaller features in integrated circuits. Integrated circuits usually include conductive microelectronic structures or vias that connect conductive structures or layers. The conductive structure may include line features (such as metal lines or metallization layers) that span a distance on the chip, and interconnect features (such as vias) that connect the line features in different levels. The line features and interconnection features can be insulated by dielectric materials.

Damascene and dual damascene manufacturing techniques have been used to produce vias and metal lines in metal interconnect structures. Damascene and dual damascene technologies are additive patterning technologies that are relied upon in the process of manufacturing metal interconnect structures (such as copper interconnect structures). However, as the size of features in integrated circuits continues to shrink, additive patterning technology may be insufficient for some technology nodes. In the case that the additive patterning technology is insufficient, the subtractive patterning technology may be suitable.

In summary, the subtractive patterning technique deposits a metal cover layer, applies a mask to the metal cover layer, and etches the metal cover layer to pattern the metal lines or features defined by the mask. In contrast, the additive patterning technique deposits a dielectric material cover layer, coats a mask on the dielectric material cover layer, etches the openings or recesses defined by the mask in the dielectric material cover layer, and uses Metal fills the openings or recesses. Typical metals used in additive patterning techniques include copper (Cu) or cobalt (Co). Copper has high electrical conductivity (second only to silver), which makes it very suitable as an interconnect metal. However, metals such as copper and cobalt are difficult to etch, so they are not a suitable choice for the reduced patterning technology commonly used in integrated circuit manufacturing.

Typical reduction patterning techniques use metals such as aluminum (Al) in the process of manufacturing metal lines and metal interconnect structures. The line width produced by the reduction patterning technology is usually about several micrometers to hundreds of nanometers. Copper damascene technology was introduced many years ago to manufacture copper wires and copper interconnect structures. The line widths produced by damascene technology are usually about tens or hundreds of nanometers. However, it is difficult to reliably obtain a line width equal to or less than 30 nm, or equal to or less than 20 nm using copper damascene technology. For example, copper interconnect structures usually require diffusion barrier layers and/or liner layers to limit the diffusion of copper into surrounding dielectric materials, and these layers may occupy more space, thus making smaller line widths more difficult to achieve. Metals other than copper can be used in reduced patterning that allows thinner diffusion barrier layers and/or liner layers (or neither). This can realize smaller size and/or technology nodes in the manufacture of integrated circuits. Reduced patterning

1A-10 show schematic diagrams of an exemplary process for forming a metal interconnect structure by reduction patterning. In FIG. 1A, a first metal layer 101 (Mx) is deposited on the substrate 100. The first metal layer 101 in FIG. 1A is an unpatterned cover layer. Appropriate deposition processes (such as physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma assisted chemical vapor deposition (PECVD), atomic layer deposition (ALD), or electrodeposition) can be used to deposit the first The metal layer 101. Electrodeposition may include, for example, electroplating or electroless plating. In some embodiments, the first metal layer 101 may include metals that can be etched, and these metals may include, but are not limited to, molybdenum (Mo), ruthenium (Ru), tungsten (W), or aluminum (Al ). In some embodiments, a spacer layer may be provided between the first metal layer 101 and the substrate 100. Examples of the liner layer include, but are not limited to, titanium nitride (TiN). Other examples include tantalum nitride (TaN), tungsten nitride (WN), and tungsten carbonitride (WCN). The thickness of the liner layer may be equal to or less than about 5 nm, or equal to or less than about 3 nm. In some embodiments, a dielectric layer 102 may be provided between the liner layer and the substrate 100. The liner layer is used to separate the first metal layer 101 from the dielectric layer 102.

In order to pattern the first metal layer 101, a first hard mask layer 103 may be deposited on the first metal layer 101. Examples of suitable hard mask materials can include silicon nitride, silicon oxide, silicon carbon nitride, silicon oxycarbide, silicon oxynitride, amorphous silicon, polysilicon, or carbon (e.g., amorphous carbon, metal doped Amorphous carbon, diamond-like carbon, polycrystalline diamond). The photoresist 104 and the photoresist lower layer 105 subjected to extreme ultraviolet light (EUV) lithography can be used to pattern the first hard mask layer 103. Additional film layers can be formed between the photoresist and the first hard mask layer, and the additional film layers can be useful in lithography processing. For example, the amorphous carbon 106 (a-C) and the anti-reflection layer 107 (ARL) may be disposed between the photoresist 104 and the first hard mask layer 103. The anti-reflection layer 107 can be used to prevent the radiation in the subsequent lithography process from reflecting from the underlying film layer and interfering with the exposure process.

In FIG. 1B, a plurality of first hard mask features 108 are formed by patterning the first hard mask layer 103. The photoresist 104 can be patterned by using lithography (such as EUV lithography) to define the plurality of first hard mask features 108. In addition, in some embodiments, a self-aligned double patterning (SADP) process can be used to reduce the feature size of the first hard mask feature. For example, a narrower hard mask feature can be formed by pitch doubling, in which SADP processing can be used to reduce the pitch of the plurality of first hard mask features 108 from 80 nm. As small as 40 nm.

In FIG. 1C, an additional mask layer can be optionally deposited and patterned over the plurality of first hard mask features 108. These additional mask layers can be patterned to be used to etch the plurality of first hard mask features 108 underneath into the desired configuration of the first hard mask features, so as to pattern the first metal layer 101 . Then, the first metal layer 101 can be patterned and "cut" according to the desired configuration of the first hard mask feature 108. In some embodiments, the additional mask layer may include photoresist 109, photoresist underlayer 110, and spin-on carbon 111 (SoC). However, it should be understood that instead of using an additional mask layer to etch the plurality of first hard mask features 108 underneath, the etching of the first hard mask features 108 may be performed after the first metal layer 101 is etched. In other words, the first metal layer 101 is "cut" through the additional mask layer instead of subjecting the plurality of first hard mask features 108 to "cutting".

In FIG. 1D, a plurality of first hard mask features 108 are patterned through an additional mask layer. Through the "cut" etching process, the additional mask layer forms the plurality of first hard mask features 108 into the desired feature configuration. These additional mask layers are then removed.

In FIG. 1E, the first metal layer 101 is patterned to form a first patterned metal line layer 112. During the metal line etching process, the first patterned metal line layer 112 is defined by a plurality of first hard mask features 108. The metal line etching process can selectively etch through metal to form the first patterned metal line layer 112 without etching the underlying dielectric layer 102. A suitable etchant may be used to etch the metal without substantially etching the dielectric material of the underlying dielectric layer 102. As used herein, "substantially not etched" may refer to the following etching process: the etching rate of the target material (for example, dielectric) is at least 1/5 times lower than the etching rate of the target material (for example, metal) to be etched Etching treatment. For example, subtractive plasma etching can remove the metal capping layer at a significantly higher etch rate than the underlying dielectric layer 102. After forming the first patterned metal line layer 112, the plurality of hard mask features 108 may be removed. In some embodiments, a diffusion barrier layer and/or a liner layer may be deposited on the first patterned metal line layer 112. The diffusion barrier layer and/or the liner layer separate the first patterned metal line layer 112 from the surrounding dielectric material.

In FIG. 1F, the first dielectric material 113 is deposited on the first patterned metal line layer 112 and filled in the gaps between adjacent first metal lines. The first dielectric material 113 may surround the first patterned metal line layer 112. After the metal capping layer is etched to form the first patterned metal line layer 112, the first dielectric material 113 is filled in the gaps, recesses, openings, or spaces previously filled by the metal capping layer. In some embodiments, after depositing the first dielectric material 113, a planarization process (such as chemical mechanical polishing (CMP) and/or blanket etchback) may be used to make the first dielectric material 113 flattening. In some embodiments, the first dielectric material 113 is a dielectric material with a low dielectric constant (low-k dielectric). The low-k dielectric may have a dielectric constant equal to or lower than about 5.0, which may be equal to or lower than the dielectric constant of silicon oxide (about 4.2). The low-k dielectric material may include fluorine-doped or carbon-doped silicon oxide or organic-containing low-k materials, such as organic silicon glass (OSG). In some embodiments, air gaps can be formed in the first dielectric material 113 between adjacent patterned metal lines, where the air gaps can be used to further make the first dielectric material between adjacent patterned metal lines The dielectric constant of the electrical material 113 decreases. These air gaps 114 can be observed in FIG. 2A, which is a schematic cross-sectional view of a partially processed metal interconnect structure taken from the line A-A of FIG. 1F. As shown in FIG. 2A, the first dielectric material 113 fills the gaps between adjacent patterned metal lines. The air gap 114 is formed in the first dielectric material 113 in the gap between adjacent patterned metal lines, wherein the patterned metal line is separated from the air gap 114 by the remaining first dielectric material 113.

In FIG. 1G, a via mask 115 may be formed over the first dielectric material 113. In some embodiments, the via mask 115 may include one or more mask layers, where the one or more mask layers include photoresist 116, photoresist underlayer 117, and spin-on carbon 118 (SoC) . In order to form a via connected to the first patterned metal line layer 112, a via opening as defined by the via mask 115 is patterned and formed in the first dielectric material 113. A lithography process can be applied to the photoresist 116 to pattern the photoresist 116 of the via mask 115. One or more holes 119 may be formed in the via mask 115 to define the via opening in the first dielectric material 113. It is intended to align one or more holes 119 in the via mask 115 with the first patterned metal line layer 112.

In FIG. 1H, a via opening 120 is formed in the first dielectric material 113 by etching. The via opening 120 is defined by one or more holes 119 of the via mask 115. It is intended that the via opening 120 is aligned with one or more patterned metal lines of the first layer 112. However, as described below, alignment errors may occur during the lithography process, which may cause the via opening 120 to not be aligned with one or more patterned metal lines of the first layer 112. The via mask 115 may be removed after the via opening 120 is formed. In FIG. 2B-1, the via opening 120 that is completely aligned with one or more patterned metal lines of the first layer 112 can be observed, and in FIG. 2B-2, it can be observed that the via opening 120 is not aligned with the first layer 112 One or more via openings 120 aligned with patterned metal lines.

As the feature size shrinks, it may be difficult to scale the conventional lithography process to provide a smaller feature size. This is at least partially due to alignment or coverage errors between features in the metal interconnect structure. Alignment or coverage errors always occur during the lithography process because the mask is not completely aligned with the underlying structure. For example, during the exposure stage of the use of a reduction mask in the lithography process, the patterned mask for the vias and trenches may be misaligned by a few nanometers. Therefore, the vias intended to be connected to the patterned metal lines may be misaligned. Although the coverage error can be minimized by performing lithography again, a certain degree of coverage error is unavoidable.

As shown in FIG. 2B-1, when the via opening 120 patterned through one or more mask layers is completely aligned with the first patterned metal line layer 112, the via opening 120 does not deviate from the first pattern化metal wire layer 112. The via opening 120 is formed directly above the first patterned metal line layer 112 and is not formed in the gap between adjacent patterned metal lines of the first layer 112. However, alignment or coverage errors may cause one or more mask layers to be misaligned in the x direction or the y direction, even if they are several nanometers. As shown in FIG. 2B-2, the via opening 120 is patterned through one or more mask layers and is not aligned with the first patterned metal line layer 112. The misalignment causes a portion of the via opening 120 to be formed in the gap between adjacent patterned metal lines of the first layer 112. The misalignment results in the loss of the contact area between the patterned metal line of the first layer 112 and the via, and the via overlaps with a portion of the dielectric material surrounding the first patterned metal line layer 112. In addition, the misalignment may cause the risk of a gap adjacent to the air gap 114, which may cause a short circuit or leakage.

In FIG. 1I, a second metal layer 121 (Mx+1) is deposited on the first dielectric material 113, wherein the second metal layer 121 fills the via opening 120 to form one or more vias. The second metal layer 121 provides a metal capping layer on the first dielectric material 113. In some embodiments, a liner layer is provided between the second metal layer 121 and the first dielectric material 113. The liner layer may also be disposed between one or more patterned metal lines of the first layer 112 and the via. The second metal layer 121 may provide a metal capping layer over the first dielectric material 113 or may be deposited to a target thickness of the second metal layer 121. The deposition of the second metal layer 121 may cause surface topography problems or surface roughness, which can be attributed to the metal-filled via opening 120 and covering the first dielectric material 113. In some embodiments, a planarization process can be used to planarize the second metal layer 121 to produce a relatively smooth and flat metal thin layer. In some embodiments, the second metal layer 121 is deposited by a suitable deposition technique (for example, PVD, CVD, PECVD, ALD, or electrodeposition). In some embodiments, the second metal layer 121 includes Mo, Ru, Al, or W. In some embodiments, a metal deposition process different from the metal deposition process of depositing metal on the first dielectric material 113 may be used to fill the via opening 120. For example, a suitable deposition process can be used to fill the via opening 120 with one of the metals listed above. After that, a separate process can be performed to deposit a cover layer of one of the metals listed above on the first dielectric material 113 and connect to the via. In some embodiments, a planarization process can be performed to the desired thickness of the second metal layer 121.

In FIG. 1J, a second hard mask layer 122 is deposited on the second metal layer 121. Examples of suitable hard mask materials include silicon nitride, silicon oxide, silicon carbon nitride, silicon oxycarbide, silicon oxynitride, amorphous silicon, polysilicon, or carbon (e.g., amorphous carbon, metal doped Amorphous carbon, diamond-like carbon, polycrystalline diamond). The photoresist 123 and the photoresist lower layer 124 subjected to extreme ultraviolet light (EUV) lithography can be used to pattern the second hard mask layer 122. An additional film layer may be formed between the photoresist 123 and the second hard mask layer 122, wherein the additional film layer may be useful in lithography processing. For example, the amorphous carbon 125 (a-C) and the anti-reflection layer 126 (ARL) may be disposed between the photoresist 123 and the second hard mask layer 122.

2C-1 and 2C-2 show schematic cross-sectional views of a partially processed metal interconnection structure taken from the line C-C of FIG. 1J. As shown in FIGS. 2C-1 and 2C-2, the second metal layer 121 fills the via opening 120 to form a via 127, which provides an electrical connection with the first patterned metal line layer 112. In FIG. 2C-1, the via 127 is completely aligned with the first patterned metal line layer 112. However, due to alignment or coverage errors, as shown in FIG. 2C-2, the via 127 is not aligned with the first patterned metal line layer 112. Due to alignment or coverage errors, the via 127 is partially "landed" on the top surface of one or more of the patterned metal lines in the first layer 112, thereby causing the via 127 to shift and change. The adjacent patterned metal line near the first layer 112 enters the surrounding dielectric material. This reduces the distance between the conductive features, which means that the insulating gap between the via 127 and the adjacent patterned metal line of the first layer 112 is smaller. The reduced distance may result in insufficient short-circuit margin and reduced time-dependent dielectric breakdown (TDDB), or even complete short-circuit. TDDB is a failure mode in which the insulating layer (such as the first dielectric material 113) collapses over time and no longer acts as an effective electrical insulator in a typical electric field. TDDB depends on the electric field between the metal wires, because areas exposed to higher electric fields are more susceptible to TDDB failure. High voltage and/or reduced insulator thickness will result in higher electric fields. TDDB also depends on the spacing between adjacent metal lines, because the spacing may be reduced to the point where the insulating layer cannot withstand the electric field, resulting in undesirable conductance between adjacent metal lines. When the insulating layer cannot withstand the working electric field, the final result is a short circuit or reduced reliability. "Unlanded" vias may cause serious reliability problems due to TDDB degradation. In addition, the "unlanded" vias may cause gaps in the bottom air gaps 114, which are deposited by conductive materials, which may cause short circuits.

In FIG. 1K, a plurality of second hard mask features 128 are formed by patterning the second hard mask layer 122. The photoresist 123 can be patterned by using lithography (such as EUV lithography) to define the plurality of second hard mask features 128. In addition, in some embodiments, a self-aligned double patterning (SADP) process can be used to reduce the feature size of the second hard mask feature 128. For example, a narrower hard mask feature can be formed by pitch doubling, where SADP processing can be used to reduce the pitch of the plurality of second hard mask features 128 from 40 nm As small as 20 nm.

In FIG. 1L, an additional mask layer can be optionally deposited and patterned over a plurality of second hard mask features 128. These additional mask layers can be patterned to be used to etch the plurality of second hard mask features 128 underneath into the desired configuration of the second hard mask features 128, so as to pattern the second metal layer 121化. Then, the second metal layer 121 can be patterned and "cut" according to the desired configuration of the second hard mask feature 128. In some embodiments, the additional mask layer may include photoresist 129, photoresist underlayer 130, and spin-on carbon 131 (SoC). However, it should be understood that instead of using an additional mask layer to etch the plurality of second hard mask features 128 underneath, the second hard mask features 128 may be etched after the second metal layer 121 is etched. In other words, the second metal layer 121 is “cut” through the additional mask layer instead of subjecting the plurality of second hard mask features 128 to “cutting”.

In FIG. 1M, a plurality of second hard mask features 128 are patterned through an additional mask layer. Through the "cut" etching process, the additional mask layer forms the plurality of second hard mask features 128 into the desired feature configuration. These additional mask layers are then removed.

In FIG. 1N, the second metal layer 121 is patterned to form a second patterned metal line layer 132. During the metal line etching process, the patterned metal line is defined by a plurality of second hard mask features 128. The metal line etching process can selectively etch through the metal to form the second patterned metal line layer 132 without etching the first dielectric material 113. A suitable etchant may be used to remove the metal without etching or substantially not etching the first dielectric material 113. For example, subtractive plasma etching can remove the metal capping layer at a significantly higher etching rate than the underlying first dielectric material 113. After the second patterned metal line layer 132 is formed, the plurality of second hard mask features 128 may be removed. In some embodiments, a diffusion barrier layer and/or a liner layer may be deposited on the second patterned metal line layer 132. The diffusion barrier layer and/or the liner layer separate the second patterned metal line layer 132 from the surrounding dielectric material.

The via 127 provides an electrical interconnection between the second patterned metal line layer 132 and the first patterned metal line layer 112 to form a metal interconnection structure. As mentioned above, when one or more holes 119 are patterned in the via mask 115, there is a risk of misalignment with the first patterned metal line layer 112. There is not only a risk of misalignment with the first patterned metal line layer 112 (Mx), but also a risk of misalignment with the second patterned metal line layer 132 (Mx+1). When the second patterned metal line layer 132 is patterned, there is a risk of misalignment between the via 127 and the second patterned metal line layer 132. 2D-1 shows a schematic cross-sectional view of the metal interconnection structure taken from the line D-D of FIG. 1N, in which the via 127 is aligned with the second patterned metal line layer 132. In FIG. 2D-1, there is no loss of contact area between the via 127 and the second patterned metal line layer 132. 2D-2 shows a schematic cross-sectional view of the metal interconnection structure taken from the line D-D of FIG. 1N, in which the via 127 is misaligned with the second patterned metal line layer 132. Due to the misalignment, in FIG. 2D-2, there is a loss of contact area between the via 127 and the second patterned metal line layer 132. This leads to a loss of via area. The electrical resistance is proportional to the resistivity of the material and its length, and inversely proportional to the cross-sectional area of the material. The loss of via area results in higher via resistance, which leads to reduced performance and reduced reliability.

In FIG. 10, in the same manner as Mx, the dielectric material 133 is deposited on the second patterned metal line layer 132 and filled in the gaps between adjacent second metal lines. The dielectric material 133 (hereinafter referred to as the second dielectric material) may surround the second patterned metal line layer 132. After the metal capping layer is etched to form the second patterned metal line layer 132, the second dielectric material 133 is filled in the gaps, recesses, openings, or spaces previously filled by the metal capping layer. In some embodiments, after the second dielectric material 133 is deposited, the second dielectric material 133 may be planarized by a planarization process (such as CMP and/or blanket etchback). In some embodiments, the second dielectric material 133 is a low-k dielectric material. In some embodiments, the second dielectric material 133 has the same composition as the first dielectric material 113. In some embodiments, air gaps can be formed in the second dielectric material between adjacent second metal lines, where the air gaps can be used to further make the second dielectric material between adjacent second metal lines The dielectric constant of the electrical material 133 decreases. After depositing the second dielectric material 133, a metal interconnection structure is formed. The metal interconnection structure formed by the reduction patterning technology has a first patterned metal line layer 112 and a second patterned metal line layer 132 located above the first patterned metal line layer 112, one or more The multi-layer window 127 provides electrical interconnection between the first patterned metal line layer 112 and the second patterned metal line layer 132. It should be understood that additional metal lines (such as Mx+2, Mx+3, etc.) can be deposited and patterned to build on the metal interconnect structure. The additional metal lines can be formed in the same or similar manner as the second patterned metal line layer 132 and the first patterned metal line layer 112. Self-aligned vias in reduced patterning

The present invention relates to the manufacture of metal interconnect structures, in which one or more vias are formed after forming two connected metallization layers. The one or more via openings are formed by filling the one or more via openings with a conductive material after patterning the first metal layer and after patterning the second metal layer. The metal interconnection structure is manufactured by reduction patterning technology. The one or more vias are aligned with each of the two connected metallization layers. The alignment state between the one or more vias and the connected metallization layers is achieved by the following method: After forming two connected metallization layers, leaving some hard mask material above the patterned metal lines Or other insulating materials. When etching through one of the connected metallization layers, some of the remaining insulating material is removed to form one or more via openings. Due to the difference in etch selectivity between the surrounding dielectric material and insulating isolation material, and the difference in etch selectivity between the surrounding dielectric material and the connected metallization layer, the formation of one or more vias is limited to not Formed into the space of the surrounding dielectric material. In some embodiments, the one or more vias are fully aligned with the two connected metallization layers to provide improved contact area, reduced resistivity, reduced risk of TDDB failure, and reduced Risk of short circuit.

According to some embodiments, FIG. 3 shows a flowchart of an exemplary method of manufacturing a metal interconnect structure in an integrated circuit. The operations in the program 300 may be performed in a different order, and/or with different, fewer, or additional operations.

At block 310 of process 300, a first patterned metal line layer (Mx) is formed on the substrate by reduction patterning. In some embodiments, the substrate is a semiconductor wafer, is disposed on a semiconductor wafer, or part of a semiconductor wafer. The substrate may include a dielectric layer, and the first patterned metal line layer is formed on the dielectric layer. In some embodiments, a diffusion barrier layer and/or a liner layer may be deposited on the dielectric layer to separate the first patterned metal line layer from the dielectric layer. The first patterned metal line layer represents the first metallization layer in the metal interconnect structure. As used herein, the patterned metal wire layer may also be referred to as a metallization layer, metal layer, metal wire, metal feature, or wire feature. The first patterned metal line layer or the first metallization layer can also be referred to as the bottom patterned metal line layer or the bottom metallization layer.

At block 310 of process 300, forming the first patterned metal line layer by reduction patterning may involve one or more operations. In some embodiments, the operation of forming the first patterned metal line layer includes depositing a first metal layer on the substrate, depositing a first insulating layer on the first metal layer, and etching the first insulating layer to form a layer on the first metal layer. A first insulating feature is formed above and the first metal layer is etched to form a first patterned metal line layer defined by the plurality of first insulating features. In some embodiments, the first insulating layer can be a first hard mask layer, and the first insulating feature can be a first hard mask feature. The first metal layer may include any suitable metal that can be etched and patterned using a reduction patterning technique. For example, the first metal layer may include Mo, Ru, Al, or W. In some embodiments, any suitable deposition technique (eg, PVD, CVD, PECVD, ALD, or electrodeposition) is used to deposit the first metal layer. Electrodeposition may include, for example, electroplating or electroless plating. In some embodiments, the critical dimension (CD) of the patterned metal line of the first layer (Mx) is equal to or less than about 50 nm, equal to or less than about 20 nm, equal to or less than about 15 nm, or equal to or less than About 10 nm. In some embodiments, the pitch of the patterned metal lines of the first layer (Mx) is equal to or less than about 100 nm, equal to or less than about 40 nm, equal to or less than about 30 nm, or equal to or less than about 20 nm .

In some embodiments, the process 300 further includes forming a plurality of first insulating features on the first metal layer. The plurality of first insulating features can define patterned metal lines in the first metal layer. The process 300 further includes forming a first dielectric material in the gap between adjacent metal lines. The first dielectric material may surround the plurality of first insulating features and the first patterned metal line layer. After the first dielectric material is formed, a plurality of first insulating features are left to cover the top surface of the first patterned metal line layer. This can be used to limit the subsequent etching process when forming one or more vias.

4A-4D show schematic diagrams of an exemplary process of forming a first patterned metal wire layer on a substrate by reduction patterning. Compared with those shown in FIGS. 4A-4D, the formation of the first patterned metal line layer in the block 310 of the process 300 may involve different, fewer, or additional operations. In FIG. 4A, a first metal layer 401 (Mx) is deposited on the substrate 400. The first metal layer 401 in FIG. 4A is an unpatterned metal covering layer. In some embodiments, a spacer layer may be provided between the first metal layer 401 and the substrate 400. Examples of the liner layer include, but are not limited to, titanium nitride (TiN). Other examples include tantalum nitride (TaN), tungsten nitride (WN), and tungsten carbonitride (WCN). The thickness of the liner layer may be equal to or less than about 5 nm, or equal to or less than about 3 nm. In some embodiments, a dielectric layer 402 may be provided between the liner layer and the substrate 400. The liner layer is used to separate the first metal layer 401 from the dielectric layer 402.

In order to pattern the first metal layer 401, a first hard mask layer 403 may be deposited on the first metal layer 401. Examples of suitable hard mask materials can include silicon nitride, silicon oxide, silicon carbon nitride, silicon oxycarbide, silicon oxynitride, amorphous silicon, polysilicon, or carbon (e.g., amorphous carbon, metal doped Amorphous carbon, diamond-like carbon, polycrystalline diamond). The photoresist 404 and the photoresist lower layer 405 can be used to pattern the first hard mask layer 403, as shown in FIG. 1A, and the amorphous carbon layer 406 and the anti-reflection layer 407 are optionally disposed on the photoresist 404 and Between the first hard mask layers 403, as shown in FIG. 1A.

In FIG. 4B, a plurality of first hard mask features 408 are formed by patterning the first hard mask layer 403. The photoresist 404 can be patterned by using lithography (for example, EUV lithography) to realize the patterning of the first hard mask layer 403. In some embodiments, a smaller feature size can be formed by pitch doubling as shown in FIG. 1B. In some embodiments, additional masking operations may be performed to "cut" the first hard mask feature 408 into the desired configuration of the first hard mask feature 408, as shown in FIGS. 1C and 1D. Then, after additional masking and cutting operations, the first metal layer 401 will be patterned as defined by the first hard mask feature 408.

In FIG. 4C, the first metal layer 401 is patterned to form a first patterned metal line layer 409. During the metal line etching process, the first patterned metal line layer 409 is defined by a plurality of first hard mask features 408. The metal line etching process can selectively etch through the metal to form the first patterned metal line layer 409 without etching or substantially not etching the underlying dielectric layer 402. For example, subtractive plasma etching can remove the metal capping layer at a significantly higher etch rate than the underlying dielectric layer 402. The plurality of first hard mask features 408 are retained without removing the plurality of first hard mask features 408 from the first patterned metal line layer 409 in FIG. 4C. In some embodiments, a liner layer and/or a diffusion barrier layer may be deposited on the plurality of first hard mask features 408 and the first patterned metal line layer 409. The liner layer and/or diffusion barrier layer separates the first patterned metal line layer 409 and the plurality of first hard mask features 408 from the surrounding dielectric material.

In FIG. 4D, the first dielectric material 410 is deposited around the first patterned metal line layer 409 and the plurality of first hard mask features 408, and is filled in the gaps between adjacent patterned metal lines . The first dielectric material 410 can surround the first patterned metal line layer 409 and the first hard mask feature 408. In some embodiments, the first dielectric material 410 is deposited over the plurality of first hard mask features 408. After the metal capping layer is etched to form the first patterned metal line layer 409, the first dielectric material 410 is filled in the gaps, recesses, openings, or spaces previously filled by the metal capping layer. In some embodiments, after the first dielectric material 410 is deposited, a planarization process (such as CMP and/or blanket etchback) may be used to make the first dielectric material 410 and the first The hard mask feature 408 is flattened. The planarization process may expose the top surface of the first hard mask feature 408 covering the first patterned metal line layer 409. The first hard mask feature 408 is coplanar with the top surface of the first dielectric material 410. In some embodiments, the first dielectric material 410 is a low-k dielectric material. The low-k dielectric material may include fluorine-doped or carbon-doped silicon oxide or organic-containing low-k materials, such as OSG. In some embodiments, air gaps can be formed in the first dielectric material 410 between adjacent patterned metal lines, where the air gaps can be used to further make the first dielectric material between adjacent patterned metal lines The dielectric constant of the electrical material 410 decreases. The air gap is formed in the first dielectric material 410 in the gap between adjacent patterned metal lines, wherein the patterned metal line is separated from the air gap by the remaining first dielectric material 410.

Returning to FIG. 3, in block 320 of process 300, a second patterned metal layer is formed on the first patterned metal layer by reduction patterning. In some embodiments, a diffusion barrier layer and/or a liner layer may be deposited on the exposed surface of the first dielectric material and the plurality of first insulating features. The second patterned metal layer represents the second metalized layer in the metal interconnect structure.

At block 320 of process 300, forming the second patterned metal line layer by reduction patterning may involve one or more operations. In some embodiments, the operation of forming the second patterned metal wire layer includes depositing a second metal layer on the first dielectric material and the first patterned metal wire layer, and depositing a second insulating layer on the second metal layer. Layer, etching the second insulating layer to form a plurality of second insulating features over the second metal layer, and etching the second metal layer to form a second patterned metal line layer defined by the plurality of second insulating features. In some embodiments, the second insulating layer can be a second hard mask layer, and the second insulating feature can be a second hard mask feature. The second metal layer may include any suitable metal that can be etched and patterned using a reduction patterning technique. For example, the second metal layer may include Mo, Ru, Al, or W. In some embodiments, the second metal layer is the same material as the first metal layer. In some embodiments, any suitable deposition technique (eg, PVD, CVD, PECVD, ALD, or electrodeposition) is used to deposit the second metal layer. Electrodeposition may include, for example, electroplating or electroless plating. In some embodiments, the critical dimension of the patterned metal line of the second layer (Mx+1) is equal to or less than about 50 nm, equal to or less than about 20 nm, equal to or less than about 15 nm, or equal to or less than about 10 nm. In some embodiments, the pitch of the patterned metal lines of the second layer (Mx+1) is equal to or less than about 100 nm, equal to or less than about 40 nm, equal to or less than about 30 nm, or equal to or less than about 20 nm.

In some embodiments, the process 300 further includes forming a plurality of second insulating features on the second metal layer. The plurality of second insulating features can define a second patterned metal line layer in the second metal layer. The process 300 further includes forming a second dielectric material in the gap between adjacent metal lines. The second dielectric material may surround the plurality of second insulating features and the second patterned metal line layer. After the second dielectric material is formed, a plurality of second insulating features are retained to cover the top surface of the second patterned metal line layer. This can be used to limit the subsequent etching process when forming one or more vias.

4E-4H show schematic diagrams of an exemplary process of forming a second patterned metal wire layer on the first patterned metal wire layer by reduction patterning. Compared with those shown in FIGS. 4E-4H, the formation of the second patterned metal line layer in the block 320 of the process 300 may involve different, fewer, or additional operations. In FIG. 4E, a second metal layer 411 (Mx+1) is deposited on the first patterned metal line layer 409, on the first dielectric material 410, and on the plurality of first hard mask features 408. The second metal layer 411 in FIG. 4E provides a metal covering layer above the first dielectric material 410 and the plurality of first hard mask features 408. In some embodiments, a liner layer is provided between the second metal layer 411 and the first dielectric material 410, and between the second metal layer 411 and the plurality of first hard mask features 408. During the patterning of the second metal layer 411, a second hard mask layer 412 can be deposited on the second metal layer 411, wherein a photoresist 413 and a photoresist lower layer 414 can be used to pattern the second hard mask layer 412 As shown in FIG. 1J, and the amorphous carbon layer 415 and the anti-reflection layer 416 are optionally disposed between the photoresist 413 and the second hard mask layer 412, as shown in FIG. 1J.

In FIG. 4F, a plurality of second hard mask features 417 are formed by patterning the second hard mask layer 412. The patterning of the second hard mask layer 412 can be achieved by patterning the photoresist 413 by using lithography (for example, EUV lithography). In some embodiments, a smaller feature size can be formed by pitch doubling as shown in FIG. 1K. In some embodiments, additional masking operations may be performed to "cut" the second hard mask feature 417 into the desired configuration of the second hard mask feature 417, as shown in FIGS. 1L and 1M. Then, after additional masking and cutting operations, the second metal layer 411 will be patterned as defined by the second hard mask feature 417.

In FIG. 4G, the second metal layer 411 is patterned to form a second patterned metal line layer 418. During the metal line etching process, the second patterned metal line layer 418 is defined by a plurality of second hard mask features 417. The metal line etching process can selectively etch through the second metal layer 411 to form the second patterned metal line layer 418 without etching or substantially not etching the first dielectric material 410 and the plurality of first hard mask features 408 . For example, the reduced plasma etching can remove the metal capping layer at a significantly higher etch rate than the first dielectric material 410 and the plurality of first hard mask features 408. As used herein, "significantly higher etching rate" may refer to: the etching rate of the target material to be etched is at least 5 times greater than other materials. The plurality of second hard mask features 417 are retained, and the plurality of second hard mask features 417 are not removed from the second patterned metal line layer 418 in FIG. 4G. In some embodiments, a liner layer and/or a diffusion barrier layer may be deposited on the plurality of second hard mask features 417 and the second patterned metal line layer 418. The liner layer and/or the diffusion barrier layer separate the second patterned metal line layer 418 and the plurality of second hard mask features 417 from the surrounding dielectric material.

In FIG. 4H, the second dielectric material 419 is deposited around the second patterned metal line layer 418 and the plurality of second hard mask features 417, and is filled in the gaps between adjacent patterned metal lines . The second dielectric material 419 can surround the second patterned metal line layer 418 and the second hard mask feature 417. In some embodiments, the second dielectric material 419 is deposited over the plurality of second hard mask features 417. After the metal capping layer is etched to form the second patterned metal line layer 418, the second dielectric material 419 is filled in the gaps, recesses, openings, or spaces previously filled by the metal capping layer. In some embodiments, after the second dielectric material 419 is deposited, a planarization process (such as CMP and/or blanket etchback) may be used to make the second dielectric material 419 and the second The hard mask feature 417 is flattened. The planarization process may expose the top surface of the second hard mask feature 417 covering the second patterned metal line layer 418. The second hard mask feature 417 is coplanar with the top surface of the second dielectric material 419. In some embodiments, the second dielectric material 419 is a low-k dielectric material. In some embodiments, an air gap may be formed in the second dielectric material 419 between adjacent patterned metal lines, wherein the patterned metal line is separated from the air gap by the remaining second dielectric material 419 open.

Returning to FIG. 3, at block 330 of the process 300, one or more vias providing electrical interconnection between the first patterned metal line layer and the second patterned metal line layer are formed to form a metal interconnection structure . The one or more vias are formed after forming the first patterned metal wire layer and the second patterned metal wire layer. In addition, the one or more vias are formed after the following steps: the reduction patterning of the first metal layer and the use of the first dielectric material to fill the gaps around the first patterned metal line layer, and the second metal The layer reduction patterning and the use of a second dielectric material to fill the gaps around the second patterned metal line layer. In other words, the operation of patterning the one or more vias is performed after defining two metallization layers.

At block 330 of process 300, the formation of the one or more vias may involve one or more operations. By forming one or more via openings through at least the second patterned metal wire layer to the first patterned metal wire layer, and filling the one or more via openings with a conductive material, the one or more via openings can be formed More interlayer windows. The operation of forming one or more via openings includes etching through one or more second insulating features, etching through the second patterned metal line layer, and etching through one or more first insulating features. Etching through three or more layers of material without etching or substantially not etching the surrounding material can present many challenges. In some embodiments, etching through one or more second insulating features occurs without etching or substantially not etching the second dielectric material. In some embodiments, etching through the second patterned metal line layer occurs without etching or substantially without etching the second dielectric material. In some embodiments, etching through one or more first insulating features occurs without etching or substantially not etching the first dielectric material. As used herein, "substantially not etched" may refer to the following etching process: the etching rate of the target material (for example, dielectric) is at least 1/5 times the etching rate of the target material (for example, hard mask) to be etched Low etching treatment. In other words, the etch selectivity of the target material to be etched to other materials is equal to or greater than about 5:1. The operation of etching through three or more layers of materials may use the same etching process using the same etchant, or may use different etching processes using different etchants. In some embodiments, filling one or more via openings with a conductive material includes backfilling where the second patterned metal line layer and one or more first insulating features are etched away. These backfill operations form the one or more vias to provide electrical connection with the remaining second patterned metal line layer.

The operation of forming one or more via openings up to the first patterned metal wire layer can be restricted by the first insulating feature and the second insulating feature, so that the one or more via openings are not biased Shifted or misplaced. Specifically, the first insulating feature and the second insulating feature are used to limit the etching process, so that the via opening is not formed in the surrounding dielectric material. In the case where the first insulating feature and the second insulating feature are not retained after the first patterned metal line layer and the second patterned metal line layer are formed, alignment or coverage errors may occur, which may occur in the first patterned metal An undesirable electrical connection (such as an undesirable short circuit) is generated between the wire layer and the second patterned metal wire layer.

The material difference between the first and second insulating features and the surrounding dielectric material promotes etching contrast, thus restricting the formation of vias, so that one or more vias can interact with the first patterned metal line layer and the second 2. The patterned metal wire layer is self-aligned. The conventional manufacturing process for providing a via window between metallization layers usually uses the same dielectric material as the space compensation between the metallization layers, and the first and second insulating features of the present invention provide the dielectric The material difference of the material has different etching selectivity.

The vertical wall portion of the surrounding dielectric material serves as an etching boundary for limiting the etching of the via, so that the formation of the via is aligned with the first patterned metal wire layer and the second patterned metal wire layer. The via etching does not extend into the surrounding dielectric material or adjacent vias. By constraining the formation of vias, this ensures self-alignment of one or more vias with the first patterned metal line layer and the second patterned metal line layer. When one or more vias are aligned with at least the first patterned metal wire layer, the one or more vias directly contact the top surface of the first patterned metal wire layer without overlapping. Therefore, the one or more vias will not overlap with the first dielectric material, and the problem of TDDB degradation and short circuits caused by misaligned vias is solved. When one or more vias are aligned with at least the second patterned metal line layer, the one or more vias are filled with conductive material where one or more patterned metal lines of the previous second layer were etched, And it does not overlap with the second dielectric material. This solves the problems of reduced contact area, higher via resistance, and reduced reliability due to misaligned vias. Therefore, the self-aligned via patterning solution can provide one or more vias that are completely aligned with the second patterned metal line layer and the first patterned metal line layer.

In some embodiments, the process 300 further includes depositing a via mask over the second plurality of insulating features and the second dielectric material, and patterning one or more holes in the via mask to define a Or more via openings. Each of the one or more porous holes has a diameter or width larger than the critical dimension of the second patterned metal wire layer and/or the first patterned metal wire layer. In some embodiments, each of the one or more porous holes has a diameter or width that is up to about 100% larger than the critical dimension of the second patterned metal line layer and/or the first patterned metal line layer. The diameter or width of one or more holes in the via mask is too large, so as to be larger than the diameter or width of one or more vias actually formed. In this way, any misalignment between the one or more porous holes and the underlying layer to be etched will not leave the target material to be etched. By having too large holes, this also ensures that the underlying layer to be etched is actually etched regardless of any alignment errors. This is partly due to making the second insulating feature selective to the second dielectric material during etching, and making the second patterned metal line layer selective to the second dielectric material during etching, And during etching, the first insulating feature is made selective to the first dielectric material. However, it should be understood that the diameter or width of one or more holes is not so large that there is a risk of extending into adjacent metal lines. Therefore, the diameter or width of one or more holes in the via mask is slightly too large to solve the problem of misalignment tolerance, but not too large to etch into other metal lines.

4I-4L shows a schematic diagram of an exemplary process for forming one or more vias, where the one or more vias are used between the first patterned metal wire layer and the second patterned metal wire layer Provide electrical interconnection. Compared with those shown in FIGS. 4I-4L, the formation of one or more vias in block 330 of process 300 may involve different, fewer, or additional operations. In FIG. 4I, a via mask 420 may be formed over the plurality of second hard mask features 417 and the second dielectric material 419. In FIG. The via mask 420 may have one or more holes 421 for patterning one or more via openings through at least the second patterned metal line layer 418. The via mask 420 may include one or more film layers for patterning, where the one or more film layers may include photoresist 422, photoresist underlayer 423, spin-on carbon 424 (SoC), and a mask Layer 425 (e.g., hard mask layer). A lithography process may be applied to the photoresist 422 to pattern the mask layer 425, wherein one or more holes may be formed in the mask layer 425. Portions of the mask layer 425 can be etched to form one or more holes for defining one or more via openings. It is intended to align one or more holes in the mask layer 425 with each of the following: the second hard mask feature 417 in which one or more vias will be formed, the second patterned metal line layer 418, And the first hard mask feature 408. In some embodiments, the diameter of the one or more holes is larger than the critical size of the second patterned metal wire layer 418 and/or the first patterned metal wire layer 409. In some embodiments, the critical dimension of the first patterned metal line layer 409 or the second patterned metal line layer 418 may be equal to or less than about 50 nm, equal to or less than about 20 nm, or equal to or less than about 10 nm . In some embodiments, the diameter is about 1% to about 100% larger, about 5% to about 100% larger than the critical dimension of the second patterned metal line layer 418 and/or the first patterned metal line layer 409. %, or greater, about 10% to about 50%. The diameter of the one or more holes is larger than the actual one or more via openings formed through the second patterned metal line layer 418, where the difference in size resolves some misalignment tolerance issues without etching adjacent metals line. In some embodiments, the mask layer 425 of the via mask 420 includes a different material from the second hard mask feature 417, the second patterned metal line layer 418, and the first hard mask feature 408 s material.

In FIG. 4J, one or more via openings 426 are formed through at least the second patterned metal line layer 418 to the first patterned metal line layer 409 by etching. One or more via openings 426 are defined by one or more holes 421 in the via mask 420. It is intended that one or more via openings 426 are aligned with one or more patterned metal lines of the second layer 418 and one or more patterned metal lines of the first layer 409. By leaving the electrically insulating material (such as the first and second hard mask features) on the top surface of the patterned metal line that has a different etch selectivity from the surrounding dielectric material, the misalignment tolerance problem can be solved. In this way, the electrically insulating material is used to limit the etching process so that one or more via openings 426 will not be formed in the surrounding dielectric material. The problem of misalignment tolerance can also be solved by the following methods: making the via mask 420 have slightly too large holes, and ensuring that the etching process compares the surrounding dielectric materials to the second hard mask feature 417 and the second patterning The metal line layer 418 and the first hard mask feature 408 are selective. In this way, the excessively large holes in the via mask 420 reduce the risk that the etching process misses the target material to be etched, so the operation of forming one or more via openings 426 does not leave any target material.

The operation of forming one or more via openings 426 includes etching through one or more second hard mask features 417, etching through the second patterned metal line layer 418, and etching through one or more first hard masks. Cover feature 408. The etching process stops on the first patterned metal line layer 409. After the etching process, the first patterned metal line layer 409 is exposed. The operation of etching through one or more second hard mask features is selective to the second dielectric material 419, and the operation of etching through the second patterned metal line layer 418 is relatively selective to the second dielectric material 419 The operation of etching through one or more first hard mask features 408 is selective and selective relative to the first dielectric material 410. In FIGS. 5A and 5B taken along line AA and line BB of FIG. 4J, respectively, it can be observed that the via opening 426 is formed through one or more second hard mask features 417, through the second patterned metal line Layer 418 and pass through one or more first hard mask features 408.

In FIG. 4K, a conductive material 427 is deposited in one or more via openings 426 to fill the one or more via openings 426. By filling the one or more via openings 426 previously filled with one or more first hard mask features 408 and second patterned metal line layer 418, one or more vias 428 are formed. In some embodiments, the conductive material 427 is the same material as the first patterned metal wire layer 409 and the second patterned metal wire layer 418. For example, the conductive material 427 includes Mo, Ru, Al, or W. In some embodiments, the conductive material 427 is a different material from the first patterned metal wire layer 409 and the second patterned metal wire layer 418. In some embodiments, the conductive material 427 is deposited by a suitable deposition technique (such as PVD, CVD, PECVD, ALD, or electrodeposition) so as to at least substantially fill one or more via openings 426. In some embodiments, before filling the one or more via openings 426 with the conductive material 427, a diffusion barrier layer and/or a liner layer may be deposited in the one or more via openings 426. The diffusion barrier layer and/or the liner layer may separate one or more vias 428 from the surrounding dielectric material.

One or more vias 428 are formed by backfilling the places where the second patterned metal line layer 418 and the one or more first hard mask features 408 are etched away with the conductive material 427. By backfilling, the conductive material 427 contacts the exposed first patterned metal line layer 409 and provides an electrical interconnection with the second patterned metal line layer 418. In some embodiments, the conductive material 427 is deposited to fill one or more via openings 426, to fill one or more holes in the mask layer 425, and to provide conductivity over the one or more via openings 426 Covering layer of material 427. This provides a cover layer of conductive material 427 above one or more via openings 426.

In FIG. 4L, a part of the conductive material 427 is removed so that the remaining part of the conductive material 427 will be filled with one or more first hard mask features 408 and the second patterned metal line layer 418 previously. The layer window opening 426 is filled. These operations of removing the portion of the conductive material 427 include etching the conductive material 427 in the following areas: one or more of the via openings 426, one or more holes in the mask layer 425, and one or more The second hard mask feature 417 previously filled one or more via openings 426. This removes the cover layer of the conductive material 427, and leaves the conductive material 427 to the bottom level of the second hard mask feature 417. Therefore, one or more recesses can be formed through the one or more holes to the bottom level of the second hard mask feature 417, thereby providing at least one recessed metal filling 429 to the bottom level of the second hard mask feature 417 . In FIG. 4L, the metal interconnect structure is fabricated with two connected metallization layers connected by one or more fully aligned vias 428.

Returning to FIG. 3, the process 300 may further include covering the exposed portion of the conductive material with a third dielectric material. In some embodiments, a third dielectric material may be deposited over the recessed via metal fill and the second insulating feature. The third dielectric material can be etched or polished to make it coplanar with the second insulating feature. In some embodiments, the third dielectric material may be the same material as the second insulating feature.

In some embodiments, the process 300 may further include forming a third patterned metal line layer (Mx+2) on the second patterned metal line layer by reduction patterning. The third patterned metal line layer may represent the third metalization layer in the metal interconnect structure. In some embodiments, one or more additional dielectric windows may be formed that provide electrical interconnections between the second patterned metal line layer and the third patterned metal line layer. It is possible to continue to manufacture additional metallization layers and vias in the metal interconnection structure, in which additional metallization layers can be formed in the same or similar manner as the first metallization layer and the second metallization layer, and the The electrical interconnection between one patterned metal line layer and the second patterned metal line layer forms additional vias in the same or similar manner as one or more vias.

4M-4N show schematic diagrams of an exemplary process of using a third dielectric material to cover the recessed via metal filling. Compared with those shown in FIGS. 4M-4N, the metal filling operation of capping the recessed vias may involve different, fewer, or additional operations. In FIG. 4M, the third dielectric material 430 is deposited over the plurality of second hard mask features 417 and the recessed via metal fill 429. The third dielectric material 430 may be deposited in one or more recesses formed after the portion of the conductive material 427 filling the one or more via openings 426 is removed. In some embodiments, the third dielectric material 430 is the same material as the second hard mask feature 417. In some embodiments, the third dielectric material 430 is deposited over the mask layer 425. The third dielectric material 430 may be the same material or the same type of material as the mask layer 425. The third dielectric material 430 is deposited to cover the exposed portion of the conductive material 427.

In FIG. 4N, a planarization process is performed to remove the third dielectric material 430 up to the second hard mask feature 417. The planarization process may include CMP and/or blanket etchback, so that the third dielectric material 430 and the second hard mask feature 417 are coplanar. In addition, while removing some of the third dielectric material 430, the mask layer 425 above the plurality of second hard mask features 417 can be removed. The third dielectric material 430 and the second hard mask feature 417 are used to cover or cover the second patterned metal line layer 418. Subsequently, additional patterned metal line layers and additional vias can be formed in the same or similar manner as the first patterned metal line layer 409, the second patterned metal line layer 418, and one or more vias 428. After the recessed via metal filling 429 is capped, in FIGS. 5C and 5D taken along lines C-C and D-D in FIG. 4N, a metal interconnect structure can be observed. The metal interconnection structure in FIGS. 5C and 5D shows a fully aligned via 428, which provides an electrical interconnection between the first patterned metal line layer 409 and the second patterned metal line layer 418.

After forming one or more vias 428 that provide electrical interconnections between the first patterned metal line layer 409 and the second patterned metal line layer 418, a metal interconnection structure is formed. An exemplary metal interconnect structure of an integrated circuit is shown in FIGS. 5C and 5D. The metal interconnection structure may include a first patterned metal line layer 409, a plurality of first insulating features 431 on at least some of the patterned metal lines in the first layer 409, and a second patterned metal line layer 409. The patterned metal line layer 418 and a plurality of second insulating features 432 on at least some of the patterned metal lines in the second layer 418. The metal interconnection structure further includes one or more vias 428 that provide electrical interconnection between the first patterned metal line layer 409 and the second patterned metal line layer 418, wherein the one or more vias 428 is completely aligned with the first patterned metal line layer 409 and the second patterned metal line layer 418. The first dielectric material 410 surrounds the first patterned metal line layer 409 and the plurality of first insulating features 431. The second dielectric material 419 surrounds the second patterned metal line layer 418 and the second insulating feature 432. The one or more vias 428 are completely aligned such that the one or more vias 428 directly contact the first patterned metal line layer 409 without overlapping the first dielectric material 410 or the second dielectric material 419. The one or more vias 428 are formed after patterning the first patterned metal wire layer 409 and the second patterned metal wire layer 418.

In some embodiments, the metal interconnect structure further includes a third dielectric material 430 above the recessed via metal filling 429, wherein the top surface of the second patterned metal line layer 418 is covered by the second insulating feature 432 The covered and recessed via metal filling 429 is covered by the third dielectric material 430. In some embodiments, the third dielectric material 430 is the same material as the second insulating feature 432. In some embodiments, each of the first dielectric material 410 and the second dielectric material 419 is a low-k dielectric material. The first insulating feature 431 and the second insulating feature 432 have a different etch selectivity from the low-k dielectric material. In some embodiments, the first patterned metal line layer 409 and the second patterned metal line layer 418 include Mo, Ru, Al, or W. In some embodiments, the one or more vias 428 include Mo, Ru, Al, or W, wherein the material of the one or more vias 428 and the first patterned metal line layer 409 and the second pattern The material of the metal wire layer 418 is the same or different.

The processes described herein can be used with, for example, lithographic patterning tools or processes used to manufacture semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Generally speaking, although not necessary, such tools/processing will be used or performed together in a common manufacturing plant. Film lithography patterning usually includes some or all of the following operations. Each operation is provided with several possible tools: (1) Use spin-coating or spray-coating tools to coat the work piece (ie, the substrate) Distribute the photoresist; (2) Use a hot plate or oven or UV curing tools to cure the photoresist; (3) Use tools (for example, a wafer stepper) to expose the photoresist to visible light or UV light or x-ray light (4) Develop the photoresist to use tools (for example, a wet cleaning table) to selectively remove the photoresist and thereby pattern it; (5) Use dry or plasma-assisted etching tools to pattern the photoresist Transfer to the underlying film or work piece; and (6) Use tools (for example, RF or microwave plasma photoresist stripper) to remove the photoresist. in conclusion

In the above description, a large number of specific details are explained to provide a thorough understanding of the proposed implementation. The disclosed embodiments can be implemented without some or all of these specific details. In other examples, in order not to obscure the disclosed embodiments, the conventional processing operations will not be described in detail. Although the disclosed embodiments are described together with specific embodiments, it should be understood that they are not intended to limit the disclosed embodiments.

Although the above embodiments have been described in some details for the purpose of clear understanding, it is obvious that certain changes and modifications can be implemented within the scope of the appended patent application. It should be noted that there are many alternative ways to implement the processes, systems, and devices of embodiments of the present invention. Therefore, the embodiments of the present invention are to be regarded as illustrative rather than restrictive, and the embodiments are not limited to the details provided herein.

100: substrate 101: The first metal layer 102: Dielectric layer 103: The first hard mask layer 104: photoresist 105: photoresist lower layer 106: Amorphous carbon 107: Anti-reflection layer 108: The first hard mask feature 109: photoresist 110: photoresist lower layer 111: Spin-coated carbon 112: first patterned metal wire layer 113: The first dielectric material 114: air gap 115: Interlayer window mask 116: photoresist 117: photoresist lower layer 118: Spin-coated carbon 119: One or more holes 120: Interlayer window opening 121: second metal layer 122: second hard mask layer 123: photoresist 124: photoresist lower layer 125: Amorphous carbon 126: Anti-reflective layer 127: Interlayer window 128: Second hard mask feature 129: photoresist 130: photoresist lower layer 131: Spin-coated carbon 132: second patterned metal wire layer 133: second dielectric material 300: program 310: Block 320: block 330: Block 400: substrate 401: first metal layer 402: Dielectric layer 403: The first hard mask layer 404: photoresist 405: photoresist lower layer 406: Amorphous carbon layer 407: Anti-reflective layer 408: The first hard mask feature 409: first patterned metal wire layer 410: The first dielectric material 411: second metal layer 412: second hard mask layer 413: photoresist 414: photoresist lower layer 415: Amorphous carbon layer 416: Anti-reflective layer 417: Second hard mask feature 418: second patterned metal wire layer 419: second dielectric material 420: Interlayer window mask 421: One or more holes 422: photoresist 423: photoresist lower layer 424: Spin-on carbon 425: Mask layer 426: Interlayer window opening 427: conductive material 428: Interlayer Window 429: Recessed via metal filling 430: The third dielectric material 431: First insulation feature 432: Second insulation feature

1A-10 show schematic diagrams of an exemplary process for forming a metal interconnect structure by reduction patterning.

2A shows a schematic cross-sectional view of an exemplary partially processed metal interconnection structure taken from line A-A of FIG. 1F.

2B-1 shows a schematic cross-sectional view of an exemplary partially processed metal interconnect structure from line B-B of FIG. 1H, in which the via opening is aligned with the underlying metal line.

2B-2 shows a schematic cross-sectional view of an exemplary partially processed metal interconnect structure from line C-C of FIG. 1H, where the via opening is not aligned with the underlying metal line.

2C-1 shows a schematic cross-sectional view of an exemplary partially processed metal interconnect structure from line C-C of FIG. 1J, in which the via is aligned with the underlying metal line.

2C-2 shows a schematic cross-sectional view of an exemplary partially processed metal interconnect structure from line C-C of FIG. 1J, where the via is not aligned with the underlying metal line.

2D-1 shows a schematic cross-sectional view of an exemplary metal interconnect structure from line D-D of FIG. 1N, in which the via is aligned with the overlying metal line.

2D-2 shows a schematic cross-sectional view of an exemplary metal interconnection structure from line D-D in FIG. 1N, where the via is not aligned with the overlying metal line.

According to some embodiments, FIG. 3 shows a flowchart of an exemplary method of manufacturing a metal interconnect structure in an integrated circuit.

According to some embodiments, FIGS. 4A-4N show schematic diagrams of an exemplary process for forming a metal interconnect structure with fully aligned vias by reduced patterning.

According to some embodiments, FIG. 5A shows a schematic cross-sectional view of an exemplary partially processed metal interconnect structure taken from line A-A of FIG. 4J.

According to some embodiments, FIG. 5B shows a schematic cross-sectional view of an exemplary partially processed metal interconnection structure taken from line B-B of FIG. 4J.

According to some embodiments, FIG. 5C shows a schematic cross-sectional view of an exemplary metal interconnection structure from the line C-C of FIG. 4N.

According to some embodiments, FIG. 5D shows a schematic cross-sectional view of an exemplary metal interconnection structure from the line D-D of FIG. 4N.

409: first patterned metal wire layer

410: The first dielectric material

418: second patterned metal wire layer

419: second dielectric material

428: Interlayer Window

430: The third dielectric material

431: First insulation feature

432: Second insulation feature

Claims (20)

A method of manufacturing a metal interconnection structure, the method comprising: Forming a first layer of patterned metal lines on a substrate by subtractive patterning; Forming a second layer of patterned metal lines above the first layer of patterned metal lines by reduction patterning; and After the patterned metal lines of the second layer are formed, one or more vias that provide electrical interconnections between the patterned metal lines of the first layer and the patterned metal lines of the second layer are formed, thereby The metal interconnection structure is formed. The method for manufacturing a metal interconnect structure of claim 1, wherein the step of forming the one or more vias includes: Forming one or more via openings through at least the patterned metal line of the second layer to the patterned metal line of the first layer; and Fill the one or more via openings with a conductive material. For example, the method of manufacturing a metal interconnection structure in claim 1, further including: Forming a plurality of first insulating features on the patterned metal line of the first layer; and After forming the plurality of first insulating features, a first dielectric material is formed in the gaps between adjacent metal lines of the first layer. For example, the method of manufacturing a metal interconnection structure in claim 3 further includes: Forming a plurality of second insulating features on the patterned metal line of the second layer; and After forming the plurality of second insulating features, a second dielectric material is formed in the gaps between adjacent metal lines of the second layer. The method for manufacturing a metal interconnect structure of claim 4, wherein the step of forming the one or more vias includes: Etching through one or more second insulating features; Etching the patterned metal line through the second layer; Etching through one or more first insulating features to form one or more via openings to expose the patterned metal lines of the first layer; and A conductive material is deposited in the one or more via openings to form the one or more vias on the exposed patterned metal lines of the first layer. For example, the method for manufacturing a metal interconnection structure in claim 5 further includes: Forming a via mask over the plurality of second insulating features and the second dielectric material; and Pattern one or more holes in the via mask, wherein each of the one or more holes has a larger critical size than the patterned metal line of the second layer and/or the patterned metal line of the first layer (CD) diameter or width. The method for manufacturing a metal interconnection structure of claim 6, wherein each of the one or more holes has a CD that is greater than the patterned metal line of the second layer and/or the patterned metal line of the first layer by up to about 100 % Of the diameter or width. The method for manufacturing a metal interconnection structure according to claim 6, wherein the step of depositing the conductive material comprises: using the conductive material to fill previously etched portions of the first insulating features and the patterned metal lines of the second layer. The method of manufacturing a metal interconnect structure of claim 5, wherein the operation of etching through the one or more second insulating features is relative to the second dielectric material surrounding the one or more second insulating features Selective, and wherein the operation of etching through the patterned metal line of the second layer is selective with respect to the second dielectric material surrounding the patterned metal line of the second layer, and wherein the etching through the one or more The operation of the multiple first insulating features is selective relative to the first dielectric material surrounding the one or more first insulating features. According to claim 5, the method of manufacturing a metal interconnection structure, wherein each of the patterned metal line of the first layer, the patterned metal line of the second layer, and the conductive material includes Mo, Ru, Al, or W . The method of manufacturing a metal interconnection structure of claim 4, wherein each of the first dielectric material and the second dielectric material includes a low-k dielectric material, and wherein the plurality of first insulating features and the plurality of first insulating features Each of the two insulating features has a different etch selectivity from the low-k dielectric material. The method for manufacturing a metal interconnection structure according to any one of claims 1-11, wherein the one or more vias are completely connected to the patterned metal line of the first layer and the patterned metal line of the second layer alignment. The method for manufacturing a metal interconnection structure according to any one of claims 1-11, wherein the CD of the patterned metal line of the first layer and the patterned metal line of the second layer is equal to or less than about 20 nm. The method for manufacturing a metal interconnection structure according to any one of claims 1-11, wherein the step of forming the patterned metal line of the first layer comprises: Depositing a first metal on the substrate; Depositing a first mask layer on the first metal; Etching the first mask layer to form a plurality of first insulating features on the first metal; and Etching the first metal to form the patterned metal lines of the first layer defined by the plurality of first insulating features; The step of forming the patterned metal line of the second layer includes: Depositing a second metal on the patterned metal lines of the first layer; Depositing a second mask layer on the second metal; Etching the second mask layer to form a plurality of second insulating features on the second metal; and The second metal is etched to form the second layer of patterned metal lines defined by the plurality of second insulating features. A metal interconnection structure for integrated circuits, the metal interconnection structure comprising: The patterned metal line of the first layer; A plurality of first insulating features located on at least some of the patterned metal lines in the first layer; The patterned metal line of the second layer is located above the patterned metal line of the first layer; A plurality of second insulating features located on at least some of the patterned metal lines in the second layer; and One or more vias, which provide electrical interconnection between the patterned metal lines of the first layer and the patterned metal lines of the second layer, wherein the one or more vias are connected to the first The patterned metal lines of the layer and the patterned metal lines of the second layer are completely aligned. For example, the metal interconnection structure for integrated circuits of claim 15, wherein the one or more vias extend through the first insulating features, so that the patterned metal lines of the first layer and the second layer Layer of patterned metal line contacts. For example, the metal interconnection structure for integrated circuits in claim 15 further includes: A first dielectric material that surrounds the patterned metal lines of the first layer and the plurality of first insulating features; and The second dielectric material surrounds the patterned metal line of the second layer and the plurality of second insulating features. For example, the metal interconnection structure for integrated circuits in claim 17 further includes: The third dielectric material is located above the metal filling of the recessed vias of the one or more vias. For example, the metal interconnection structure for integrated circuits of claim 17, wherein each of the first dielectric material and the second dielectric material includes a low-k dielectric material, and wherein the plurality of first insulating features and Each of the plurality of second insulating features has a different etch selectivity from the low-k dielectric material. The metal interconnection structure for integrated circuits according to any one of claim 15-19, wherein the one or more vias comprise a conductive material, wherein the patterned metal line of the first layer, the second layer Each of the patterned metal lines of the layer and the conductive material includes Mo, Ru, Al, or W.

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