KR100542496B1 - Method for fabricating semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor device capable of simultaneously forming a plurality of contact holes provided in an electrode of each layer in the manufacture of a capacitor having a multilayer structure.

A method of manufacturing a semiconductor device of the present invention includes forming a first interlayer insulating film on a semiconductor substrate; and a first metal layer, a first dielectric film, a second metal layer, a second dielectric film, and a third metal layer on the first interlayer insulating film. Stacking an oxide layer; and forming an etch inhibiting film on the third metal layer; and selectively patterning the etch inhibiting film to the first metal layer to form first, second, and third electrodes; and Stacking a second interlayer insulating film on the entire surface of the substrate including the etch inhibiting film; and forming an etch mask for forming contact holes exposing the first, second, and third electrodes on the second interlayer insulating film. And etching the second interlayer insulating layer using the etching mask to expose the first dielectric layer, the second dielectric layer, and the etch inhibiting layer; and the first dielectric layer, the second dielectric layer, and the etching inhibiting layer. By removing a film comprising the step of completing a contact hole exposing the first, second and third electrodes it is characterized in that formed.

Etch Suppression, Capacitor, Multilayer Structure

Description

Method for fabricating semiconductor device {Method for fabricating semiconductor device}             

1 is a structural cross-sectional view of a capacitor of a semiconductor device according to the prior art.

2 is a structural cross-sectional view of a capacitor of a semiconductor device according to another conventional technology.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Description of the main parts of the drawing

301 semiconductor substrate 302 first interlayer insulating film

303: first electrode 304: first dielectric film

305: second electrode 306: second dielectric film

307: third electrode 308: etching inhibiting film

309: second interlayer insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in the manufacture of a capacitor having a multilayer structure, the present invention relates to a method for manufacturing a semiconductor device capable of simultaneously forming a plurality of contact holes provided in an electrode of each layer.

In a unit cell composed of a MOS transistor and a capacitor, the characteristics of the device are greatly influenced by the capacitance of the capacitor. In recent years, as semiconductor devices have been highly integrated, the area occupied by capacitors in devices has also been reduced, so that capacitors having large capacitance within a small area are required.

The methods that can be considered to improve the capacitance of the capacitor include increasing the effective area of the capacitor, thinning the dielectric film located between the upper electrode and the lower electrode, forming a dielectric film with a high dielectric constant material, and the like. have.

Among the above three methods, the thinning of the dielectric film has a problem of lowering the reliability of the semiconductor device, and the formation of the dielectric film from a material having a high dielectric constant has a burden of developing a new capacitor manufacturing process. Accordingly, research is focused on a method of improving the capacitance by increasing the effective area of the capacitor.

On the other hand, the structure of a conventional conventional capacitor is as follows.

As shown in FIG. 1, a conventional capacitor has a structure in which a lower electrode 102, a dielectric film 104, and an upper electrode 105 are sequentially formed on a semiconductor substrate. In the conventional capacitor structure, the lower electrode 102 has a planar structure, so that the area of the lower electrode is reduced in proportion to the miniaturization of design rules of the semiconductor device. Therefore, there is a problem that a limit is exposed to maximize the capacitance in the micro device. For reference, reference numeral 103 is an interlayer insulating film.

In order to improve this, a capacitor having a multilayer structure has been proposed. 2 is a cross-sectional view showing the structure of another conventional capacitor.

As shown in FIG. 2, another conventional capacitor includes a first electrode 202, a second electrode 204, and a third electrode 206 on a semiconductor substrate 201 and the first electrode 202. And a first dielectric film 203 and a second dielectric film 205 between the second electrode 204 and the second electrode 204 and the third electrode 206, respectively. In this manner, capacitors are formed in a multilayer structure and dielectric layers are provided for each layer to increase capacitance.

However, such a multilayer capacitor has a step between each electrode in a subsequent step of forming a contact hole exposing the first, second and third electrodes 202, 204, and 206 after laminating the interlayer insulating film 207. The depths d1, d2, and d3 of the contact holes 208 are different from each other. Accordingly, in the process of forming a contact hole, a relatively upper electrode is exposed in advance than the lower electrode, so that the upper electrode is damaged by etching. In order to solve this problem, in the related art, a first etching process exposing the upper electrodes, for example, the first and second electrodes, and a second exposing electrode, for example, the second and third electrodes, are exposed. A plurality of interlayer insulating film etching processes for forming contact holes, such as an etching process, are selected. As such, as a plurality of interlayer insulating layer etching processes are selected to solve the step difference problem between electrodes, the process becomes complicated and causes an increase in manufacturing cost.

The present invention has been made to solve the above problems, in the manufacture of a capacitor having a multi-layer structure, to provide a method for manufacturing a semiconductor device capable of simultaneously forming a plurality of contact holes provided in the electrode of each layer For the purpose of

The method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a first interlayer insulating film on a semiconductor substrate; and a first metal layer, a first dielectric film, a second metal layer, on the first interlayer insulating film; Stacking a second dielectric layer and a third metal layer; and forming an etch inhibiting film on the third metal layer; and selectively patterning the etch inhibiting film to the first metal layer to form first, second, and third metal layers. Forming an electrode; and laminating a second interlayer insulating film on the entire surface of the substrate including the etch inhibiting film; and contact holes exposing the first, second, and third electrodes on the second interlayer insulating film. Forming an etch mask to form a etch mask; and etching the second interlayer insulating layer by using the etch mask to expose the first dielectric layer, the second dielectric layer, and the etch inhibiting layer. Conductor film, characterized in that the second dielectric layer and etching to remove suppression film comprises a step to complete the contact holes exposing the first, second and third electrodes.

Preferably, the etch inhibiting film may be formed of a silicon nitride film.

Preferably, the first and second dielectric films may be formed of a silicon nitride film.

Preferably, the etch inhibiting film may be formed to a thickness of 200 to 400 kPa.

According to an aspect of the present invention, an etching suppression film having a relatively slow etching speed than an interlayer insulating film is formed on a top electrode of a capacitor having a multi-layer structure to a predetermined thickness, and thus a plurality of electrodes formed with different steps are formed by etching. It can be exposed simultaneously in time without damage to simplify the process of forming a contact hole.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. 3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

First, as shown in FIG. 3A, a first interlayer insulating film 302 is laminated on the semiconductor substrate 301. The first interlayer insulating layer 302 may be formed by using a TEOS-based oxide film such as low pressure tetra ethyl ortho silicate (LP-TEOS), O ₃ -TEOS, d-TEOS, or high density plasma CVD (High Density Plasma CVD). It can be formed by using a layer of Fluorine Silicate Glass (FSG), Undoped Silicate Glass (USG) or SiH ₄ film or BPSG. Although not shown in the figure, elements such as a MOS transistor are formed in the active region under the first interlayer insulating film.

Subsequently, a first metal layer 303, a first dielectric layer 304, a second metal layer 305, a second dielectric layer 306, and a third metal layer 307 are sequentially stacked on the first interlayer insulating layer 302. do. Here, the first and second dielectric layers 304 and 306 may be used as materials having high dielectric constant, and may be formed to have a thickness of 200 to 1000 GPa using, for example, a nitride film. In addition, the first, second and third metal layers 303, 305, 307 are preferably formed of aluminum-copper (Al-Cu), and the first and second dielectric layers (in addition to the aluminum-copper (Al-Cu) layer) may be formed. 306) metals such as platinum (Pt), ruthenium (Ru), iridium (Ir), rhodium (Rh), osmium (Os), etc., which are weakly reactive and have a high work function, may be used. The metal layer may be further formed in addition to the first, second, and third metal layers 303, 305, 307 according to the multilayer structure of the capacitor.

In the state where the third metal layer 307 is formed, an etch inhibiting film 308 is stacked on the third metal layer 307. A nitride film may be used as the etch inhibiting film 308 and may be formed to a thickness of 200 to 400 kPa using a chemical vapor deposition process. The etch inhibiting film 308 is made of a material having a slower etching speed than the interlayer insulating film. For example, when the nitride film is used as the etching inhibiting film 308, the etching selectivity with respect to the interlayer insulating film of oxide film material may be about 1:20 to 30.

In this state, as illustrated in FIG. 3B, the first metal layer 303, the first dielectric layer 304, the second metal layer 305, the second dielectric layer 306, using a photolithography process and an etching process, may be used. By selectively patterning the third metal layer 307 and the etching suppression layer 308, the first electrode 303, the first dielectric layer 304, the second electrode 305, the second dielectric layer 306, and the third electrode ( A capacitor composed of 307 is completed. The patterned etch stop layer 308 is formed on the third electrode 307 of the capacitor.

Next, as shown in FIG. 3C, a second interlayer insulating film 309 is stacked on the entire surface of the substrate 301 including the etch inhibiting film 308. Like the first interlayer dielectric layer 302, the second interlayer dielectric layer 309 is formed of a TEOS-based oxide layer such as low pressure tetra ethyl ortho silicate (LP-TEOS), O ₃ -TEOS, d-TEOS, or a high density plasma chemical vapor phase. The material may be formed of any one of a Fluorine Silicate Glass (FSG), an Undoped Silicate Glass (USG), a SiH ₄ film, or a BPSG film deposited by using a high density plasma CVD.

In this state, a photoresist film is coated on the second interlayer insulating film 309, and then a photoresist pattern 311 is formed to expose the interlayer insulating film of the region where the contact hole 310 is to be formed by using a photolithography process. Subsequently, the contact hole 310 is formed by etching the interlayer insulating layer using the photoresist pattern as an etching mask. In this case, the contact hole 310 forming process may be divided into a first etching process and a second etching process, and the first and second etching processes use a dry etching process such as reactive ion etching. The exposed portions of the contact holes 310 are upper surfaces of the first, second, and third electrodes 303, 305, and 307.

On the other hand, the heights of the interlayer insulating films formed on the respective electrodes are different because of the step difference between the first, second and third electrodes 303, 305, 307. Therefore, when the interlayer insulating layer is etched, the etch inhibiting layer 308 formed on the first electrode 303 is first exposed before the second and third electrodes 305 and 307 are exposed. The process of exposing the etch stop layer 308 on the first electrode 303 is defined as a first etch process in a temporal concept.

In this state, the second etching process is performed. In this case, the etching is performed using an etching selectivity between the etching suppression layer 308 and the interlayer insulating layer, and the etching rate of the etching suppression layer 308 is significantly slower than the etching rate of the interlayer insulating layer. The first electrode 303 is prevented from being exposed until all the interlayer insulating films on the third electrodes 305 and 307 are etched. Through the second etching process, the first dielectric layer 304, the second dielectric layer 306, and the etching suppression layer 308 formed on the first, second, and third electrodes 303, 305, and 307, respectively, are exposed. The first dielectric layer 304, the second dielectric layer 306, and the etch suppression layer 308 may be formed of silicon nitride to uniformly secure the etching characteristics.

Then, as illustrated in FIG. 3E, the first dielectric layer 304, the second dielectric layer 306, and the etch inhibiting layer 308 are removed to remove the upper surfaces of the first, second, and third electrodes 303, 305, and 307. Exposing the contact hole 310 is completed. Subsequently, although not shown in the drawing, a predetermined metal layer is deposited on the second interlayer insulating film 309 to sufficiently fill the contact hole 310, and then the metal layer is planarized through a chemical mechanical polishing process, or the like, in the via hole. When the contact plug is formed, the manufacturing process of the semiconductor device according to the present invention is completed.

The method of manufacturing a semiconductor device according to the present invention has the following effects.                     

By forming an etching inhibiting film having a relatively slow etching speed than the interlayer insulating film on the uppermost electrode of the multilayer capacitor to a predetermined thickness, a plurality of electrodes formed with different steps may be simultaneously exposed in time without damage due to etching. As a result, the contact hole forming process can be simplified.

Claims (4)

Forming a first interlayer insulating film on the semiconductor substrate; Stacking a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, and a third metal layer on the first interlayer insulating layer; Forming an etch inhibiting film on the third metal layer; Selectively patterning the etch inhibiting layer to the first metal layer to form first, second and third electrodes; Stacking a second interlayer insulating film on the entire surface of the substrate including the etch inhibiting film; Forming an etch mask on the second interlayer insulating film to form contact holes exposing the first, second and third electrodes; Etching the second interlayer insulating layer using the etching mask to expose the first dielectric layer, the second dielectric layer, and an etch inhibiting layer; And removing the first dielectric layer, the second dielectric layer, and the etch inhibiting layer to complete the contact holes exposing the first, second, and third electrodes. The method of claim 1, wherein the etch inhibiting film is formed of a silicon nitride film. The method of manufacturing a semiconductor device according to claim 1, wherein the first and second dielectric films are formed of a silicon nitride film. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the etching inhibiting film is formed to a thickness of 200 to 400 kPa.

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