KR19990008511A - Test pattern pad structure and its formation method - Google Patents

Abstract

The present invention relates to a test pattern pad structure formed on a semiconductor substrate in a scribe line region and a method of forming the same. The test pattern pad of the present invention includes a first interlayer insulating layer formed on a semiconductor substrate having a scribe line region, and A polysilicon layer formed to define a sawing region on the interlayer insulating layer, a second interlayer insulating layer formed to cover the polysilicon layer on the first interlayer insulating layer, and a surface of the polysilicon layer on the second and first interlayer insulating layers A plurality of holes formed to expose the plurality of holes, respective plugs filled in the plurality of holes, a first metal layer formed to cover each plug on the second interlayer insulating layer, and a first metal layer on the second interlayer insulating layer. And a third interlayer dielectric layer formed so that the second interlayer dielectric layer is formed so as to be in contact with the first metal layer on a portion of the third interlayer dielectric layer. In the turn pad manufacturing method, after forming a first interlayer insulating layer covering a semiconductor substrate, forming a polysilicon layer on a predetermined portion on the first interlayer insulating layer, and covering the polysilicon layer on the first interlayer insulating layer. Forming a second interlayer dielectric layer, forming a plurality of holes exposing a polysilicon layer on a predetermined portion of the second interlayer dielectric layer and the first interlayer dielectric layer, and filling a plurality of holes with metal Forming two plugs, forming a first metal layer to cover the surface of the plug on the remaining second interlayer insulating layer, and forming a third interlayer insulating layer to expose the first metal layer on the second interlayer insulating layer. And forming a second metal layer in contact with the first metal layer on a portion of the third interlayer insulating layer.

Therefore, in the test pattern pad structure of the present invention and a method of forming the same, the plug is formed so that cracks generated by the stress generated at the interface between the first metal layer and the second interlayer insulating layer during the sawing process do not extend to various unit devices of the semiconductor chip region. This prevents the product from being damaged and improves reliability.

Description

Test pattern pad structure and its formation method

The present invention relates to a structure of a test pattern pad formed in a scribe line region for separating into individual semiconductor chips and a method of forming the same, in particular to each individual semiconductor chip (sawing And a method of forming a test pattern pad that can protect the semiconductor chip from cracks caused by damage to the interfaces of the layers upon separation.

At the edges of the semiconductor chip regions in which the element is formed, there is a portion in which no element, called a scribe line region, is formed.

The scribe line area is a sawing area for forming a semiconductor chip and then separating the semiconductor chip into individual semiconductor chips. Therefore, the scribe line region does not form a semiconductor chip as a region which disappears when sawing.

However, during the semiconductor chip process, a plurality of test patterns are formed for checking each unit process state in the scribe line region or for forming the same cell as the cell in the semiconductor chip region to test the operation state of the cell before the sawing.

These test patterns disappear or break with the scribe line area during the sawing process.

1 is a plan view of a conventional test pattern pad, FIG. 2 is a cross-sectional view of a conventional test pattern pad, and FIGS. 3A to 3C are manufacturing process diagrams of a conventional test pattern pad.

Hereinafter, a conventional test pattern pad structure and a method of forming the same will be described with reference to the accompanying drawings.

Conventional test pattern pads have a first interlayer insulating layer 102 and a first interlayer insulating layer 102 covering the semiconductor substrate 100 of the scribe line region as shown in FIGS. 1 and 2. A second interlayer insulating layer 104 formed on the first interlayer insulating layer 104, a first metal layer 106 formed on the second interlayer insulating layer 104, a planarization layer 108 covering both sides of the first metal layer 106, and The second metal layer 110 covers the first metal layer 106 and the planarization layer 108.

A method of forming a pad of a conventional test pattern having such a structure will be described in detail.

Referring to FIGS. 1 and 3A, a BPSG (Boro Phosphor Silicate Galss) is deposited on the semiconductor substrate 100 of the scribe line region 120 to form a first interlayer dielectric layer 102 and a second interlayer dielectric layer 104. Form sequentially.

Referring to FIG. 3B, a first metal layer 106 of aluminum patterned to define a sawing region using aluminum is formed in the second interlayer insulating layer 104.

Referring to FIG. 3C, a planarization layer 108 is formed by depositing TEOS (Tetra Ethyl Ortho Silicate) on the first metal layer 106, and then patterned to cover both sides of the first metal layer 106.

Subsequently, the second metal layer 110 is formed to cover the exposed first metal layer 106 and the planarization layer 108 to complete the test pattern pad formation.

Reference numeral ⓐ is the width of the cutting tool, it means the width to be sawed.

However, in the conventional test pattern pad forming method, cracks are generated due to stress generated at an interface between the first metal layer, which is aluminum, and the second interlayer insulating layer, which is BPSG.

Therefore, the generated crack affects various unit devices of the semiconductor chip region, resulting in a problem that the product is damaged.

Accordingly, it is an object of the present invention to provide a test pattern pad formation method capable of preventing cracks caused by stress of an interface between a metal layer and an interlayer insulating layer, which is a BPSG, from affecting various unit devices in a semiconductor chip region.

In order to achieve the above object, the test pattern pad of the present invention comprises a first interlayer insulating layer formed on a semiconductor substrate having a scribe line region, a polysilicon layer formed to define a sawing region on the first interlayer insulating layer, and A second interlayer insulating layer formed to cover the polysilicon layer on the interlayer insulating layer, a plurality of holes formed so that the surface of the polysilicon layer is exposed on the second and first interlayer insulating layers, and each plug filled in the plurality of holes And a first metal layer formed to cover the respective plugs on the second interlayer insulating layer, a third interlayer insulating layer formed to expose the first metal layer on the second interlayer insulating layer, and a portion of the third interlayer insulating layer. And a second metal layer formed in contact with the first metal layer.

In the method for manufacturing a test pattern pad having the above structure, after forming a first interlayer insulating layer covering a semiconductor substrate, a polysilicon layer is formed on a predetermined portion of the first interlayer insulating layer, and on the first interlayer insulating layer. Forming a second interlayer insulating layer to cover the polysilicon layer, forming a plurality of holes exposing the polysilicon layer to a predetermined portion of the second interlayer insulating layer and the first interlayer insulating layer, Forming a plurality of plugs by filling a hole with a metal; forming a first metal layer to cover the surface of the plug on the remaining second interlayer insulating layer; and exposing the first metal layer on the second interlayer insulating layer. And forming a third interlayer insulating layer, and forming a second metal layer in contact with the first metal layer on a portion of the third interlayer insulating layer.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

1 is a plan view of a conventional test pattern pad,

2 is a cross-sectional view of a conventional test pattern pad,

3A to 3C are manufacturing process diagrams of a conventional test pattern pad.

And Figure 4 is a plan view of the test pattern pad of the present invention,

5 is a cross-sectional view of the test pattern pad of the present invention;

6A to 6D are manufacturing process diagrams of the test pattern pad of the present invention.

Explanation of symbols for the main parts of the drawings

100, 200. Semiconductor substrates 102, 202. First interlayer insulating layer

104, 204. Second interlayer insulating layer 106, 206. First metal layer

108, 208. Planarization layer 110, 210. Second metal layer

120, 220.Scribine 130, 230.

212. Polysilicon layer 214-1. plug

4 is a plan view of the test pattern pad of the present invention, FIG. 5 is a cross-sectional view of the test pattern pad of the present invention, and FIGS. 6A to 6D are manufacturing process diagrams of the test pattern pad of the present invention.

4 and 5, in the test pattern pad of the present invention, a first interlayer insulating layer 201 is formed on a semiconductor substrate 200 having a scribe line region 220, and a first interlayer insulating layer 201 is formed. Polysilicon layer 212 is formed on the scribe line region of the (). A second interlayer insulating layer 202 is formed on the first interlayer insulating layer 202 so as to cover the polysilicon layer 212, and a third interlayer insulating layer 202 is formed on the second interlayer insulating layer 202. 204 is formed.

A plurality of holes 212 are formed in the second interlayer insulating layer 202 and the third interlayer insulating layer 204 so that the polysilicon layer 212 is exposed, and a plurality of holes 212 are filled with tungsten or the like. Two plugs 214-1. In addition, the first metal layer 206 is formed on the third interlayer insulating layer 204 to be in contact with the plurality of plugs 214-1.

A fourth interlayer insulating layer 208 is formed on the third interlayer insulating layer 204 to expose the first metal layer 206. A second metal layer 210 in contact with the first metal layer 206 is formed on a portion of the fourth interlayer insulating layer 208, and a planarization layer covering the second metal layer 210 on the fourth interlayer insulating layer 208. (Not shown in the figure) is formed.

The test pattern pad having the above-described structure forms a semiconductor chip in a semiconductor chip region (not shown), and then, saws each of the individual semiconductor chips by sawing with a cutting tool such as a diamond saw along the region ⓑ in the scribe line region. Separate.

At this time, a crack is generated by the stress between the third interlayer insulating layer 204 and the first metal layer 206.

The cracks generated between the third interlayer insulating layer 204 and the first metal layer 206 diffuse into a wide range, and the third interlayer insulating layer 204 and the first metal layer 206 in the plurality of holes 214. A plurality of plugs 214-1 formed of a medium different from) prevents cracks from spreading into the semiconductor chip region.

The method of forming the test pattern pad of the present invention having the structure as described above will be described in detail.

Referring to FIG. 6A, a BPSG (Boro Phosphor Silicate Galss) is deposited on the semiconductor substrate 200 of the scribe line region 220 to form a first interlayer insulating layer 201 having a predetermined thickness.

Subsequently, after forming the polysilicon layer 212 patterned to define the sawing region in the first interlayer insulating layer 201, the BPSG is applied to cover the polysilicon layer 212 on the first interlayer insulating layer 201. It deposits again and forms the 2nd interlayer insulation layer 202. FIG.

A third interlayer dielectric layer 204 is formed by depositing BPSG or the like on the second interlayer dielectric layer 202.

Referring to FIG. 6B, a mask pattern (not shown) is formed in a predetermined portion on the third interlayer insulating layer 204. Referring to FIG. The third and second interlayer insulating layers 204 and 202 are etched using the mask pattern as a mask to form a plurality of holes 214 exposing the polysilicon layer 212.

Next, the mask pattern is removed.

Here, the polysilicon layer 212 serves to limit the depth to be etched when the hole 214 is formed.

Referring to FIG. 6C, a plurality of plugs 214-1 are formed in the plurality of holes 214.

The plurality of plugs 214-1 are formed by depositing a metal such as tungsten on the third interlayer insulating layer 204 to fill the plurality of holes 214, and then etching back.

The first metal layer 206 is formed on the third interlayer insulating layer 204 to cover the plurality of plugs 214-1.

Referring to FIG. 6D, a fourth interlayer insulating layer 208 exposing the first metal layer 206 is formed on the third interlayer insulating layer 204.

The second metal layer 210 is formed and patterned to cover the exposed first metal layer 206 and the fourth interlayer insulating layer 208.

Subsequently, a planarization layer (not shown) covering the second metal layer 210 is formed on the fourth interlayer insulating layer 208 to complete the manufacture of the test pattern pads 206 and 210.

Subsequently, the plurality of plugs 214 and the plugs are cut by using a cutting tool and separated into individual semiconductor chips. At this time, the remaining plug 214 prevents cracks generated due to stress generated at the interface between the first metal layer 206 and the third interlayer insulating layer 204 to the semiconductor chip region.

Reference sign ⓑ means the width being sawed.

Therefore, in the test pattern pad structure of the present invention and a method of forming the same, the plug is formed so that cracks generated by the stress generated at the interface between the first metal layer and the second interlayer insulating layer during the sawing process do not extend to various unit devices of the semiconductor chip region. This prevents the product from being damaged and improves reliability.

Claims (3)

A first interlayer insulating layer formed on the semiconductor substrate having a scribe line region; A polysilicon layer formed on the first interlayer insulating layer to define a sawing region; A second interlayer insulating layer formed on the first interlayer insulating layer to cover the polysilicon layer; A plurality of holes formed to expose the surface of the polysilicon layer on the second and first interlayer insulating layers, each plug filled in the plurality of holes, A first metal layer formed on the second interlayer insulating layer to cover the respective plugs; A third interlayer insulating layer formed on the second interlayer insulating layer to expose a first metal layer; And a second metal layer formed to be in contact with the first metal layer on a portion of the third interlayer insulating layer. In the method for forming a test pattern pad in the scribe line region of a semiconductor substrate, Forming a polysilicon layer on a predetermined portion on the first interlayer insulating layer after forming the first interlayer insulating layer covering the semiconductor substrate; Forming a second interlayer dielectric layer on the first interlayer dielectric layer to cover the polysilicon layer; Forming a plurality of holes exposing the polysilicon layer to a predetermined portion of the second interlayer insulating layer and the first interlayer insulating layer; Filling a plurality of holes with metal to form a plurality of plugs; Forming a first metal layer on the remaining second interlayer insulating layer to cover the plug surface; Forming a third interlayer dielectric layer on the second interlayer dielectric layer to expose a first metal layer; And forming a second metal layer on a portion of the third interlayer insulating layer to be in contact with the first metal layer. The method according to claim 2, And a sawing step between the plug and the plug.