JP2005101181A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable the cutting process under the condition that damage such as chipping and crack is not caused within a semiconductor element at the time of forming a surface protection film and an interlayer insulating film on a dicing lane on the surface of the semiconductor wafer. <P>SOLUTION: The semiconductor device includes a dicing lane 2 for separating a semiconductor wafer 1 into individual semiconductor elements. A point pattern 6 in the equal interval is formed by providing a through hole on a surface protection film, metal wiring layer or an interlayer insulating film formed on the dicing lane 2. Accordingly, the cutting may be realized under the condition that a damage such as chipping and crack is not caused within the semiconductor element even when the surface protection film, metal wiring film, interlayer insulating film or the like is not formed on the dicing lane 2 of the semiconductor wafer 1. Moreover, it is also possible to provide the dicing method of the semiconductor wafer 1 which does not allow the occurrence of a fault in the assembling process because fragments caused by the peeling of the surface protection film, metal wiring layer and interlayer insulating film becomes small sufficiently. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a dicing method for dividing a semiconductor element formed on a semiconductor wafer, and in particular, a semiconductor device for a scribe line structure of a semiconductor wafer that can reduce chipping, film peeling, cracks, and the like, and the same It relates to a manufacturing method.

  Conventionally, as a method for dicing a semiconductor wafer, a method of crushing by rotating an annular dicing saw in which diamond or CBN particles are held by a bonding material at a high speed has been most commonly used. Processing with a dicing saw works to improve processing quality by improving and optimizing the diamond particle size, density, bond material and other dicing saw specifications, and rotational speed, feed speed, and cutting depth. I have been. However, since the processing by the dicing saw is crushing processing, phenomena such as chipping and peeling of the film formed on the dicing lane are inevitably generated.

  On the other hand, in order to realize further miniaturization of semiconductor elements, it is necessary to improve the exposure resolution. The NA (lens numerical aperture) of the exposure apparatus and the wavelength of the light source have been shortened. Resulting in a decrease. In other words, if the wafer surface has large irregularities, the targeted resolution cannot be obtained, and the wafer surface needs to be flattened. As a planarization method, a step of an SOG (Spin on Glass) film, an etch back method, CMP (Chemical Mechanical Polishing), or the like is used to eliminate a step of an oxide film or a metal wiring. This planarization is performed not only on the semiconductor element portion on the semiconductor wafer but also on the dicing lane. As a result, SOG, an interlayer insulating film, and the like are formed as a remaining film after planarization.

  Since the dicing is a crushing process using diamond or CBN particles as described above, the film may be peeled off when the remaining film is diced. This is particularly noticeable when the remaining film is fragile or the adhesion with the lower layer is weak.

  The peeling and cracking of the film not only has a risk of damaging the inside of the semiconductor element, but also the pieces of the peeled film cause problems such as a short circuit in the assembly process.

  For this reason, various countermeasures have conventionally been taken in dicing.

  For example, Patent Document 1 discloses that the surface protection film 106 on the bonding pad 105 of the semiconductor wafer 101 is selectively removed as shown in FIG. 9, and at the same time, the semiconductor element region is interposed between the dicing lane 102 and the semiconductor element region 103. A slit 107 that divides the surface protective film 106 covering the surface 103 and the surface protective film 106 remaining on the dicing lane 102 is formed, and dicing is performed along the dicing lane 102. According to this method, even if peeling 109 or crack 110 of the surface protective film 106 occurs due to damage during dicing, the surface protective film 106 covering the semiconductor element region 103 and the surface protective film 106 remaining on the dicing lane 102 are divided. Since there is a slit 107 to be damaged, damage does not reach the inside of the semiconductor element. Further, even when the silicon chipping 108 is large, it can be stopped by the slit portion 107 to some extent.

However, according to this method, damage to the inside of the semiconductor element can be avoided, but generation of fragments of the peeled surface protective film cannot be suppressed. The fragments of the surface protective film have a risk of causing problems in the assembly process. For example, such a problem occurs that a piece of the surface protective film adheres to a collet that adsorbs a chip during die picking, and a piece of the surface protective film sticks to the surface of a chip to be picked up next. Further, when the scattered pieces of the surface protective film adhere to the bonding pad, problems such as wire adhesion occur. In addition, when performing electrode bonding using a liquid conductor such as silver paste, if the scattered pieces of the surface protective film adhere between adjacent bonding pads, the liquid conductor travels through the pieces of the surface protective film. It leads to a short between adjacent pads.
Japanese Patent Laid-Open No. 3-129855 (pages 1 to 4 and FIG. 2)

  However, in Patent Document 1, damage to the inside of the semiconductor element can be avoided as described above, but generation of fragments of the peeled surface protective film cannot be suppressed. The fragments of the surface protective film have a risk of causing problems in the assembling process and must be avoided.

  Accordingly, an object of the present invention is to provide a surface protective film or an interlayer insulating film formed on a dicing lane on the surface of a semiconductor wafer, particularly when the surface protective film or the interlayer insulating film is fragile or has a weak adhesion to the lower layer. Even in such a case, a semiconductor wafer dicing method that enables cutting without damage caused by chipping or cracks inside the semiconductor element is provided, and further, cutting that does not cause fragmentation due to peeling of the surface protective film or interlayer insulating film is provided. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same.

  In order to solve the above problems, a semiconductor device according to claim 1 of the present invention is a semiconductor device having a dicing lane for separating a semiconductor wafer into individual semiconductor elements, and the surface protection formed on the dicing lane. By forming through holes in the film, the metal wiring layer, or the interlayer insulating film, dot patterns with equal intervals were formed.

  According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the arrangement interval of the dot patterns is narrower than the dicing width when the semiconductor wafer is separated into semiconductor elements.

  According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the dot pattern is disposed in a region wider than a processing width when dividing the semiconductor element.

  5. The semiconductor device according to claim 4, wherein the semiconductor device has a dicing lane for separating a semiconductor wafer into individual semiconductor elements, and penetrates a surface protective film, a metal wiring layer, or an interlayer insulating film formed on the dicing lane. A hole pattern was provided, and a dot pattern with equal intervals was formed by embedding metal in the through hole.

  According to a fifth aspect of the present invention, in the semiconductor device of the fourth aspect, the arrangement interval of the dot patterns is narrower than the dicing width when the semiconductor wafer is separated into semiconductor elements.

  A semiconductor device according to a sixth aspect is the semiconductor device according to the fourth aspect, wherein the dot pattern is disposed in a region wider than a processing width when dividing the semiconductor element.

  The semiconductor device according to claim 7 is a semiconductor device having a dicing lane that separates a semiconductor wafer into individual semiconductor elements, and is formed by etching a metal wiring layer formed on the dicing lane so as to form an equidistant point pattern. And a surface protective film was coated thereon.

  According to an eighth aspect of the present invention, in the semiconductor device according to the seventh aspect, the arrangement interval of the dot patterns is narrower than the dicing width when the semiconductor wafer is separated into semiconductor elements.

  A semiconductor device according to a ninth aspect is the semiconductor device according to the seventh aspect, wherein the dot pattern is arranged in a region wider than a processing width when dividing the semiconductor element.

  According to the ninth aspect of the present invention, since the point pattern is arranged in a region wider than the processing width when dividing the semiconductor element, the region in which the point pattern is arranged needs to occupy from end to end of the dicing lane. And can be easily formed.

  The method for manufacturing a semiconductor device according to claim 10, wherein an integrated circuit is formed on a semiconductor wafer, and simultaneously, a plurality of dot patterns including through holes are formed in a chip division processing region of a surface of the semiconductor wafer on which a semiconductor element is formed. And a step of separating the semiconductor wafer along a chip division processing region.

  According to the semiconductor device of the first aspect of the present invention, since the surface protection film, the metal wiring layer or the interlayer insulating film formed on the dicing lane is provided with the through holes, the equally spaced point patterns are formed. Even if a surface protective film, a metal wiring layer, an interlayer insulating film, or the like on the dicing lane of the wafer substrate is formed, cutting without chipping or crack damage inside the semiconductor element is enabled. Furthermore, a semiconductor wafer dicing method can be provided in which the fragmentation caused by the peeling of the surface protective film, the metal wiring layer, and the interlayer insulating film is sufficiently small and does not cause problems in the assembly process.

  That is, when the semiconductor wafer is divided into semiconductor elements by dicing, peeling or cracking occurs in the surface protective film, metal wiring layer, or interlayer insulating film formed on the dicing lane on the surface of the semiconductor wafer. The through hole formed in the metal wiring layer and interlayer insulating film suppresses the progress of peeling and cracking, and it is possible to make it difficult for the surface protection film, metal wiring layer and interlayer insulating film to peel and crack damage to propagate to semiconductor elements. It is said.

  In claim 2, since the arrangement interval of the dot pattern is narrower than the dicing width when the semiconductor wafer is separated into semiconductor elements, the surface protection film and the metal wiring layer can be formed by sufficiently reducing the arrangement interval of the through holes. The progress of the peeling of the interlayer insulating film can be suppressed at a small stage. For this reason, the fragment due to peeling that occurs during dicing is sufficiently reduced, and the risk of occurrence of problems in the assembly process can be reduced.

  According to the third aspect of the present invention, since the point pattern is arranged in a region wider than the processing width when dividing the semiconductor element, it is necessary that the region where the point pattern is arranged occupies the dicing lane from end to end. And can be easily formed.

  According to the semiconductor device of the fourth aspect of the present invention, through holes are provided in the surface protective film, metal wiring layer or interlayer insulating film formed on the dicing lane, and the metal is embedded in the through holes so as to be equally spaced. Since the dot pattern is formed, even if a surface protection film, metal wiring layer, interlayer insulating film, etc. on the dicing lane of the semiconductor wafer substrate are formed, cutting without chipping or crack damage inside the semiconductor element is enabled. . Furthermore, a semiconductor wafer dicing method can be provided in which the fragmentation caused by the peeling of the surface protective film, the metal wiring layer, and the interlayer insulating film is sufficiently small and does not cause problems in the assembly process.

  In other words, the surface protection film, the metal wiring layer, and the interlayer insulating film are formed with through-holes embedded with metals such as tungsten, aluminum, and copper, so that the adhesion of the film is improved and the semiconductor wafer is divided into semiconductor elements by dicing. In addition, it is possible to suppress the occurrence of peeling and cracking in the surface protective film, metal wiring layer, and interlayer insulating film formed on the dicing lane on the surface of the semiconductor wafer.

  According to the fifth aspect of the present invention, since the dot pattern arrangement interval is narrower than the dicing width when the semiconductor wafer is separated into semiconductor elements, the effect of improving the adhesion of the film is sufficiently small. As a result, the surface protection film, the metal wiring layer, and the interlayer insulating film can be prevented from peeling off at a small stage. For this reason, the fragment due to peeling that occurs during dicing is sufficiently reduced, and the risk of occurrence of problems in the assembly process can be reduced.

  According to the sixth aspect of the present invention, since the point pattern is arranged in an area wider than the processing width when dividing the semiconductor element, the area where the point pattern is arranged needs to occupy the end of the dicing lane. And can be easily formed.

  According to the semiconductor device of the seventh aspect of the present invention, the metal wiring layer formed on the dicing lane is etched to form the equidistant point pattern, and the surface protective film is coated thereon. Even if a metal wiring layer on the dicing lane of the wafer substrate is formed, cutting without chipping or crack damage inside the semiconductor element is enabled. Furthermore, a semiconductor wafer dicing method can be provided in which the fragment due to the peeling of the metal wiring layer is sufficiently small and does not cause problems in the assembly process.

  That is, the dot pattern of the metal wiring layer is formed on the dicing lane, and the interlayer adhesion is improved by the anchor effect due to the step by coating the surface protective film on the dot pattern. Further, although the surface protective film follows the surface by the step of the point pattern, the surface protective film can be made uneven. As a result, when the semiconductor wafer is divided into semiconductor elements by dicing, it is possible to suppress the occurrence of peeling and cracking in the surface protective film formed on the dicing lane on the surface of the semiconductor wafer.

  According to the eighth aspect of the present invention, since the arrangement interval of the dot patterns is narrower than the dicing width when the semiconductor wafer is separated into the semiconductor elements, the effect of increasing the rigidity of the surface protective film is as follows. By making the arrangement interval sufficiently small, the distance is further increased, and peeling of the metal wiring layer can be suppressed at a small stage. For this reason, the fragment due to peeling that occurs during dicing is sufficiently reduced, and the risk of occurrence of problems in the assembly process can be reduced.

  According to the semiconductor device manufacturing method of the present invention, the integrated circuit is formed on the semiconductor wafer, and at the same time, a plurality of through holes are formed in the chip division processing region on the surface of the semiconductor wafer where the semiconductor elements are formed. Since it includes a step of forming a point pattern and a step of separating the semiconductor wafer along the chip division processing region, a surface protective film, a metal wiring layer, an interlayer insulating film, etc. are formed on the dicing lane of the semiconductor wafer substrate. However, cutting without chipping or crack damage inside the semiconductor element is enabled. Furthermore, a semiconductor wafer dicing method can be provided in which the fragmentation caused by the peeling of the surface protective film, the metal wiring layer, and the interlayer insulating film is sufficiently small and does not cause problems in the assembly process.

  That is, when the semiconductor wafer is divided into semiconductor elements by dicing, peeling or cracking occurs in the surface protective film, metal wiring layer, or interlayer insulating film formed on the dicing lane on the surface of the semiconductor wafer. The through hole formed in the metal wiring layer and interlayer insulating film suppresses the progress of peeling and cracking, and it is possible to make it difficult for the surface protection film, metal wiring layer and interlayer insulating film to peel and crack damage to propagate to semiconductor elements. It is said.

  A first embodiment of the present invention will be described with reference to FIGS. First, the outline will be described.

  FIG. 1A is a plan view showing a dicing lane and its periphery of a semiconductor wafer according to an embodiment of the present invention, and FIG. 1B shows a plan view after dicing. Moreover, FIG.1 (c) is AA sectional drawing shown to Fig.1 (a), FIG.1 (d) is CC sectional drawing shown in FIG.1 (b). Further, FIG. 1 (e) is an enlarged view of a portion B shown in FIG. 1 (a), and FIG. 1 (f) is an enlarged view of a portion D shown in FIG. 1 (b). In the figure, 1 is a semiconductor wafer, 2 is a dicing lane, 2a is the center of a dicing line, 3 is a semiconductor element region, 4 is an example of a dicing cutting width, 5 is a bonding pad, and 6 is a dot pattern.

  The semiconductor wafer 1 has a dicing lane 2. The dicing lane 2 is a virtual line for cutting. An active element such as a transistor, a passive element such as a resistance element, a wiring, a bonding pad 5 and the like are formed on the semiconductor element forming surface on the semiconductor wafer 1, and an interlayer insulating film or the like is also formed on the dicing lane 2. Residual films such as metal wiring layers and surface protective films may be formed.

  A feature of the embodiment of the present invention is that a dot pattern 6 is formed on the dicing lane 2, and the dot pattern is formed by a surface protection film, a metal wiring layer, a through hole of an interlayer insulating film, or a metal Or by forming a dot pattern 6 with a metal wiring layer and covering a surface protective film thereon (sixth embodiment). . When the dicing lane in which the dot pattern 6 is formed is diced, silicon chipping generated during dicing, surface protection film, metal wiring layer, interlayer insulating film peeling, cracks, and the like are suppressed by the dot pattern 6, and the semiconductor element Damage to area 3 can be prevented. In addition, since the surface protection film, the metal wiring layer, and the interlayer insulating film are peeled off sufficiently, the problems in the assembly process can be prevented.

  Next, the arrangement of the point patterns will be described with reference to the drawings.

  FIGS. 1E and 2A to 2D show dot pattern arrangements on a dicing lane of a semiconductor wafer according to an embodiment of the present invention, which are first to fifth examples, respectively. That is, FIG. 1 (e) shows the first embodiment of the dot pattern arrangement, FIG. 2 (a) shows the second embodiment, FIG. 2 (b) shows the third embodiment, and FIG. ) Is the fourth embodiment, and FIG. 2D is the fifth embodiment. In the figure, 2 is a dicing lane, 2a is the center of a dicing line, 3 is a semiconductor element region, and 6 is a dot pattern.

  In the first embodiment of the point pattern arrangement, the point patterns are arranged at equal intervals in the grid. The interval between each point pattern needs to be sufficiently small, needs to be narrower than at least the dicing width, and is selected from the range of 0.5 μm to 20 μm. Further, it is not always necessary to arrange them at regular intervals. In addition, the size of the area where the dot pattern is arranged needs to occupy a wide area at least outside the dicing width. It is not always necessary to occupy the dicing lane from end to end.

  The second embodiment of the point pattern arrangement is an example in which no point pattern is arranged in the vicinity of the center of the dicing lane that is always cut and removed during the actual dicing process. If sufficient consideration is given to variation in the processing width of the dicing apparatus, processing position deviation, and the like, and the region in which the point pattern is desired to be arranged is determined, there is no need to form a point pattern near the center.

  The third embodiment of the point pattern arrangement is an example in which the interval between the point patterns is changed between the cutting direction and the dicing lane width direction.

  In the fourth and fifth embodiments of the point pattern arrangement, the point patterns are not arranged in a vertical and horizontal line like the grid pattern as in the first embodiment, but are arranged alternately or in an oblique direction. It is. Even in such an arrangement, the effect of the point pattern targeted by the present invention can be obtained without change.

  Next, a method for forming the above-described point pattern will be described with reference to the cross-sectional view of FIG.

  3A to 3B are process diagrams using cross-sectional views of the dicing lane of the semiconductor wafer according to the first embodiment of the present invention. In FIGS. 3A to 3B, reference numeral 6 denotes a dot pattern. 7 is an interlayer insulating film between the polysilicon and the first metal, 8 is an interlayer insulating film between the first metal and the second metal, 9 is an interlayer insulating film between the second metal and the third metal, A surface protective film is shown.

  Here, the constituent materials of the interlayer insulating films 7 to 9 and the surface protective film include, for example, a nitride film, an oxide film, a high dielectric film, a low dielectric film, an organic film, a metal film, and the like. 10 nm to several μm.

  As shown in FIG. 3A, an interlayer insulating film 8, an interlayer insulating film 9, and a surface protective film 10 are formed in this order from the interlayer insulating film 7 on the dicing lane. As a forming method, a CVD method, a PVD method, a coating method, or the like is used.

  As shown in FIG. 3B, a through-hole that becomes a point pattern 6 is formed in the surface protective film 10 formed in the uppermost layer by using a dry etching method or a wet etching method.

  All the above processes are performed simultaneously with the manufacturing process of the semiconductor element region.

  A second embodiment of the present invention will be described with reference to FIG.

  Similar to the first embodiment, a feature of the embodiment of the present invention is that a point pattern 6 is formed on the dicing lane 2, and the point pattern 6 includes a surface protective film, a metal wiring layer, and an interlayer insulating film. The through-hole is formed.

  4A to 4J are process diagrams using cross-sectional views of the dicing lane of the semiconductor wafer according to the second embodiment of the present invention. In FIGS. 4A to 4J, 6 is a dot pattern, 7 is an interlayer insulating film, 8 is an interlayer insulating film, 9 is an interlayer insulating film, and 10 is a surface protective film.

  As shown in FIG. 4A, an interlayer insulating film 7 is formed on the dicing lane.

  Next, as shown in FIG. 4B, only the dot pattern portion is selectively etched in the formed interlayer insulating film 7 to form through holes of the dot pattern 6.

  Next, as shown in FIG. 4C, the interlayer insulating film 8 is formed, and then the unevenness of the interlayer insulating film 8 formed by the step of the point pattern 6 formed by the interlayer insulating film 7 is eliminated. As shown in (d), planarization is performed by a process such as high-temperature reflow.

  Next, as shown in FIG. 4E, only a portion of the point pattern 6 is selectively etched in the interlayer insulating film 8 to form a through hole of the point pattern 6. At this time, the dot pattern of the interlayer insulating film 8 is not necessarily formed at the same position as the dot pattern 6 of the interlayer insulating film 7 as shown in the drawing.

  Next, similarly to the interlayer insulating film 8, the interlayer insulating film 9 is formed with a film in FIG. 4 (f), planarized in FIG. 4 (g), and through-holes with a dot pattern 6 are formed in FIG. 4 (h). Do.

  Next, as shown in FIG. 4I, a surface protective film 10 is formed.

  Finally, as shown in FIG. 4 (j), a through hole of the point pattern 6 is formed in the surface protective film 10.

  As another embodiment, it is good also as completion by FIG.4 (i).

  Further, all of the above processes are performed simultaneously with the manufacturing process of the semiconductor element region.

  A third embodiment of the present invention will be described with reference to FIG.

  Similar to the first embodiment, a feature of the embodiment of the present invention is that a point pattern 6 is formed on the dicing lane 2, and the point pattern 6 includes a surface protective film, a metal wiring layer, and an interlayer insulating film. The through-hole is formed.

  FIGS. 5A to 5J are process diagrams using cross-sectional views of a dicing lane of a semiconductor wafer according to a third embodiment of the present invention. In FIGS. 5A to 5J, 6 is a dot pattern, 7 is an interlayer insulating film, 8 is an interlayer insulating film, 9 is an interlayer insulating film, and 10 is a surface protective film.

  As shown in FIG. 5A, an interlayer insulating film 7 is formed on the dicing lane.

  Next, as shown in FIG. 5B, only the dot pattern portion is selectively etched in the formed interlayer insulating film 7 to form through holes of the dot pattern 6.

  Next, as shown in FIG. 5C, the interlayer insulating film 8 is formed, and then the unevenness of the interlayer insulating film 8 formed by the step difference of the point pattern formed by the interlayer insulating film 7 is eliminated. As shown in d), planarization is performed by a process such as high-temperature reflow.

  Next, as shown in FIG. 5E, only the dot pattern portion is selectively etched in the interlayer insulating film 8 to form through holes of the dot pattern 6. At this time, the dot pattern of the interlayer insulating film 8 is formed so as to be positioned between the dot patterns 6 of the interlayer insulating film 7 so as not to overlap the dot pattern 6 of the interlayer insulating film 7 as shown in the figure.

  Next, as with the interlayer insulating film 8, the interlayer insulating film 9 is formed with a film in FIG. 5 (f), planarized in FIG. 5 (g), and formed with a through hole for the point pattern 6 in FIG. 5 (h). Do. Here, the dot pattern 6 of the interlayer insulating film 9 is formed so as to be positioned between the dot patterns 6 of the interlayer insulating film 8 so as not to overlap the dot pattern 6 of the interlayer insulating film 8 as shown in the figure.

  Next, a surface protective film 10 is formed as shown in FIG.

  Finally, as shown in FIG. 5 (j), a through hole of the point pattern 6 is formed in the surface protective film 10. Also at this time, the point pattern 6 of the surface protective film 10 is formed so as to be positioned between the point patterns 6 of the interlayer insulating film 9 so as not to overlap the dot pattern 6 of the interlayer insulating film 9 as shown in the figure.

  In another embodiment, the process may be completed up to FIG.

  Further, all of the above processes are performed simultaneously with the manufacturing process of the semiconductor element region.

  In the present embodiment, unlike the second embodiment, the dot patterns located above and below are alternately formed so as not to overlap each other at the planar position. Therefore, due to the anchor effect between the upper and lower films, adhesion and rigidity are improved, and film peeling and cracking during dicing are less likely to occur.

  A fourth embodiment of the present invention will be described with reference to FIG.

  Similar to the first embodiment, a feature of the embodiment of the present invention is that a dot pattern 6 is formed on the dicing lane 2. The point pattern 6 is formed by a surface protection film, a metal wiring layer, and a through hole of an interlayer insulating film, and further formed by a through hole in which metal is embedded.

  FIGS. 6A to 6P are process diagrams using sectional views of a dicing lane of a semiconductor wafer according to a fourth embodiment of the present invention. In FIGS. 6A to 6P, 6 is a dot pattern, 7 is an interlayer insulating film, 8 is an interlayer insulating film, 9 is an interlayer insulating film, 10 is a surface protection film, 11 is a contact plug for electrically connecting polysilicon and the first metal, and 12 is a first metal and a second metal. A via plug 13 connects between the second metal and the third metal.

  Here, the constituent materials of the interlayer insulating films 7 to 9 and the surface protective film include, for example, a nitride film, an oxide film, a high dielectric film, a low dielectric film, an organic film, a metal film, and the like. 10 nm to several μm. The constituent material of the contact plug 11 and the via plugs 12 and 13 includes polysilicon, tungsten, aluminum, copper and the like.

  As shown in FIG. 6A, an interlayer insulating film 7 is formed on the dicing lane.

  Next, as shown in FIG. 6B, only the dot pattern portion is selectively etched in the formed interlayer insulating film 7 to form through holes of the dot pattern 6.

  Next, as shown in FIG. 6C, a thin film of the constituent material of the contact plug 11 is formed using a CVD method, a PVD method, or a plating method, and as shown in FIG. Then, the interlayer insulating film 7 is exposed to the surface, and at the same time, the surface step is flattened. Thereby, a point pattern 6 in which metal is embedded is formed.

  Next, as shown in FIG. 6 (e), an interlayer insulating film 8 is formed and the surface unevenness of the interlayer insulating film 8 is eliminated. As shown in FIG. Flattening is performed by processing such as reflow.

  Next, as shown in FIG. 6G, only the dot pattern portion is selectively etched in the interlayer insulating film 8 to form through holes in the dot pattern 6. At this time, the dot pattern 6 of the interlayer insulating film 8 is not necessarily formed at the same position as the dot pattern 6 of the interlayer insulating film 7 as shown in the drawing.

  Next, as with the contact plug 11, the via plug 12 is subjected to film formation in FIG. 6 (h) and planarization in FIG. 6 (i).

  Next, as shown in FIG. 6 (j), an interlayer insulating film 9 is formed, and as shown in FIG. 6 (k), planarization is performed by a process such as an etch back method, a CMP method, high temperature reflow, etc. In (l), the through hole of the point pattern 6 is formed in the interlayer insulating film 9.

  Next, as with the contact plug 11 and the via plug 12, the via plug 13 is subjected to film formation in FIG. 6 (m) and planarization processing in FIG. 6 (n).

  Next, as shown in FIG. 6 (o), a surface protective film 10 is formed.

  Finally, as shown in FIG. 6 (p), a through hole having a dot pattern is formed in the surface protective film 10.

  As another embodiment, the process may be completed up to FIG.

  Further, all of the above processes are performed simultaneously with the manufacturing process of the semiconductor element region.

  A fifth embodiment of the present invention will be described with reference to FIG.

  Similar to the first embodiment, a feature of the embodiment of the present invention is that a dot pattern 6 is formed on the dicing lane 2. The point pattern 6 is formed by a surface protection film, a metal wiring layer, and a through hole of an interlayer insulating film, and further formed by a through hole in which metal is embedded.

  7A to 7B are process diagrams using cross-sectional views of a dicing lane of a semiconductor wafer according to a fifth embodiment of the present invention. In FIGS. 7A to 7B, 6 is a dot pattern, 7 is an interlayer insulating film, 8 is an interlayer insulating film, 9 is an interlayer insulating film, 10 is a surface protective film, 11 is a contact plug, 12 is a via plug, and 13 is a via plug.

  The fifth embodiment is characterized in that the same formation method as that of the fourth embodiment is used, and the positions of the point patterns 6 are staggered so as not to overlap each other in a planar position in a layer in contact with the top and bottom. Yes. Thereby, due to the anchor effect between the upper and lower films, adhesion and rigidity are improved, and film peeling and cracking during dicing are less likely to occur.

  A sixth embodiment of the present invention will be described with reference to FIG.

  Similar to the first embodiment, a feature of the embodiment of the present invention is that a dot pattern 6 is formed on the dicing lane 2. The point pattern 6 is formed by forming a through hole in the metal wiring layer and covering the surface protective film thereon.

  8A to 8C are process diagrams using cross-sectional views of a dicing lane of a semiconductor wafer according to a sixth embodiment of the present invention. In FIGS. 8A to 8C, 6 is a dot pattern, 7 is an interlayer insulating film, 8 is an interlayer insulating film, 9 is an interlayer insulating film, 10 is a surface protective film, and 14 is a metal wiring layer (third metal in this embodiment).

  Here, the constituent materials of the interlayer insulating films 7 to 9 and the surface protective film include, for example, a nitride film, an oxide film, a high dielectric film, a low dielectric film, an organic film, a metal film, and the like. 10 nm to several μm. Examples of the constituent material of the metal wiring layer 14 include aluminum and copper.

  As shown in FIG. 8A, an interlayer insulating film 8, an interlayer insulating film 9, and a metal film are formed in order from the interlayer insulating film 7 on the dicing lane. As a forming method, a CVD method, a PVD method, a coating method, a plating method, or the like is used.

  As shown in FIG. 8B, the dot pattern is transferred and developed on a photoresist using a mask on the formed metal film, and a portion that becomes the point pattern 6 is left using a dry etching method or a wet etching method. The metal film other than the point pattern portion is removed on the dicing lane.

  Finally, as shown in FIG. 8C, the surface protective film 10 is formed.

  All the above processes are performed simultaneously with the manufacturing process of the semiconductor element region.

  The semiconductor device and the manufacturing method thereof according to the present invention can reduce film peeling and cracks sufficiently in dicing even when an interlayer insulating film, a metal wiring film, a surface protective film, or the like is formed on the dicing lane. It can be applied as a method for manufacturing a high-quality semiconductor device. In particular, it is useful as a design and manufacturing method of a semiconductor wafer when the film on the dicing lane is fragile or the adhesion is weak. In addition, it can be expected that the dicing lane can be reduced by reducing the cutting width and the number of semiconductor elements collected on the semiconductor wafer can be increased.

(A) is a plan view showing a dicing lane and its periphery of a semiconductor wafer according to an embodiment of the present invention, (b) is a plan view after dicing, (c) is a cross-sectional view taken along line AA shown in (a), (d) ) Is a cross-sectional view taken along the line C-C shown in FIG. 5B, FIG. 5E is an enlarged view of a portion B shown in FIG. (A)-(d) is a top view which shows the Example of the point pattern arrangement | positioning to the dicing lane of the semiconductor wafer of embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor wafer concerning the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor wafer concerning the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor wafer concerning the 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor wafer concerning the 4th Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor wafer concerning the 5th Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor wafer concerning the 6th Embodiment of this invention. (A) is a top view of the dicing lane of the conventional semiconductor wafer, (b) is a top view which shows the state after the dicing.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,101 Semiconductor wafer 2,102 Dicing lane 2a, 102a Center of dicing line 3,103 Semiconductor device area 4,104 Dicing cutting width example 5,105 Bonding pad 6 Point pattern 7 Interlayer insulating film (polysilicon and first metal while)
8 Interlayer insulation film (between first metal and second metal)
9 Interlayer insulation film (between second metal and third metal)
10, 106 Surface protective film 11 Contact plug (between polysilicon and first metal)
12 Via plug (between first metal and second metal)
13 Via plug (between second metal and third metal)
14 Metal wiring layer (third metal)
107 slit 108 chipping of silicon 109 film peeling of surface protective film and interlayer insulating film 110 crack of surface protective film and interlayer insulating film (raised)

Claims (10)

  A semiconductor device having a dicing lane for separating a semiconductor wafer into individual semiconductor elements, and by providing through holes in a surface protective film, a metal wiring layer, or an interlayer insulating film formed on the dicing lane, the points are equally spaced A semiconductor device, wherein a pattern is formed.   The semiconductor device according to claim 1, wherein the arrangement interval of the point patterns is narrower than a dicing width when the semiconductor wafer is separated into semiconductor elements.   The semiconductor device according to claim 1, wherein the dot pattern is arranged in a region wider than a processing width when dividing the semiconductor element.   A semiconductor device having a dicing lane for separating a semiconductor wafer into individual semiconductor elements, wherein a through hole is provided in a surface protection film, a metal wiring layer or an interlayer insulating film formed on the dicing lane, and the through hole is provided in the through hole. A semiconductor device characterized in that dot patterns with equal intervals are formed by embedding metal.   The semiconductor device according to claim 4, wherein the arrangement interval of the point patterns is narrower than a dicing width when the semiconductor wafer is separated into semiconductor elements.   The semiconductor device according to claim 4, wherein the point pattern is arranged in a region wider than a processing width when dividing the semiconductor element.   A semiconductor device having a dicing lane for separating a semiconductor wafer into individual semiconductor elements, and by forming an equidistant point pattern by etching a metal wiring layer formed on the dicing lane, surface protection is performed thereon A semiconductor device characterized by coating a film.   The semiconductor device according to claim 7, wherein the arrangement interval of the point patterns is narrower than a dicing width when the semiconductor wafer is separated into semiconductor elements.   The semiconductor device according to claim 7, wherein the dot pattern is disposed in a region wider than a processing width when dividing the semiconductor element.   Forming an integrated circuit on a semiconductor wafer and simultaneously forming a plurality of dot patterns made of through holes in a chip division processing area of the surface of the semiconductor wafer on which the semiconductor elements are formed; and dividing the semiconductor wafer into a chip division processing area And a step of separating along the semiconductor device.

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