JP2008066716A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent dishing in a CMP process, and to prevent chipping failure by reducing clogging of a dicing blade in separating a semiconductor substrate (wafer). <P>SOLUTION: The ratio per unit area of a first dummy pattern 7 disposed in a cutting region 5 of a scribe region 4 is lower than that per unit area of a second dummy pattern 8 disposed in a non-cutting region 6. Also, the ratio per unit area of a region including a region contacting at least a side of a dicing blade 19 in the first dummy pattern 7 and adjacent to the non-cutting region 6 is lower than another region in the first dummy pattern 7, or the ratio per unit area of a region adjacent to a circuit region 2 in the second dummy pattern 8 is lower than another region in the second dummy pattern 8. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a multilayer wiring structure.

  In general, when forming each wiring layer in a semiconductor device having a multilayer wiring structure, a method (damascene method) in which a metal film is embedded in a groove formed in an interlayer insulating film for each wiring layer is employed. The metal film deposited on the entire surface of the semiconductor substrate is left only inside the groove by, for example, a chemical mechanical polishing (CMP) method, and the unnecessary metal film is removed. At this time, in the region where the wiring pattern formed in the interlayer insulating film is sparse, the film thickness of the wiring pattern becomes smaller due to the difference in polishing rate compared to the region where the wiring pattern is dense. In order to prevent this variation in film thickness, a technique is adopted in which pseudo wiring patterns are arranged as dummy patterns in regions where wiring patterns are sparse. As a result, pattern corner collapse (dishing) that occurs in the CMP process can be prevented.

  For example, Patent Document 1 below describes a semiconductor device in which uniform dummy patterns are provided in a scribe region and a circuit region of a semiconductor substrate in order to prevent dishing in a CMP process.

  FIG. 33A and FIG. 33B show a planar configuration of a scribe region, which is a cutting region when a semiconductor wafer in a semiconductor device according to a conventional example is divided into chips, and FIG. The cross-sectional structure in the XXXIIIb-XXXIIIb line | wire of a) is shown.

  As shown in FIGS. 33 (a) and 33 (b), a plurality of circuit regions 2 in which functional elements (not shown) are formed are formed on the main surface of the semiconductor substrate 1 at intervals. A seal ring 3 made of a conductive material is formed around each circuit region 2. A scribe region 4 is formed between the circuit regions 2 as a cutting region when the circuit regions 2 are separated.

On the main surface of the semiconductor substrate 1, first interlayer insulating films 11 and second interlayer insulating films 12 are alternately stacked, and the circuit region 2 in the first interlayer insulating film 11 has a conductive property. A wiring (not shown) made of a material is formed, and a via (not shown) made of a conductive material is formed in the second interlayer insulating film 12. On the other hand, in the scribe region 4 in the first interlayer insulating film 11, a dummy pattern 107, which is an isolated pattern (island pattern) made of a conductive material and arranged uniformly, is formed. In this way, dishing in the CMP process is prevented by the dummy pattern 107 that is evenly arranged in the scribe region 4 in the semiconductor substrate 1.
JP 2004-235357 A JP 2006-41244 A JP 2004-153015 A

  However, in the conventional semiconductor device, when the scribe region 4 is cut by the dicing blade, the dicing blade cuts the conductive material constituting the dummy pattern 107. For this reason, the blade of the dicing blade is clogged by the conductive material, and there is a problem that the cutting ability of the dicing blade is lowered and chipping (chip) is likely to occur in the obtained semiconductor chip.

  On the other hand, when the dummy pattern 107 is not disposed in the scribe region 4, there is a problem that dishing occurs in the CMP process described above.

  The present invention solves the above-described conventional problems and reduces clogging of a dicing blade when a semiconductor substrate (wafer) is singulated while preventing dishing in a CMP process, thereby preventing chipping failure. For the purpose.

  In order to achieve the above object, the present invention provides a semiconductor device in which the occupancy rate of the dummy pattern in the cut region in the scribe region is smaller than the occupancy rate of the dummy pattern in the non-cut region located on both sides of the cut region, and A region having a smaller occupation ratio is provided on the non-cutting region side of the cutting region, or a region having a smaller occupation ratio is provided on the circuit region side of the non-cutting region.

  Specifically, a semiconductor device according to the present invention includes a circuit region having a functional element formed on a semiconductor substrate, and a region located between the circuit region and another circuit region formed at an interval from the circuit region. A scribe region comprising a cut region and a non-cut region provided on both sides of the cut region, a first interlayer insulating film formed on the scribe region in the semiconductor substrate, and a first interlayer insulation A first dummy pattern made of a conductive material formed in a cut region in the film, and a second dummy pattern made of a conductive material formed in a non-cut region in the first interlayer insulating film, The occupancy rate per unit area of the first dummy pattern is smaller than the occupancy rate per unit area of the second dummy pattern in the non-cut region.

  According to the semiconductor device of the present invention, the occupation rate per unit area of the first dummy pattern in the cut region is smaller than the occupation rate per unit area of the second dummy pattern in the non-cut region. The integrity of the cut region and the non-cut region in the film as a laminated structure is lowered, and the mechanical strength of the cut region of the scribe region is smaller than the strength of the non-cut region. Thereby, it is possible to prevent damage that occurs in the cut area when the dicing blade separates into the non-cut area. In addition, since the occupation ratio of the first dummy pattern is smaller than the occupation ratio of the second dummy pattern, the cutting amount of the conductive material constituting the first dummy pattern cut by the dicing blade is reduced. As a result, since the clogging of the dicing blade is less likely to occur, the occurrence of cracks in the substrate due to the clogging can be prevented. On the other hand, the non-cutting region has a higher mechanical strength than the cutting region due to the second dummy pattern having a higher occupation ratio (density) than the first dummy pattern. It is possible to reduce the occurrence of damage due to stress generated in the cutting region. Further, since the clogging of the side surface of the dicing blade is prevented, the cutting ability can be recovered by polishing the end surface of the blade, so that the life of the dicing blade can be extended.

  In the semiconductor device of the present invention, the width of the cutting region is preferably equal to or larger than the blade width of the dicing blade that cuts the scribe region.

  In this way, it is possible to reliably prevent clogging of the dicing blade.

  The semiconductor device of the present invention preferably further includes a seal ring made of a conductive material formed on the semiconductor substrate so as to surround the periphery of the circuit region.

  In the semiconductor device of the present invention, the scribe region is formed around the circuit region, and is preferably a margin for cutting the circuit region from the semiconductor substrate.

  In the semiconductor device of the present invention, the pattern pitch of the first dummy pattern is preferably larger than the pattern pitch of the second dummy pattern.

  In this way, it is possible to reliably prevent clogging of the side surface of the dicing blade.

  In the semiconductor device of the present invention, the pattern size of the first dummy pattern is preferably smaller than the pattern size of the second dummy pattern.

  Even in this case, it is possible to reliably prevent clogging of the side surface of the dicing blade.

  In the semiconductor device of the present invention, the average occupancy per unit area in the cut area of the first dummy pattern is 10% or more and less than 25%, and the average occupancy per unit area in the non-cut area of the second dummy pattern is The average occupation ratio is preferably 25% or more and 90% or less.

  In the semiconductor device of the present invention, the region in contact with the side surface of the dicing blade in the cutting region is preferably the first space where the first dummy pattern is not formed.

  In this way, at least the side surface of the dicing blade does not come into contact with the conductive material during the singulation, so that the clogging of the side surface of the dicing blade can be prevented. As a result, the generation of cracks in the substrate can be more effectively prevented.

  In the semiconductor device of the present invention, the width of the first space is preferably equal to or greater than the minimum pitch length of the first dummy pattern.

  In this way, clogging of the side surface of the dicing blade can be reliably prevented.

  In the semiconductor device of the present invention, the cutting region includes a first region that includes at least a region in contact with the side surface of the dicing blade and is adjacent to the non-cutting region, and a second region excluding the first region, The occupation rate per unit area of the first dummy pattern in one region is preferably smaller than the occupation rate per unit area of the first dummy pattern in the second region.

  Furthermore, in the semiconductor device of the present invention, the cutting region includes at least a region that is in contact with the side surface of the dicing blade and that is adjacent to the non-cutting region, and a second region that excludes the first region. However, it is preferable that the first dummy pattern is not formed in the first region, and the first dummy pattern is formed only in the second region.

  If it does in this way, clogging of the side of a dicing blade can be prevented more certainly.

  In this case, it is preferable that the second region in the cutting region is smaller than the blade width of the dicing blade and located inside the both side surfaces of the dicing blade.

  In the semiconductor device of the present invention, the non-cutting region has a third region adjacent to the circuit region and a fourth region adjacent to the cutting region, and the second region is formed with a second dummy pattern. It is preferable that the second dummy pattern is formed only in the fourth region, which is the second space that is not formed.

    If it does in this way, unification of the structure of a non-cutting field and a circuit field can be cut off. In addition, by providing the second space having a low structural strength in the non-cutting region, even if a crack occurs in the substrate, damage caused by the crack may be released to the second space having a lower strength than other portions. As a result, cracks can be prevented from extending in the circuit area.

  In this case, the width of the second space is preferably equal to or greater than the minimum pitch length of the second dummy pattern.

  In the semiconductor device of the present invention, it is preferable that a third space in which the first dummy pattern is not formed is provided in the central portion along the cutting direction of the cutting region.

  In this way, the third space prevents clogging at the center portion of the tip surface of the dicing blade, and cracks generated in the semiconductor substrate are likely to extend in the depth direction. And the propagation of cracks can be prevented.

  In the semiconductor device of the present invention, the first interlayer insulating film is also formed on the circuit region in the semiconductor substrate, and a wiring electrically connected to the functional element is formed in the first interlayer insulating film. It is preferable that

  In this case, the semiconductor device includes a second interlayer insulating film formed on or below the first interlayer insulating film, a via formed in the second interlayer insulating film and electrically connected to the wiring. Is preferably further provided.

  According to the semiconductor device of the present invention, dishing that occurs in the CMP process can be prevented, and clogging of the dicing blade when the semiconductor substrate (wafer) is singulated can be reduced to suppress cracks generated in the semiconductor substrate. it can. In addition, since the circuit region can be protected from damage that occurs during separation, chipping can be prevented, and a highly reliable semiconductor device can be realized.

(One embodiment)
An embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a planar configuration of the semiconductor device according to the first embodiment.

  As shown in FIG. 1, the semiconductor device according to the present embodiment includes a plurality of functional elements (not shown) electrically connected to a wafer-like semiconductor substrate 1 by wirings and vias connected to the wirings. The circuit regions 2 are formed in a matrix at intervals from each other.

  Each circuit region 2 is surrounded by an annular seal ring 3 including one line or two or more lines of line vias. Here, the line via refers to, for example, a line-shaped via connected along a line-shaped wiring formed in the first interlayer insulating film.

  In a region between the circuit regions 2 surrounded by the seal ring 3 in the semiconductor substrate 1, a scribe region 4 serving as a margin for a semiconductor device, that is, a separation process for cutting out the circuit region 2 from the semiconductor substrate 1. Is formed.

  In the circuit region 2, a wiring pattern (not shown) made of wiring and vias, and a dummy wiring (not shown) made of the same conductive material as the wiring pattern and dummy vias are formed. In the scribe region 4, dummy wirings (not shown) made of dummy wirings and dummy vias made of the same conductive material as the wiring pattern are formed. In this manner, by providing the dummy pattern in the circuit region 2 and the scribe region 4, it is possible to prevent dishing that occurs in the CMP process.

  2A is a partially enlarged view of the end of the circuit region 2 in FIG. 1 and the scribe region 4 provided between the circuit regions 2, and FIG. 2B shows a cross-sectional configuration taken along the line IIb-IIb in FIG. 2A. Show. FIG. 2A shows the upper surface of one of the plurality of first interlayer insulating films.

  As shown in FIG. 2A, the scribe region 4 is a central portion thereof, and is a cut region 5 cut by the dicing blade 19 in the singulation process, and a non-cut region that is located on both sides of the cut region 5 and is not cut. It is divided into six. A first dummy pattern 7 is formed in the cut area 5, and a second dummy pattern 8 is formed in the non-cut area 6. Here, the cutting region 5 in the scribe region 4 includes at least a region in contact with the blade of the dicing blade 19 and has a width equal to or larger than the blade width of the dicing blade 19.

  As shown in the sectional view of FIG. 2B, the semiconductor device according to the present embodiment is formed on the upper surface of the semiconductor substrate 1, and includes a first interlayer insulating film 11 including wirings and dummy wirings, and a second layer including vias and dummy vias. The interlayer insulating films 12 are alternately stacked. Here, the first dummy pattern 7 is formed in the cut region 5 in the first interlayer insulating film 11, and the second dummy pattern 8 is formed in the non-cut region 6 in the first interlayer insulating film 11. ing. On the other hand, no dummy pattern is formed in the cut region 5 and the non-cut region 6 in the second interlayer insulating film 12. Note that an etching stopper film or a cap film may be formed between the first interlayer insulating film 11 and the second interlayer insulating film 12. Also, functional elements formed on the upper surface or the main surface of the semiconductor substrate 1, such as a diffusion layer and a gate electrode of a transistor, are omitted.

  A first protective film 16a and a second protective film 16b made of an insulating material are provided on the uppermost layer of the plurality of first interlayer insulating films 11, spaced apart from each other on the circuit region 2 and the scribe region 4, respectively. It is formed by laminating sequentially. A resin protective film 17 made of an insulating material is formed on the circuit region 2 in the second protective film 16b. In addition, a buried film 18 made of a conductive material is disposed on the end portion of the first protective film 16a on the scribe region 4 side.

  In the present embodiment, the occupation rate per unit area in the cut region 5 of the first dummy pattern 7 is made smaller than the occupation rate per unit area in the non-cut region 6 of the second dummy pattern 8. ing. Here, as the occupation ratio per unit area, an average occupation ratio that is an average value of a plurality of data obtained by measuring a plurality of measurement regions may be used.

  As described above, the semiconductor device provided on the wafer-like semiconductor substrate 1 according to the present embodiment includes each of the region including at least the cut region 5 in the scribe region 4 and the non-cut region 6 located on both sides of the region. The occupation ratio per unit area of the first dummy pattern 7 and the second dummy pattern 8 to be arranged is set to be smaller in the first dummy pattern than in the second dummy pattern. As a result, in the scribe region 4, the structural integrity of the cut region 5 and the non-cut region 6 is lost, so that an intensity distribution can be generated in the scribe region 4. That is, the strength of the non-cutting region 6 is higher than the strength of the cutting region 5. Thereby, the damage which arises in the cutting | disconnection area | region 5 in the singulation process reaches the non-cutting | disconnection area | region 6 easily.

  In other words, in the semiconductor device according to the present embodiment, the arrangement of the first dummy pattern 7 with respect to the cut region 5 is made sparser than the arrangement of the second dummy pattern 8 with respect to the non-cut region 6. For example, the first dummy pattern 7 is arranged so that the pattern pitch of the first dummy pattern 7 is larger than that of the second dummy pattern 8, or the pattern size of the first dummy pattern 7 is smaller than that of the second dummy pattern 8. . Thus, clogging of the dicing blade 19 in the singulation process is reduced by making the amount of the conductive material constituting the first dummy pattern 7 per unit area smaller than that of the second dummy pattern. Can do. For this reason, it is possible to prevent the occurrence of cracks (hereinafter simply referred to as substrate cracks) in the semiconductor substrate 1 due to clogging of the dicing blade 19.

  On the other hand, the non-cut region 6 in the scribe region 4 is stronger than the cut region 5 in which the first dummy patterns 7 are sparsely arranged because the second dummy patterns 8 are densely arranged. Therefore, it is possible to reduce the occurrence of damage due to stress generated in the non-cut region 6 in the singulation process.

  In order to prevent clogging of the dicing blade 19 more effectively, the arrangement of the first dummy patterns 7 in the cutting region 5 should be as sparse as possible within the range in which the film thickness uniformity in the CMP process is maintained. preferable. For this reason, it is preferable that the average occupation rate per unit area in the cut region 5 of the first dummy pattern 7 is 10% or more and less than 25%. On the contrary, in order to reduce the occurrence of damage due to the stress generated in the non-cut region 6, it is preferable that the arrangement of the second dummy patterns 8 is as dense as possible. For this reason, it is preferable that the average occupation rate per unit area in the non-cut region 6 of the second dummy pattern 8 is about 25% to 90%. Note that the average occupation rate per unit area in the cut region 5 of the first dummy pattern 7 is not limited to the above range. Since the average occupancy per unit area in the non-cut region 6 of the second dummy pattern 8 is low and it is only necessary to prevent dishing that occurs in the CMP process, for example, it may be 5% or more and less than 50%. Good.

  FIG. 3 shows the relationship between the dummy density (area ratio) and the chipping amount of the first dummy pattern 7 according to this embodiment. Here, the horizontal axis represents the pattern area ratio, and the vertical axis represents the chipping amount. Thus, it can be seen that the smaller the area ratio of the first dummy pattern 7, the higher the chipping prevention effect.

  In the present embodiment, the width of the scribe region 4 is, for example, about 60 μm to 150 μm, and the width of the cutting region 5 located at the center is about 30 μm to 70 μm, which is the same as or slightly larger than the dicing blade 19. The width of the non-cut region 6 located on both sides of the cut region 5 is about 5 μm to 40 μm.

  In general, an insulating material such as TEOS (Tetra-Ethyl-Ortho-Silicate) or FSG (Fluoro-Silicate-Glass) can be used for the first interlayer insulating film 11 and the second interlayer insulating film 12. In addition, various low dielectric constant films such as silicon oxide carbide (SiOC) or porous films can be used for the interlayer insulating films 11 and 12. The first interlayer insulating film 11 and the second interlayer insulating film 12 may be made of the same material or different materials.

  In FIG. 2B, the first interlayer insulating film 11 and the second interlayer insulating film 12 are shown with the same film thickness in a simplified manner, but the first interlayer insulating film 11 and the second interlayer insulating film 12 The interlayer insulating film 12 may have the same film thickness or a different film thickness. For example, the first interlayer insulating film 11 and the second interlayer insulating film 12 on the lower layer side (for example, the first layer and the second layer) of the stacked structure (for example, the seven-layer structure) have a thickness of about 100 nm to 300 nm. The first interlayer insulating film 11 and the second interlayer insulating film 12 on the upper layer side (for example, the sixth layer and the seventh layer) are made of TEOS having a film thickness of about 300 nm to 1500 nm. It is preferable to use an interlayer insulating film. Further, TEOS or the like having a film thickness of about 200 nm to 500 nm may be used for the intermediate layer portion (for example, the third to fifth layers).

  The dummy wirings and dummy vias constituting the dummy pattern formed in the circuit region 2 and the scribe region 4 form wirings and vias constituting the wiring pattern formed in the circuit region 2 and the scribe region 4 by using a damascene process or the like. In the process, they can be formed simultaneously. Here, the wiring, the dummy wiring, the via, and the dummy via can be formed of a conductive material such as copper or a copper alloy, respectively. A barrier film (not shown) for preventing diffusion formed of a thin film such as titanium nitride (TiN) may be provided at the interface between the interlayer insulating films 11 and 12.

  In general, the first protective film 16a and the second protective film 16b formed on the upper surface of the uppermost first interlayer insulating film 11 include pad portions (not shown) made of a conductive material such as aluminum (Al). The opening is made of silicon nitride (SiN) or the like. Here, a two-layer structure composed of the protective films 16a and 16b is used, but a single layer or three or more layers may be used.

  The buried film 18 embedded in the space between the first protective film 16a and the second protective film 16b can be formed of a conductive material such as Al. For example, the buried film 18 can be formed simultaneously with the pad portion in the step of forming the pad portion. With this configuration, it is possible to reduce damage such as chipping that occurs during cutting in the singulation process.

  In addition, it is preferable to use polyimide or polybenzoxazole (PBO) resin for the resin protective film 17 that covers at least the upper surface of the circuit region 2. Thereby, the functional element formed in the circuit region 2 can be protected against external stress such as filler contained in the sealing resin material for sealing the separated semiconductor device.

  In the present embodiment, the seal ring 3 is doubled in the in-plane direction of the semiconductor substrate 1 and, as described above, is formed by alternately laminating line-shaped (line-shaped) wiring patterns and line vias. Has been. As a result of the sealing of the seal ring 3 configured as described above, the circuit region 2 and the outside are shut off, so that the circuit region 2 can be prevented from being contaminated by water or impurities. Here, the seal ring 3 can be formed of the same material in the same process as the wiring pattern formed in the circuit region 2. Moreover, the seal ring 3 does not necessarily need to be formed in double, and may be provided in a single or triple or more.

  Usually, the scribe region 4 is formed with an alignment mark and a process management pattern (not shown), and the first dummy pattern 7 and the second dummy pattern 8 are naturally aligned with each other. It is provided in a region where a process management pattern or the like is not formed. The first dummy pattern 7 and the second dummy pattern 8 are part of a region in a direction perpendicular to the cutting direction (cutting direction) in the scribe region 4 or one of the laminated interlayer insulating films 11 and 12. You may provide only in a part. Here, it is preferable that the alignment mark, the process management pattern, and the like be formed so as to fit in the cutting region 5 as much as possible.

  In the present embodiment, an example is shown in which the second interlayer insulating film 12 and the first interlayer insulating film 11 are alternately stacked for seven layers from the substrate side. The number of layers is not limited to this embodiment, and can be applied to various configurations.

  2A and 2B only schematically show the seal ring 3 and the dummy patterns 7 and 8, and the dummy patterns 7 and 8 of the present invention can be applied to various configurations other than FIGS. 2A and 2B. It is.

  Further, the seal ring 3 covering the periphery of each circuit region 2 is not necessarily an essential component for the present invention.

  This is not limited to the present embodiment, and the same applies to the entire semiconductor device of the present invention.

(First Modification of One Embodiment)
A first modification of one embodiment of the present invention will be described with reference to the drawings. FIG. 4 shows a cross-sectional configuration of a scribe region in the semiconductor device according to the first modification and including a seal ring. Here, in FIG. 4, the same components as those shown in FIG. This is the same in each modification shown below.

  As shown in FIG. 4, the semiconductor device according to the first modification includes a first region 5 a that includes at least a region in contact with the side surface 19 a and the tip surface 19 b of the dicing blade 19 in the cutting region 5 and is adjacent to the non-cutting region 6. The occupation ratio per unit area of the first dummy pattern 7 is made smaller than that of the second region 5b of the cutting region 5 excluding the first region 5a. That is, the arrangement of the first dummy pattern 7 formed in the first region 5a in contact with the side surface 19a of the dicing blade 19 is sparser than the arrangement of the first dummy pattern 7 formed in the second region 5b. Has been. The occupation rate per unit area of the first dummy pattern 7 in the second region 5b of the cut region 5 is equivalent to the occupation rate per unit area of the second dummy pattern 8 in the non-cut region 6. Or less.

  With this configuration, the dicing blade can reduce the amount of the conductive material constituting the first dummy pattern 7 at least in the first region 5a of the cutting region 5 in contact with the side surface 19a of the dicing blade 19 in the singulation process. The clogging of the 19 side surfaces 19a can be suppressed. For this reason, generation | occurrence | production of the substrate crack resulting from clogging of the dicing blade 19 can be prevented.

  Further, since clogging of the side surface 19a of the dicing blade 19 hardly occurs, the dicing blade 19 can be kept in a good state for a long time.

  Here, as an example, when the first region 5a of the cut region 5 in the first dummy pattern 7 includes a dummy pattern of one pitch with respect to the region width of at least two pitches in the second region 5b. Is shown.

(Second Modification of One Embodiment)
A second modification of the embodiment of the present invention will be described with reference to the drawings. FIG. 5 shows a cross-sectional configuration of a scribe region in the semiconductor device according to the second modified example and including a seal ring.

  As shown in FIG. 5, the semiconductor device according to the second modified example is a region adjacent to the non-cut region 6 of the cut region 5 in the scribe region 4, and at least a first region in contact with the side surface 19 a of the dicing blade 19. In 5a, the first dummy pattern 7 is not formed, and a first space 13 is provided. A first dummy pattern 7 is formed in the second region 5b excluding the first region 5a of the cutting region 5, and the unit area occupied in the second region 5b of the first dummy pattern 7 is The occupation ratio may be equal to or less than the occupation ratio per unit area in the non-cut region 6 of the second dummy pattern 8.

  With this configuration, when the laminated body of the interlayer insulating films 11 and 12 is cut by the dicing blade 19 in the singulation step, at least the side surface 19a of the dicing blade 19 is electrically conductive to form the first dummy pattern 7. The material does not come into contact. For this reason, since clogging of the side surface 19a of the dicing blade 19 can be prevented, generation of a substrate crack due to clogging of the dicing blade 19 can be prevented. Moreover, since the clogging does not occur on the side surface 19a of the dicing blade 19, the life of the dicing blade 19 can be extended.

  Here, in order to more reliably prevent clogging of the side surface 19 a of the dicing blade 19, the width of the first space 13 (first region 5 a) is equal to or greater than the minimum pitch length of the first dummy pattern 7. It is desirable to be.

  Here, even if the blade width of the dicing blade 19 is smaller than the width of the second region 5b in which the first dummy pattern 7 is formed, the first dummy pattern as in the present modification example. By providing the first space 13 between the first dummy pattern 8 and the second dummy pattern 8, the first space 13 can provide an effect as a stress relaxation layer, and chipping in the chip internal direction can be achieved. The effect of prevention can be acquired.

(Third Modification of One Embodiment)
A third modification of the embodiment of the present invention will be described with reference to the drawings. FIG. 6 shows a cross-sectional configuration of a scribe region in the semiconductor device according to the third modified example and including a seal ring.

  As shown in FIG. 6, in the semiconductor device according to the third modified example, the non-cut region 6 in the scribe region 4 is adjacent to the third region 6 a adjacent to the circuit region 2 including the seal ring 3 and the cut region 5. And a fourth region 6b. Here, in the third region 6a, the second dummy pattern 8 is not formed. Instead, the third region 6a is the second space 14, and only the fourth region 6b is the second region. Two dummy patterns 8 are formed.

  With this configuration, the structural integrity between the non-cut region 6 in the scribe region 4 and the circuit region 2 including the seal ring 3 adjacent to the non-cut region 6 can be cut off. In addition, the second region 14a in the first interlayer insulating film 11 that does not include the second dummy pattern 8 made of a conductive material and has a structurally low mechanical strength is provided. Even if a substrate crack occurs during separation, damage due to the crack can be released to the second space 14 that is easily destroyed, so that the substrate crack extends beyond the seal ring 3 to the circuit region 2. Can be prevented.

  Here, the width of the second space 14 (third region 6a) is equal to or larger than the minimum pitch length of the second dummy pattern 8 or the seal ring 3 so as to secure a region in which damage caused by the substrate crack is released. It is desirable to be.

  In one embodiment of the present invention and each modification thereof, the first dummy pattern 7 and the second dummy pattern 8 are formed as a plurality of island-shaped (isolated) formed in the first interlayer insulating film 11. ) Although described as a dummy wiring, each dummy wiring is not limited to an island shape, and may be a shape in which a line-shaped wiring and a line-shaped wiring, or a combination of a line-shaped wiring and an island-shaped wiring. Furthermore, a configuration may be employed in which a plurality of dummy vias or line vias are provided in the dummy wiring.

  Further, as shown in FIG. 7, in the semiconductor device according to the present invention, in the scribe region 4, the first space 13 is provided in the first region 5 a of the cutting region 5 and the third region of the non-cutting region 6. It is good also as a structure which provides the 2nd space 14 in 6a. At this time, the first dummy pattern 7 is provided only in the second region 5 b of the cut region 5, and the second dummy pattern 8 is provided only in the fourth region 6 b of the non-cut region 6. With such a configuration, the effect of preventing clogging of the dicing blade 19 by the first space 13 and the effect of protecting the circuit region 2 by escaping damage such as substrate cracks by the second space 14 are achieved. Can be obtained.

  As in this modification, by providing the second space 14 in the third region 6a in the uncut region 6 of the scribe region 4, the second space 14 can provide an effect as a stress relaxation layer. And the effect of preventing chipping in the inner direction of the chip can be obtained.

(Fourth modification of one embodiment)
A fourth modification of the embodiment of the present invention will be described with reference to the drawings. 8A to 8F show the configuration of a scribe region in a semiconductor device according to a fourth modification, which includes a seal ring, FIG. 8A is a plan view, and FIGS. 8B to 8F are cross-sectional views. .

  First, as shown in FIG. 8A and FIG. 8B which is a cross-sectional view thereof, the semiconductor device according to the fourth modified example has a first dummy pattern 7 in the center portion along the cutting direction of the cutting region 5 in the scribe region 4. A third space 22 in which no is formed is provided. That is, in the fourth modified example, the first dummy pattern 7 is formed in a region other than the central portion of the cut region 5.

  With this configuration, the effect of preventing clogging of the dicing blade 19 and the effect of preventing chipping can be obtained. Specifically, the third space 22 prevents clogging of the central portion of the tip surface 19b of the dicing blade 19, and further, cracks generated in the semiconductor substrate 1 easily extend in the depth direction. Lateral stress and crack propagation can be prevented.

  FIG. 8C is a configuration in which the configuration in which the third space 22 is provided in the cutting region 5 according to the fourth modified example is combined with the first modified example of the present embodiment. That is, the configuration shown in FIG. 4 is a configuration in which the third space 22 is provided in the center of the second region 5b of the cutting region 5, and the other configuration is the same as the configuration shown in FIG. .

  FIG. 8D shows a configuration in which the configuration according to the fourth modification is combined with the second modification of the present embodiment. That is, in the configuration shown in FIG. 5, the third space 22 is provided at the center of the second region 5b of the cutting region 5, and the other configuration is the same as the configuration shown in FIG. .

  FIG. 8E shows a configuration in which the configuration according to the fourth modification is combined with the third modification of the present embodiment. That is, in the configuration shown in FIG. 6, the third space 22 is provided at the center of the cutting region 5, and the other configuration is the same as the configuration shown in FIG. 6.

  FIG. 8F shows a configuration in which the configuration according to the fourth modification is combined with another example of the third modification of the present embodiment. That is, in the configuration shown in FIG. 7, the third space 22 is provided in the center of the second region 5b of the cutting region 5, and the other configuration is the same as the configuration shown in FIG. .

  Even if it does in this way, the effect of the semiconductor device concerning each modification can be acquired, respectively.

(Fifth Modification of One Embodiment)
Further, as shown in FIGS. 8G and 8H, the first dummy pattern made of a conductive material may not be formed in the cut region 5 in the scribe region 4. With this configuration, clogging of the dicing blade 19 can be reliably prevented. FIG. 8G is a configuration in which the first dummy pattern 7 is not formed in the cutting region 5 with respect to the configuration shown in FIG. 2B, and the other configuration is the same as the configuration shown in FIG. 2B. 8H is a configuration in which the first dummy pattern 7 is not formed in the cutting region 5 with respect to the configuration shown in FIG. 6, and the other configuration is the same as the configuration shown in FIG.

(Sixth Modification of One Embodiment)
A sixth modification of the embodiment of the present invention will be described with reference to the drawings. FIG. 9 shows a cross-sectional configuration of a scribe region in a semiconductor device according to the sixth modification and including a seal ring. FIG. 9 is a configuration in which the second space 15 is formed in the non-cut region 6 with respect to the configuration shown in FIG. 2B, and the other configuration is the same as the configuration shown in FIG. 2B.

  As shown in FIG. 9, the semiconductor device according to the sixth modification is formed in the non-cut region 6 of the scribe region 4 in parallel and obliquely with respect to the normal line of the main surface of the semiconductor substrate 1. Two rows of second spaces 15 are provided. Specifically, each of the second spaces 15 is formed such that a lower portion thereof is positioned on the cutting region 5 side and an upper portion thereof is positioned on the seal ring 3 side adjacent to the non-cutting region 6.

  Thus, in the semiconductor device according to the sixth modified example, the second space 15 having a low structural strength without including the second dummy pattern 8 made of the conductive material is provided in the uncut region 6 of the scribe region 4. By being provided, the second space 15 of the non-cutting region 6 is easily destroyed in the singulation process. Therefore, the stress that causes film peeling or substrate cracking of the respective interlayer insulating films 11 and 12 can be absorbed by the second space 15. In particular, by providing a plurality of second spaces 15 continuously from the lower part on the cut region 5 side to the upper part on the seal ring 3 side in each interlayer insulating film 11, 12, the crack extends to the semiconductor substrate 1 side. Since it becomes difficult, a substrate crack can be escaped more effectively. That is, when separating into pieces, the stress that causes film peeling or substrate cracks starting from the cutting region 5 is obliquely applied from the lower portion on the cutting region 5 side to the upper portion on the seal ring 3 side in the non-cutting region 6. It is possible to effectively escape to the upper layer side along the second space 15 which is a non-strengthened region formed in the above.

  The second space 15 is not limited to two rows, and may be one row or three or more rows.

  In the sixth modification, the second space 15 is formed in an oblique direction so that the lower part is on the cutting region 5 side and the upper part is on the seal ring 3 side. It may be formed. Specifically, the lower portion of the second space 15 may be the seal ring 3 side and the upper portion may be the cutting region 5 side so that the substrate crack does not reach the circuit region 2.

  As a seventh modified example, as shown in FIG. 10A, the second space 15 has a second lower portion in the non-cutting region 6 so that the lower portion is widened and the upper portion is narrowed toward the seal ring 3 side. The dummy pattern 8 may not be arranged. On the other hand, as shown in FIG. 10B, the second space 15 is formed so that the upper part of the non-cutting region 6 is widened and the lower part is narrowed toward the cutting region 5 side. The dummy pattern 8 may not be arranged.

  Also in the sixth and seventh modified examples, the first dummy pattern 7 and the second dummy pattern 8 are not limited to the plurality of island-like dummy wirings formed in the first interlayer insulating film 11, but have various configurations. Can be taken. The configuration is shown below.

  11A, FIG. 11B, FIG. 12A, and FIG. 12B show the configuration of the second dummy pattern in the scribe region and the region including the seal ring in the semiconductor device according to the eighth modification of the present invention.

  The second dummy pattern 8 formed in the non-cut region 6 of the scribe region 4 shown in FIG. 11A is configured by line-shaped dummy wirings each extending in a direction perpendicular to the scribe region 4. The dummy wiring is divided by the second space 15.

    The second dummy pattern 8 shown in FIG. 11B is composed of line-shaped dummy wirings and line vias each extending in a direction perpendicular to the scribe region 4, and the dummy wirings and line vias are divided by the second space 15. ing.

  The second dummy pattern 8 shown in FIG. 12A includes island-shaped dummy wirings or line-shaped dummy wirings extending in a direction parallel to the scribe region 4 (cutting direction) and island-shaped dummy vias, The dummy via is divided by the second space 15.

The second dummy pattern 8 shown in FIG. 12B has a mesh structure including line-shaped dummy wirings each extending in a direction perpendicular to the scribe region 4 and island-shaped dummy vias or line vias extending in the cutting direction. The network structure is divided by the second space 5. Note that the dummy vias adjacent in the vertical direction may be arranged so as to be placed on one straight line (normal line) perpendicular to the substrate surface, or may be arranged so as to be shifted from each other.
In addition to these, the second dummy pattern 8 can take various configurations as will be described later.

  In the sixth to eighth modifications, the first space 13 can be provided in the cutting region 5 of the scribe region 4 and the second space 14 can be provided in the non-cutting region 6. Further, the first dummy pattern 7 may not be provided in the cutting area 5.

  By the way, in one embodiment of the present invention and each modification thereof, the first dummy pattern 7 provided in the cutting region 5 of the scribe region 4 is disposed so as not to impair the uniformity of the film thickness in the CMP process as described above. Is preferably made as sparse as possible, and is preferably formed by a plurality of island-like dummy wirings formed in the first interlayer insulating film 11.

  Hereinafter, a more effective configuration of the first dummy pattern for preventing damage such as substrate cracking due to chipping and film peeling of the interlayer insulating film will be described by way of example.

(First Modification of First Dummy Pattern)
A first dummy pattern according to a first modification of the embodiment of the present invention and each modification thereof will be described with reference to the drawings. FIG. 13A to FIG. 13D show a planar configuration of the first dummy pattern according to the first modified example arranged in the cutting region of the scribe region.

  As shown in FIGS. 13A to 13D, the first dummy pattern 7 according to the first modification is formed by a plurality of island-like dummy wirings formed in the first interlayer insulating film. ing. Furthermore, the first dummy pattern 7 has an occupancy rate per unit length in a direction perpendicular to the cutting direction in the cutting region 5 smaller than an occupancy rate per unit length in the cutting direction in the cutting region 5. Has been placed. That is, the first dummy pattern 7 is formed so that the pattern arrangement is sparse in the direction perpendicular to the direction parallel to the cutting direction.

  For example, the first dummy pattern 7 shown in FIG. 13A has a space in a direction perpendicular to a direction parallel to a cutting direction of a plurality of island-shaped (planar square-shaped) dummy wirings arranged in an array. Is arranged to be wide.

  In the first dummy pattern 7 shown in FIG. 13B, a plurality of island-like dummy wirings arranged so that a space in a direction perpendicular to the direction parallel to the cutting direction is widened is parallel to the cutting direction. In the direction, they are arranged in a straight line, and in the direction perpendicular to the cutting direction, the end faces of the dummy wirings adjacent to each other are arranged so as not to be placed on one straight line.

  The first dummy pattern 7 shown in FIGS. 13C and 13D has two sides that oppose the planar shape of each dummy wiring in the arrangement pattern shown in FIGS. 13A and 13B. The rectangular shape is long in the direction parallel to the cutting direction.

  As described above, the first dummy pattern 7 according to the first modification is cut into the first interlayer insulating film by arranging the wiring patterns densely in the direction parallel to the direction perpendicular to the cutting direction. A plurality of wall structures having high mechanical strength in a direction parallel to the direction are formed. For this reason, the damage at the time of being separated into pieces along the space part with low mechanical strength sandwiched between the wall structures can be released in the cutting direction. As a result, chipping that occurs in a direction perpendicular to the cutting direction can be suppressed.

  Here, as shown in FIGS. 13 (b) and 13 (d), by preventing each end face of the pattern on which stress generated in a direction perpendicular to the cutting direction is likely to concentrate on one straight line, The generated damage can be easily escaped depending on the cutting direction. Further, the planar shape of the island-like dummy wiring is not limited to a square, and may be a polygonal shape. In this case, even in a polygonal shape, a dense wiring pattern can be obtained in the cutting direction by making the longitudinal direction coincide with the cutting direction, as shown in FIGS. 13 (c) and 13 (d). .

(Second Modification of First Dummy Pattern)
A first dummy pattern according to a second modification of the embodiment of the present invention and each modification thereof will be described with reference to the drawings. FIG. 14 shows a cross-sectional configuration in a direction parallel to the cutting direction of the first dummy pattern according to the second modification example arranged in the cutting region.

  As shown in FIG. 14, the plurality of first dummy patterns 7 are formed with the second interlayer insulating film 12 interposed in the first interlayer insulating film 11, respectively. As a feature of the second dummy pattern 7 according to the second modification, the end faces of the first dummy patterns 7 adjacent in the vertical direction in the direction parallel to the cutting direction are one of the main surfaces of the semiconductor substrate 1. It is formed so as not to overlap the normal.

  As described above, the end surfaces of the pattern in which stress is concentrated in the film thickness direction of the first interlayer insulating film 11 and the second interlayer insulating film 12 do not lie on one straight line (normal line) in the direction parallel to the cutting direction. By doing so, it is possible to reduce damage caused by cutting that occurs in each of the interlayer insulating films 11 and 12 such as film peeling.

  In this case, with respect to the cross section perpendicular to the cutting direction, the end faces of the first dummy patterns 7 respectively formed on the first interlayer insulating film 11 are placed on one straight line (normal line). It is preferable to arrange. This is because, in the direction perpendicular to the cutting direction, the space portion having a low structural strength is placed on one straight line (normal line) in the direction perpendicular to the cutting direction. This is because the general resistance is reduced.

  Next, in one embodiment of the present invention and each modification thereof, the second dummy pattern 8 is preferably arranged as densely as possible in order to increase the mechanical strength of the non-cut region 6. Various configurations such as combining island-shaped vias with a line-shaped dummy wiring and combining line vias with a line-shaped dummy wiring can be employed.

  In order to more effectively prevent chipping due to film peeling that occurs in each interlayer insulating film 11, 12, the second dummy pattern 8 is provided between the first interlayer insulating films 11 that are vertically adjacent to each other. The second interlayer insulating film 12 is preferably provided with a dummy via that connects the dummy wirings formed in the first interlayer insulating film 11. The dummy via functions as a wedge of each interlayer insulating film 11, 12 and can supplement the peeling resistance of each interlayer insulating film 11, 12. This is particularly effective when a low dielectric constant material having relatively low adhesion is used for each of the interlayer insulating films 11 and 12.

  Hereinafter, the second dummy pattern having an arrangement or shape that can more effectively prevent substrate cracking due to chipping and film peeling of the interlayer insulating films 11 and 12 will be described by way of example.

(First Modification of Second Dummy Pattern)
A second dummy pattern according to a first modification of the embodiment of the present invention and each modification thereof will be described with reference to the drawings. FIGS. 15A and 15B show a planar configuration of the second dummy pattern according to the first modification example arranged in one non-cutting region of the scribe region.

  As shown in FIGS. 15A and 15B, the second dummy pattern 8 according to the first modification is formed by a plurality of island-like dummy wirings formed in the first interlayer insulating film. ing. Further, in the second dummy pattern 8, the occupation rate per unit length in the direction perpendicular to the cutting direction in the non-cutting region 6 is smaller than the occupation rate per unit length in the cutting direction in the non-cutting region 6. Are arranged as follows. That is, the second dummy pattern 8 is formed such that the pattern arrangement is sparser in the direction perpendicular to the cutting direction than in the direction parallel to the cutting direction. A dummy via for connecting dummy wirings included in the first interlayer insulating film formed above and below the second interlayer insulating film may be formed for each second interlayer insulating film.

  For example, the second dummy pattern 8 shown in FIG. 15A has a space in a direction perpendicular to the direction parallel to the cutting direction of a plurality of island-shaped (planar square-shaped) dummy wirings arranged in an array. It arrange | positions so that a part may become large.

  Further, the second dummy pattern 8 shown in FIG. 15B has a plurality of island-shaped dummy wirings arranged in the cutting direction so that a space in a direction perpendicular to the direction parallel to the cutting direction is widened. In the parallel direction, they are arranged in a straight line, and in the direction perpendicular to the cutting direction, the end faces of the dummy wirings adjacent to each other are arranged so as not to be on one straight line.

  With this configuration, the second dummy pattern 8 has a higher mechanical strength in the direction parallel to the cutting direction in which the wiring patterns are densely arranged than in the direction perpendicular to the cutting direction in which the wiring patterns are sparsely arranged. Lower due to wide space part in direction. For this reason, damage caused by cutting in each interlayer insulating film in the singulation process can be released in a direction parallel to the cutting direction.

  Here, as shown in FIG. 15B, by preventing each end face of the pattern in which stress generated in a direction perpendicular to the cutting direction is likely to concentrate on one straight line, the generated damage is reduced in the cutting direction. Can make it easier to escape. Further, a dense wiring pattern can be arranged in the cutting direction by making the planar shape of each dummy wiring, for example, a rectangular shape and making its longitudinal direction coincide with the cutting direction.

  In addition, not only in this modification but also in each modification described below, similarly, the second dummy pattern 8 is densely arranged in the direction parallel to the cutting direction as compared with the direction perpendicular to the cutting direction, thereby cutting. It is possible to easily release the damage caused by the damage in a direction parallel to the cutting direction.

  In the present modification and each modification described below, the planar shape of the island-like dummy wiring is not limited to a square shape, and may be a polygonal shape.

(Second Modification of Second Dummy Pattern)
A second dummy pattern according to a second modification of the embodiment of the present invention and each modification thereof will be described with reference to the drawings. FIG. 16A to FIG. 16D show a planar configuration of the second dummy pattern according to the second modification example arranged in one uncut region of the scribe region.

  As shown in FIGS. 16A to 16D, the second dummy pattern 8 according to the second modified example has a plurality of island shapes (planar square shapes) formed in the first interlayer insulating film 11. These dummy wirings or line-shaped dummy wirings extending in a direction parallel to the cutting direction are formed. Further, in the second dummy pattern 8 according to the second modified example, the occupation rate per unit length on the cutting region 5 side in the direction perpendicular to the cutting direction is larger than the occupation rate per unit length on the seal ring 3 side. Is also arranged to be small. That is, the second dummy pattern 8 is formed so that the cutting region 5 side is sparse compared to the seal ring 3 side.

  For example, in the second dummy pattern 8 shown in FIG. 16A, the arrangement pitch of the plurality of island-like dummy wirings in the direction perpendicular to the cutting direction is set larger on the cutting region 5 side than on the seal ring 3 side. Is arranged. In the second dummy pattern 8 shown in FIG. 16B, the wiring pitch of the line-shaped dummy wirings extending in parallel with the cutting direction is arranged so that the cutting region 5 side is larger than the sealing ring 3 side. . Further, as shown in FIGS. 16C and 16D, instead of changing the wiring pitch in the direction perpendicular to the cutting direction, the width dimension in the direction perpendicular to the cutting direction of the pattern is sealed. By arranging the cutting region 5 side to be smaller than the ring 3 side, a density difference may be formed in the arrangement.

  With such a configuration, the mechanical strength of the non-cutting region 6 on the seal ring 3 side is structurally higher than that on the cutting region 5 side, so that damage caused by cutting in the singulation process is released to the non-cutting region 6. The damage generated in the non-cutting region 6 can be prevented from reaching the seal ring 3 side. Here, it is more effective if the second dummy pattern 8 is formed stepwise from the cutting region 5 side toward the seal ring 3 side in a sparse and dense manner.

  As shown in FIGS. 16 (a) and 16 (c), the second dummy pattern 8 is perpendicular to the cutting direction, and each end face on which stress tends to concentrate is placed on one straight line. By arranging so that there is no damage, it is possible to easily release damage caused by cutting to each interlayer insulating film in the cutting direction. Further, as shown in FIGS. 16B and 16D, the use of a line-shaped dummy wiring extending in parallel to the cutting direction as the second dummy pattern 8 causes a cut in each interlayer insulating film. Damage can be easily escaped by the cutting direction.

  Further, not only in this variation but also in each variation described below, similarly, the second dummy pattern 8 is generated by cutting by arranging the second dummy pattern 8 so that the cutting region 5 side is sparser than the seal ring 3 side. Damage can be easily released in a direction parallel to the cutting direction.

  Further, in the present modified example and each modified example described below, the planar shape of the line-shaped dummy wiring is not limited to a linear shape, and may have a curve or a branch. Further, the width is not necessarily uniform and may be partially wide or narrow.

(Third Modification of Second Dummy Pattern)
A second dummy pattern according to a third variation of the embodiment of the present invention and each variation thereof will be described with reference to the drawings. FIGS. 17A and 17B show a planar configuration of the second dummy pattern according to the third modification example arranged in one uncut region of the scribe region.

  As shown in FIGS. 17A and 17B, the second dummy pattern 8 according to the third modification is provided with a plurality of island-like dummy wirings formed in the first interlayer insulating film. Are formed so as to be non-uniform in the plane. For example, in the second dummy pattern 8 shown in FIG. 17A, a plurality of island-shaped dummy wirings having a square shape with the same planar shape are arranged so that the wiring pitch is not uniform. Further, the second dummy pattern 8 shown in FIG. 17B is arranged by arranging a plurality of island-like dummy wirings having square shapes having different plane dimensions or aspect ratios in each wiring pattern. A density difference may be formed.

  With this configuration, since the regions having different strengths are unevenly present in the non-cut region 6 in the first interlayer insulating film, the load applied to each interlayer insulating film in the singulation process is dispersed. Therefore, it is possible to make it difficult to cause damage to the non-cut region 6 of each interlayer insulating film.

(Fourth modification of the second dummy pattern)
A second dummy pattern according to a fourth modification of the embodiment of the present invention and each modification thereof will be described with reference to the drawings. FIG. 18A to FIG. 18D show a planar configuration of the second dummy pattern according to the fourth modification example arranged in one uncut region of the scribe region.

  As shown in FIGS. 18A to 18D, the second dummy pattern 8 according to the fourth modified example has a recess on the first interlayer insulating film at least on the opposite side facing the cutting region 5. It is formed as a plurality of island-shaped dummy wirings having a planar polygon shape.

  In other words, the second dummy pattern 8 according to the fourth modified example has a corner on the surface facing the cutting region 5 whose inner angle exceeds 180 °. The stress tends to concentrate at the corner where the internal angle exceeds 180 °. Therefore, damage can be trapped at the corner, so that the crack can be prevented from extending to the seal ring 3 side.

(Fifth Modification of Second Dummy Pattern)
A second dummy pattern according to a fifth modification of the embodiment of the present invention and each modification thereof will be described with reference to the drawings. FIG. 19A to FIG. 19D show a planar configuration of the second dummy pattern according to the fifth modification example arranged in one uncut region of the scribe region.

  As shown in FIG. 19A to FIG. 19D, the second dummy pattern 8 according to the fifth modification example has an uneven shape on the first interlayer insulating film, at least on the facing surface facing the cutting region 5. And is formed as a plurality of line-shaped dummy wirings extending in parallel with the cutting direction.

  Therefore, also in the second dummy pattern 8 according to the fifth modification, stress tends to concentrate on the corner formed on the surface facing the cutting region 5 and having an inner angle exceeding 180 °, so that damage is caused at the corner. , So that cracks can be prevented from extending to the seal ring 3 side.

(Sixth Modification of Second Dummy Pattern)
A second dummy pattern according to a sixth modification of the embodiment of the present invention and each modification thereof will be described with reference to the drawings. FIG. 20A and FIG. 20B show a planar configuration of the second dummy pattern according to the sixth modified example arranged in one uncut region of the scribe region.

  As shown in FIGS. 20A and 20B, the second dummy pattern 8 is formed by a linear pattern extending in a direction perpendicular to the cutting direction of the scribe region.

  For example, in the second dummy pattern 8 shown in FIG. 20A, a plurality of island-like dummy wirings formed in the first interlayer insulating film are substantially close to each other in the direction perpendicular to the cutting direction. Are arranged in a line, and in a direction parallel to the cutting direction, they are arranged at relatively large intervals.

  As another example, in the second dummy pattern 8 shown in FIG. 20B, a line-shaped dummy wiring formed in the first interlayer insulating film extends in a direction perpendicular to the cutting direction and is relatively Are arranged at a wide interval.

  With such a configuration, the second dummy pattern 8 made of a conductive material formed so as to extend in a direction perpendicular to the cutting direction of the scribe region extends in a direction parallel to the cutting direction. Since it is a stopper material (chipping stop material), it is possible to reduce the amount of peeling (chip amount) due to chipping that occurs in the direction perpendicular to the cutting direction in the singulation process.

  Here, the interval in the direction parallel to the cutting direction in the second dummy pattern 8 is preferably about ¼ to twice the width of the non-cut region 6. By making the interval between the second dummy patterns 8 relatively large, it is possible to prevent stress from concentrating between the second dummy patterns 8, so that the chipping extends in a direction perpendicular to the cutting direction. Can be prevented.

  As a seventh modification, as shown in FIG. 21, the second dummy pattern 8 is formed in the first interlayer insulating film, and functions as a stopper material and extends in a direction perpendicular to the cutting direction. 8a and a plurality of island-like dummy patterns 8b for strengthening the structure formed between the line-like dummy patterns 8a. Here, it is preferable that the line-like dummy pattern 8a protrudes toward the cutting region 5 side than the island-like dummy pattern 8b.

  As an eighth modification, as shown in FIG. 22, a line-shaped dummy pattern 8a serving as a stopper material may be formed only in a region near the cutting region 5 side.

  In the seventh modification and the eighth modification, the structure-enhancing dummy pattern is not limited to the island shape, and may be a line shape parallel to the cutting direction. The various variations described above in the first to fifth modifications. You may use in combination with a modification.

(Ninth Modification of Second Dummy Pattern)
A second dummy pattern according to a ninth modification of the embodiment of the present invention and each modification thereof will be described with reference to the drawings. FIG. 23A and FIG. 23B show a planar configuration of a second dummy pattern according to the ninth modification example arranged in one non-cutting region of the scribe region.

  As shown in FIG. 23A and FIG. 23B, the second dummy pattern 8 according to the ninth modification includes a line-shaped first dummy wiring extending in a direction parallel to the cutting direction of the scribe region, It has a mesh-like planar structure formed by line-shaped second dummy wirings extending in a direction perpendicular to the cutting direction.

  Thus, by making the planar configuration of the second dummy pattern 8 formed in the non-cutting region 6 into a mesh shape, the mechanical strength of the non-cutting region 6 is improved. Damage generated in the non-cut region of the interlayer insulating film can be reduced.

  Here, as shown in FIG. 23B, it is preferable that the second dummy wiring does not constitute one straight line in order to disperse the stress concentration applied to the end portion of the second dummy wiring on the cutting region 5 side.

  In order to release damage in a direction parallel to the cutting direction, it is preferable that the interval between the second dummy wirings is twice or more than the interval between the first dummy wirings.

(10th modification of 2nd dummy pattern)
A second dummy pattern according to a tenth modification of the embodiment of the present invention and each modification thereof will be described with reference to the drawings. FIGS. 24A and 24B show a planar configuration of the second dummy pattern according to the tenth modification example arranged in one non-cutting region of the scribe region.

  As shown in FIGS. 24A and 24B, the second dummy pattern 8 according to the tenth modification has at least one side forming 45 ° with respect to the cutting direction of the scribe region, and It is formed as a plurality of island-like dummy wirings having a planar polygonal shape with a recess on the opposite side facing the cutting region 5.

  With this configuration, when silicon (Si) is used for the semiconductor substrate, cracks extending in the <110> direction of the crystal zone axis, which is the cleavage direction of the semiconductor substrate, can be suppressed. This is particularly effective when the semiconductor substrate is cut in the <100> direction of its crystal zone axis.

(Eleventh Modification of Second Dummy Pattern)
A second dummy pattern according to an eleventh modification of the embodiment of the present invention and each modification thereof will be described with reference to the drawings. FIG. 25A to FIG. 25D show a planar configuration of the second dummy pattern according to the eleventh modification example arranged in one uncut region of the scribe region.

  As shown in FIGS. 25 (a) to 25 (d), the second dummy pattern 8 according to the eleventh modified example has a plurality of line-shaped dummy wirings each forming 45 ° with respect to the cutting direction of the scribe region. It is formed as.

  Even in such a configuration, as in the tenth modification, when silicon (Si) is used for the semiconductor substrate, cracks extending in the <110> direction of the crystallographic axis, which is the cleavage direction of the semiconductor substrate, are generated. In particular, it is effective when the semiconductor substrate is cut in the <100> direction of its crystal zone axis.

  In addition, as shown in FIG. 25C, when the second dummy pattern 8 is constituted by a line-like pattern inclined only in one direction, the dicing blade travel direction when separating into pieces (from above in the drawing). It is preferable to incline downward) because the resistance to the dicing blade is reduced. Note that the cutting in the <100> direction with respect to the semiconductor substrate is necessary accompanying the formation of the channel direction of the transistor element in the <100> direction in order to improve the capability of the transistor element.

  Although not shown in the drawings, as another modified example, instead of the line-shaped dummy wirings shown in FIGS. 25A to 25D, all or a part forms 45 ° with the cutting direction and It may be formed as a plurality of island-like dummy wirings arranged close to each other in a line shape.

  Although not shown, line-shaped dummy wirings each having an angle of 45 ° with respect to the cutting direction of the scribe area may be arranged at relatively wide intervals. Such a configuration also serves as a chipping stopper material (chipping stop material). Furthermore, it is preferable that a plurality of island-like dummy patterns for strengthening the structure be formed between the line-like dummy patterns that function as stopper materials. Here, it is preferable that the line-shaped dummy pattern protrudes to the cutting region 5 side than the island-shaped dummy pattern.

  The planar configuration of the dummy wiring formed in the first interlayer insulating film constituting the second dummy pattern in the embodiment of the present invention and each modification thereof has been described above, but is not limited to the above example. Various configurations such as a combination of a dummy dummy wiring and a line dummy wiring, or a dummy wiring having a bent portion or a branching portion can be employed.

  Further, the island-shaped dummy wirings may be formed in a square or polygonal pattern. Further, the line-shaped dummy wiring may be divided into two or more at arbitrary locations. Further, a part of the second dummy pattern and the seal ring may be integrally formed. The dummy wiring formed in the first interlayer insulating film may have a different pattern size, shape, or wiring direction for each interlayer insulating film.

(Twelfth Modification of Second Dummy Pattern)
A second dummy pattern according to a twelfth modification of the embodiment of the present invention and each modification thereof will be described with reference to the drawings. FIG. 26 shows a cross-sectional configuration in a direction parallel to the cutting direction of the second dummy pattern according to the twelfth modification example arranged in one non-cutting region of the scribe region.

  As shown in FIG. 26, the plurality of second dummy patterns 8 are formed with the second interlayer insulating film 12 interposed in the first interlayer insulating film 11 respectively. As a feature of the second dummy pattern 8 according to the twelfth modification, the end surfaces of the second dummy patterns 8 that are adjacent to each other in the direction parallel to the cutting direction are one of the main surfaces of the semiconductor substrate 1. It is formed so as not to overlap the normal.

  As described above, the end surfaces of the pattern in which stress is concentrated in the film thickness direction of the first interlayer insulating film 11 and the second interlayer insulating film 12 do not lie on one straight line (normal line) in the direction parallel to the cutting direction. By doing so, damage such as film peeling caused by cutting in the interlayer insulating films 11 and 12 can be reduced.

  In this case, even if the cross section in the direction perpendicular to the cutting direction is arranged so that the end face of the second dummy pattern 8 formed in each first interlayer insulating film 8 does not rest on a straight line, A higher effect can be obtained.

  As mentioned above, although the dummy wiring formed in the 1st interlayer insulation film which constitutes the 2nd dummy pattern in one embodiment and each modification of the present invention was explained, the 2nd dummy pattern concerning the present invention is A plurality of dummy vias or line vias formed in the second interlayer insulating film may be provided at an arbitrary position between the dummy wirings formed in the first interlayer insulating film.

  A configuration example in which dummy vias or line vias are provided in the second dummy pattern will be described below.

(Thirteenth Modification of Second Dummy Pattern)
A second dummy pattern according to a thirteenth modification of the embodiment of the present invention and each modification thereof will be described with reference to the drawings. FIGS. 27A and 27B are second dummy patterns according to the thirteenth modified example arranged in one non-cutting region of the scribe region, and FIG. 27A is perpendicular to the cutting direction. FIG. 27B shows a cross-sectional configuration in a direction parallel to the cutting direction along the line XXVIIb-XXVIIb in FIG.

  As shown in FIGS. 27A and 27B, the dummy vias constituting the second dummy pattern 8 are formed in each layer of the second interlayer insulating film 12 so as to be connected to the dummy wirings. ing. Furthermore, the center position of the dummy via formed in the second interlayer insulating film of one layer and the dummy via formed in the second interlayer insulating film of another layer adjacent to each other through the first interlayer insulating film 11 The center position is arranged so as not to be on one straight line (normal line).

  With this configuration, it is possible to disperse the damage caused by the cutting during the separation into a region around the dummy via portion where stress in the second interlayer insulating film 12 tends to concentrate.

  Here, the dummy vias are preferably arranged so that the cutting region 5 side is sparse compared to the seal ring 3 side. For example, the pitch of the dummy vias may be arranged so that the cutting region 5 side is larger than the seal ring 3 side. Further, the number of dummy vias may be arranged so that the cutting region 5 side is smaller than the seal ring 3 side. In this way, the non-cutting region 6 has higher mechanical strength on the seal ring 3 side than the cutting region 5 side, so that damage caused by cutting during the singulation process is released to the non-cutting region 6. At the same time, it is possible to prevent damage caused in the non-cutting region 6 from reaching the seal ring 3 side.

  The dummy vias provided in the second dummy pattern 8 are preferably arranged non-uniformly with respect to the non-cut region 6. As a result, regions having different strengths are non-uniformly distributed in the non-cut region 6 and the load at the time of singulation is distributed, so that the non-cut region 6 of each interlayer insulating film 11, 12 is damaged by cutting. Can be suppressed.

(14th modification of 2nd dummy pattern)
A second dummy pattern according to a fourteenth modification of the embodiment of the present invention and each modification thereof will be described with reference to the drawings. FIG. 28 shows a cross-sectional configuration in a direction parallel to the cutting direction of the second dummy pattern according to the fourteenth modification example arranged in one non-cutting region of the scribe region.

  As shown in FIG. 28, the second dummy patterns 8 are respectively formed on the line-shaped dummy wirings formed on the plurality of first interlayer insulating films 11 and on the plurality of second interlayer insulating films 12, respectively. Dummy vias are arranged in a cross-section mesh shape.

  Here, the network structure may be formed in a cross section in a direction parallel to the cutting direction, or may be formed in a cross section in a direction perpendicular to the cutting direction. Moreover, you may form in three dimensions in the direction parallel to a cutting direction, and a perpendicular | vertical direction. Furthermore, it may be formed in a cross section along a line-shaped dummy wiring extending in a direction oblique to the cutting direction.

  In general, stress is easily concentrated in a region surrounded by wiring and vias and is easily broken because of low mechanical strength. However, since the second dummy pattern according to the fourteenth modification has high mechanical strength due to the cross-sectional network structure, the interlayer insulating films 11 and 12 are unlikely to crack. That is, resistance to stress generated in the singulation process is improved.

  Note that the line-shaped dummy wirings formed in the first interlayer insulating film 11 do not necessarily have to be linear, and may be configured such that all or a part thereof is divided into strips. By intentionally providing a portion that is divided and structurally weak in this way, it is possible to absorb damage caused by cutting and prevent it from reaching the seal ring 3 side.

  Here, the center position of each dummy via formed in the second interlayer insulating film 12 of one layer is formed in the second interlayer insulating film of another layer adjacent through the first interlayer insulating film 11. It is preferable to arrange the dummy vias so that they do not lie on the same straight line (normal line). In this way, the dummy vias that tend to concentrate stress can be dispersed in the non-cut region 6 of the second interlayer insulating film 12.

  Further, it is preferable that the mesh-like cross-sectional structure in the second dummy pattern 8 is arranged so that the mesh structure on the cutting region 5 side is coarser than that on the seal ring 3 side. In this way, the non-cutting region 6 has a higher strength on the seal ring 3 side than the cutting region 5 side, so that damage caused by cutting in the non-cutting region 6 can be prevented from reaching the seal ring 3 side. it can.

  Furthermore, it is preferable to arrange the second dummy pattern 8 so that the mesh size is not uniform. As a result, regions having different strengths are non-uniformly distributed in the non-cutting region 6, so that the load at the time of singulation is dispersed, and the non-cutting region 6 of each interlayer insulating film 11, 12 is damaged by cutting. Can be suppressed.

(Fifteenth modification of the second dummy pattern)
A second dummy pattern according to a fifteenth modification of the embodiment of the present invention and each modification thereof will be described with reference to the drawings. FIG. 29A to FIG. 29C are second dummy patterns according to the fifteenth modified example arranged in one non-cutting region of the scribe region, and FIG. 29A is perpendicular to the cutting direction. 29B shows a cross-sectional configuration in the direction parallel to the cutting direction of the line XXIXb-XXIXb in FIG. 29A, and FIG. 29C shows a cross-sectional configuration in the line XXIXc-XXIXc of FIG. A cross-sectional configuration in a direction parallel to the direction is shown.

  As shown in FIGS. 29A to 29C, in each layer of the second interlayer insulating film 12, the line vias constituting the second dummy pattern 8 are respectively connected to the dummy wirings and parallel to the cutting direction. It is formed to extend in any direction. Further, the center position of the line via formed in the second interlayer insulating film of one layer and the line via formed in the second interlayer insulating film of another layer adjacent through the first interlayer insulating film 11 The center position is arranged so as not to be on one straight line (normal line).

  With this configuration, it is possible to realize a structure in which damage caused by cutting in the singulation process can be released in a region between line vias where stress is likely to concentrate, and the shielding power is high.

  Here, the interval between the line vias is preferably arranged so that the cutting region 5 side is larger than the seal ring 3 side. With this configuration, in each interlayer insulating film 11, 12, the mechanical strength of the non-cutting region 6 on the seal ring 3 side is improved as compared with the cutting region 5 side. Can prevent reaching the side.

(16th modification of 2nd dummy pattern)
A second dummy pattern according to a sixteenth modification of the embodiment of the present invention and each modification thereof will be described with reference to the drawings. FIG. 30 shows a configuration of a main part of the second dummy pattern according to the sixteenth modification example arranged in one non-cutting region of the scribe region.

  As shown in FIG. 30, the second dummy pattern 8 includes a plurality of line-shaped dummy wirings formed in the first interlayer insulating film 11 and a second adjacent to the first interlayer insulating film 11 in the vertical direction. The dummy insulating layer 12 is formed of dummy vias connected to the respective dummy wirings.

  As a feature of the sixteenth modification, each of the line-shaped dummy wirings is formed to extend in different directions. Here, the line-shaped dummy wirings may be arranged in a direction parallel to or perpendicular to the cutting region 6, or may be formed obliquely with respect to the cutting region 6.

  With such a configuration, the directionality of the stress applied to each of the interlayer insulating films 11 and 12 is dispersed, so that damage caused by cutting in the singulation process can be prevented from extending in one direction. .

(17th modification of 2nd dummy pattern)
A second dummy pattern according to a seventeenth modification of the embodiment of the present invention and each modification thereof will be described with reference to the drawings. FIG. 31A to FIG. 31C are second dummy patterns according to the seventeenth modified example arranged in one non-cutting region of the scribe region, and FIG. FIG. 31B shows a cross-sectional configuration taken along line XXXIb-XXXIb in FIG. 31A, and FIG. 31C shows a cross-sectional configuration taken along line XXXIc-XXXIc in FIG.

  As shown in FIGS. 31A to 31C, the second dummy pattern 8 includes, for example, a first interlayer insulating film 11 of the first layer and a first interlayer insulating film 11 of the fifth layer. Line-shaped dummy wirings extending in the same direction are formed. The second interlayer insulating film 12 of the second layer and the fourth layer are formed with dummy vias connected to the first-layer and fifth-layer line-shaped dummy wirings, respectively. Further, by forming island-shaped dummy wirings connected to the respective dummy vias in the first interlayer insulating film 11 in the third layer, two line-shaped dummy wirings, four dummy vias, two island-shaped wirings are formed. One ring structure is formed by the dummy wiring. Furthermore, another ring structure is formed so as to pass through the inside of the one ring structure.

  Here, the ring structure of the second dummy pattern 8 according to the seventeenth modification may be formed only with the line-shaped dummy wirings without using the island-shaped dummy wirings. Further, the line-shaped dummy wirings constituting each ring structure may be arranged in a direction parallel to or perpendicular to the cutting region 6, and formed obliquely with respect to the cutting region 6. May be.

  31 (a) to 31 (c) show a ladder pattern in which the ring structures are linearly connected. However, the present invention is not limited to this, and it is bent and connected so as to have a bent portion. Also good.

  According to the seventeenth modification, as the second dummy pattern 8 provided in the non-cut region 6 of the scribe region, a plurality of ring structures formed so as to pass through each other are used. A structure capable of absorbing damage due to cutting and having high mechanical strength can be realized.

  In addition, it is desirable that the ring structures formed so as to pass through each other are independent structures without being connected to each other by dummy wirings or dummy vias.

  The dummy vias formed in the second interlayer insulating film constituting the second dummy pattern described so far have been described as single vias for the sake of simplification, but are not limited to single vias. . That is, it may be constituted by a plurality of collective vias arranged densely in the via formation region. However, in this case, it goes without saying that the arrangement pitch of the dummy vias is larger than the pitch of the individual vias constituting the collective via.

  In one embodiment of the present invention and each modification thereof, the description of the impurity diffusion layer formed on the top of the semiconductor substrate is omitted.

  The first dummy pattern and the second dummy pattern use not only a normal conductive material for wiring but also a conductive material of the same wiring layer as the wiring forming the gate electrode as the dummy pattern. it can. In addition, an active region in which an STI (shallow trench isolation) isolation portion in which an insulating material is embedded in the peripheral portion is formed can be used as a dummy.

(STI separation part)
An embodiment of the present invention and an STI separation unit according to each modification will be described with reference to the drawings. 32A and 32B show a planar configuration of the scribe region in the semiconductor substrate, and FIG. 32B shows a cross-sectional configuration along the line XXXIIb-XXXIIb in FIG. 32A. However, FIG. 32A shows a planar configuration in a state where each interlayer insulating film and each dummy pattern are removed.

  As shown in FIGS. 32A and 32B, a plurality of STI isolation portions 21 are formed in a direction parallel to the cutting direction above the scribe region 4 in the semiconductor substrate 1. A plurality of dummy active regions 20 are formed between them.

  The arrangement of the first dummy pattern 7 formed in the cut region 5 of the scribe region 4 and the second dummy pattern 8 formed in the non-cut region 6 of the scribe region 4 is the same as that shown in FIG. It is.

  As described above, since the plurality of STI separation portions 21 that are likely to start cracks are provided in a direction parallel to the cutting direction, the extension direction of the crack is not in the seal ring 3 side but in a direction parallel to the cutting direction. Can do.

  As shown in FIG. 32B, STI isolation portions 21 are respectively provided above the first space 13 formed in the cut region 5 and the second space 14 formed in the non-cut region 6 in the semiconductor substrate 1. Is preferred. If it does in this way, like the 1st space 12 and the 2nd space 14, it can make it easy to escape the damage by a substrate crack to the field where mechanical strength was lowered intentionally.

  As described above, the configuration of the present invention is shown for the pattern of the scribe region 4, but an accessory pattern including an evaluation pattern or an alignment mark may be formed on the actual scribe region 4. Even a wafer-like semiconductor device including these accessory patterns is included in the present invention.

  Moreover, although one Embodiment of this invention and each modification example were demonstrated referring drawings, this embodiment and its modification are only illustrations of this invention, Embodiment which combined embodiment and its modification example Are also included in the present invention. Various configurations other than those shown in the drawings can be adopted within the scope of the technical idea of the present invention.

  The semiconductor device of the present invention can prevent dishing that occurs in the CMP process, reduce clogging of the dicing blade when the semiconductor substrate is singulated, and suppress cracks generated in the semiconductor substrate. This is useful for a semiconductor device having a structure.

1 is a plan view showing a wafer level semiconductor device according to an embodiment of the present invention. It is a partial enlarged plan view which shows the scribe area | region in the semiconductor device which concerns on one Embodiment of this invention. It is sectional drawing in the IIb-IIb line | wire of FIG. 2A. It is a graph which shows the relationship between the area ratio and chipping amount of the 1st dummy pattern in the semiconductor device which concerns on one Embodiment of this invention. It is sectional drawing which shows the scribe area | region in the semiconductor device which concerns on the 1st modification of one Embodiment of this invention. It is sectional drawing which shows the scribe area | region in the semiconductor device which concerns on the 2nd modification of one Embodiment of this invention. It is sectional drawing which shows the scribe area | region in the semiconductor device which concerns on the 3rd modification of one Embodiment of this invention. It is sectional drawing which shows the scribe area | region in the semiconductor device which concerns on the other example of the 3rd modification of one Embodiment of this invention. It is sectional drawing which shows the scribe area | region in the semiconductor device which concerns on the 4th modification of one Embodiment of this invention. It is sectional drawing in the VIIIb-VIIIb line | wire of FIG. 8A. It is sectional drawing which shows the scribe area | region in the semiconductor device which concerns on the other example of the 4th modification of one Embodiment of this invention. It is sectional drawing which shows the scribe area | region in the semiconductor device which concerns on the other example of the 4th modification of one Embodiment of this invention. It is sectional drawing which shows the scribe area | region in the semiconductor device which concerns on the other example of the 4th modification of one Embodiment of this invention. It is sectional drawing which shows the scribe area | region in the semiconductor device which concerns on the other example of the 4th modification of one Embodiment of this invention. It is sectional drawing which shows the scribe area | region in the semiconductor device which concerns on the 5th modification of one Embodiment of this invention. It is sectional drawing which shows the scribe area | region in the semiconductor device which concerns on the 5th modification of one Embodiment of this invention. It is sectional drawing which shows the scribe area | region in the semiconductor device which concerns on the 6th modification of one Embodiment of this invention. It is sectional drawing which shows the scribe area | region in the semiconductor device which concerns on the 7th modification of one Embodiment of this invention. It is sectional drawing which shows the scribe area | region in the semiconductor device which concerns on the other example of the 7th modification of one Embodiment of this invention. It is sectional drawing which shows the scribe area | region in the semiconductor device which concerns on the 8th modification of one Embodiment of this invention. It is sectional drawing which shows the scribe area | region in the semiconductor device which concerns on the other example of the 8th modification of one Embodiment of this invention. It is sectional drawing which shows the scribe area | region in the semiconductor device which concerns on the other example of the 8th modification of one Embodiment of this invention. It is sectional drawing which shows the scribe area | region in the semiconductor device which concerns on the other example of the 8th modification of one Embodiment of this invention. (A)-(d) is a top view which shows the 1st dummy pattern which concerns on the 1st modification arrange | positioned in the cutting | disconnection area | region in one Embodiment of this invention and each modification. It is sectional drawing which shows the direction parallel to the cutting direction of the 1st dummy pattern based on the 2nd modification arrange | positioned in the cutting area in one Embodiment of this invention and each modification. (A) And (b) is a top view which shows the 2nd dummy pattern based on the 1st modification arrange | positioned in one uncut area | region of the scribe area | region in one Embodiment of this invention and each modification. (A)-(d) is a top view which shows the 2nd dummy pattern which concerns on the 2nd modification arrange | positioned in one uncut area | region of the scribe area | region in one Embodiment and each modification of this invention. (A) And (b) is a top view which shows the 2nd dummy pattern which concerns on the 3rd modification arrange | positioned in one uncut area | region of the scribe area | region in one Embodiment and each modification of this invention. (A)-(d) is a top view which shows the 2nd dummy pattern which concerns on the 4th modification arrange | positioned in one uncut area | region of the scribe area | region in one Embodiment and each modification of this invention. (A)-(d) is a top view which shows the 2nd dummy pattern which concerns on the 5th modification arrange | positioned in one uncut area | region of the scribe area | region in one Embodiment of this invention and each modification. (A) And (b) is a top view which shows the 2nd dummy pattern which concerns on the 6th modification arrange | positioned at one uncut area | region of the scribe area | region in one Embodiment and each modification of this invention. It is a top view which shows the 2nd dummy pattern which concerns on the 7th modification arrange | positioned at one uncut area | region of the scribe area | region in one Embodiment of this invention and each modification. It is a top view which shows the 2nd dummy pattern which concerns on the 8th modification arrange | positioned at one uncut area | region of the scribe area | region in one Embodiment of this invention and each modification. (A) And (b) is a top view which shows the 2nd dummy pattern based on the 9th modification arrange | positioned in one uncut area | region of the scribe area | region in one Embodiment of this invention and each modification. (A) And (b) is a top view which shows the 2nd dummy pattern based on the 10th modification arrange | positioned at one uncut area | region of the scribe area | region in one Embodiment and each modification of this invention. (A)-(d) is a top view which shows the 2nd dummy pattern based on the 11th modification arrange | positioned in one uncut area | region of the scribe area | region in one Embodiment of this invention and each modification. It is sectional drawing which shows the direction parallel to the cutting direction of the 2nd dummy pattern based on the 12th modification arrange | positioned in the non-cutting area | region in one Embodiment of this invention and each modification. (A) is sectional drawing which shows a direction perpendicular | vertical to the cutting | disconnection direction of the 2nd dummy pattern based on the 13th modification arrange | positioned in one uncut area | region of the scribe area | region in one Embodiment of this invention and each modification. It is. (B) is sectional drawing in the XXVIIb-XXVIIb line | wire of (a). It is sectional drawing which shows the direction parallel to the cutting direction of the 2nd dummy pattern based on the 14th modification arrange | positioned in the non-cutting area | region in one Embodiment of this invention and each modification. (A) is sectional drawing which shows a direction perpendicular | vertical to the cutting direction of the 2nd dummy pattern based on the 15th modification arrange | positioned in one uncut area | region of the scribe area | region in one Embodiment of this invention, and each modification. It is. (B) is sectional drawing in the XXIXb-XXIXb line | wire of (a). (C) is sectional drawing in the XXIXc-XXIXc line | wire of (a). It is a perspective view of the principal part showing the 2nd dummy pattern concerning the 16th modification arranged in the non-cutting field in one embodiment of the present invention and each modification. (A) is a perspective view of an essential part showing a second dummy pattern according to a seventeenth modified example arranged in an uncut region in one embodiment of the present invention and each modified example thereof. (B) is sectional drawing in the XXXIb-XXXIb line | wire of (a). (C) is sectional drawing in the XXXIc-XXXIc line | wire of (a). It is a top view which shows the scribe area | region of the semiconductor substrate in the semiconductor device which concerns on one Embodiment of this invention, and each modification. It is sectional drawing in the XXXIIb-XXXIIb line | wire of FIG. 32A. (A) is a top view which shows the scribe area | region in the wafer level semiconductor device which concerns on a prior art example. (B) is sectional drawing in the XXXIIIb-XXXIIIb line | wire of (a).

Explanation of symbols

1 Semiconductor substrate (wafer)
2 Circuit area 3 Seal ring 4 Scribe area 5 Cutting area 5a First area 5b Second area 6 Uncut area 6a Third area 6b Fourth area 7 First dummy pattern 8 Second dummy pattern 8a Line Dummy pattern 8b island dummy pattern 11 first interlayer insulating film 12 second interlayer insulating film 13 first space 14 second space 15 second space 16a first protective film 16b second protective film 17 Resin protective film 18 Filled film 19 Dicing blade 19a Side surface 19b Front end surface 20 Dummy active region 21 STI isolation portion 22 Third space

Claims (17)

A circuit region having functional elements formed on a semiconductor substrate;
A scribe region, which is located between the circuit region and another circuit region formed at an interval from the circuit region, and includes a cutting region and non-cutting regions provided on both sides of the cutting region. When,
A first interlayer insulating film formed on the scribe region in the semiconductor substrate;
A first dummy pattern made of a conductive material formed in the cutting region in the first interlayer insulating film;
A second dummy pattern made of a conductive material formed in the non-cut region in the first interlayer insulating film,
2. The semiconductor device according to claim 1, wherein an occupation rate per unit area of the first dummy pattern in the cut region is smaller than an occupation rate per unit area of the second dummy pattern in the non-cut region. The semiconductor device according to claim 1,
The width of the cutting region is equal to or larger than the blade width of a dicing blade that cuts the scribe region. The semiconductor device according to claim 1 or 2,
A semiconductor device, further comprising: a seal ring made of a conductive material formed on the semiconductor substrate so as to surround the periphery of the circuit region. The semiconductor device according to any one of claims 1 to 3,
The semiconductor device, wherein the scribe region is formed around the circuit region, and is a margin for cutting the circuit region from the semiconductor substrate. The semiconductor device according to any one of claims 1 to 4,
The semiconductor device according to claim 1, wherein a pattern pitch of the first dummy pattern is larger than a pattern pitch of the second dummy pattern. The semiconductor device according to any one of claims 1 to 4,
The semiconductor device according to claim 1, wherein a pattern size of the first dummy pattern is smaller than a pattern size of the second dummy pattern. The semiconductor device according to any one of claims 1 to 6,
The average occupation rate per unit area in the cutting region of the first dummy pattern is 10% or more and less than 25%,
The semiconductor device, wherein an average occupation rate per unit area in the non-cut region of the second dummy pattern is 25% or more and 90% or less. The semiconductor device according to any one of claims 1 to 7,
A region in contact with the side surface of the dicing blade in the cutting region is a first space in which the first dummy pattern is not formed. The semiconductor device according to claim 8,
The width of the first space is equal to or greater than the minimum pitch of the first dummy pattern. The semiconductor device according to any one of claims 1 to 9,
The cutting region includes a first region that includes at least a region in contact with a side surface of the dicing blade and is adjacent to the non-cutting region, and a second region excluding the first region;
A semiconductor device characterized in that an occupation rate per unit area of the first dummy pattern in the first region is smaller than an occupation rate per unit area of the first dummy pattern in the second region. apparatus. The semiconductor device according to any one of claims 1 to 9,
The cutting region includes a first region that includes at least a region in contact with a side surface of the dicing blade and is adjacent to the non-cutting region, and a second region excluding the first region;
The semiconductor device, wherein the first dummy pattern is not formed in the first region, and the first dummy pattern is formed only in the second region. The semiconductor device according to claim 10 or 11,
The semiconductor device according to claim 1, wherein the second region in the cutting region has a width smaller than a blade width of the dicing blade and is located on an inner side than both side surfaces of the dicing blade. The semiconductor device according to any one of claims 1 to 12,
The non-cut region has a third region adjacent to the circuit region and a fourth region adjacent to the cut region,
The third region is a second space in which the second dummy pattern is not formed, and the second dummy pattern is formed only in the fourth region. . The semiconductor device according to claim 13,
The width of the second space is equal to or greater than the minimum pitch length of the second dummy pattern. The semiconductor device according to any one of claims 1 to 14,
A semiconductor device, wherein a third space in which the first dummy pattern is not formed is provided in a central portion along the cutting direction of the cutting region. The semiconductor device according to any one of claims 1 to 15,
The first interlayer insulating film is also formed on the circuit region in the semiconductor substrate,
The semiconductor device according to claim 1, wherein a wiring electrically connected to the functional element is formed in the first interlayer insulating film. The semiconductor device according to claim 16, wherein
A second interlayer insulating film formed above or below the first interlayer insulating film;
A semiconductor device, further comprising a via formed in the second interlayer insulating film and electrically connected to the wiring.

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