JP2011014603A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a conventional semiconductor device has an electric leak as polishing wastes of a silicon substrate harden nearby an electrode of the semiconductor device.SOLUTION: The semiconductor device has a wiring layer 4 and a Cu wiring layer 13 disposed on a surface side of a silicon substrate 2 and coated with resin films 10, 15. Side faces 18 and 19 of the semiconductor device 1 are perpendicular to a surface 20 of the semiconductor device 1, and the resin films 10, 15 and a position precision confirmation mark 14 are exposed from the side faces. With this structure, polishing wastes 22 of the silicon substrate 2 stick on the side faces 18 and 19 of the semiconductor device 1 to a certain extent, but never stick on the surface 20 thereof, thereby causing no electric leak through the polishing wastes 22.

Description

  The present invention relates to a semiconductor device that improves quality defects caused by scraps generated during back grinding and a method for manufacturing the same.

  The following manufacturing method is known as an example of a conventional method for manufacturing a semiconductor device. 9A to 9C are sectional views showing a back grinding process of a conventional WLP (Wafer Level Package).

  First, as shown in FIG. 9A, after the protective tape 53 is bonded to the surface side of the semiconductor wafer 51 in which the groove 52 is formed along the scribe region, the semiconductor wafer 51 is placed on the back grind table 54. Here, the protective tape 53 includes a base material 55 such as PET (polyethylene terephthalate) and an adhesive 56 such as an acrylic synthetic resin.

  Next, the semiconductor wafer 51 is polished from the back surface side, and the film thickness of the semiconductor wafer 51 is set to a desired thickness. At this time, by polishing up to the formation region of the groove 52 of the semiconductor wafer 51, the semiconductor wafer 51 is divided into individual WLP structure semiconductor devices. In this step, the polishing waste 57 of the semiconductor wafer 51 adheres to the cut surface 58 of the semiconductor wafer 51, the protective film 59 on the front surface side, the adhesive 56 of the protective tape 53, and the like.

  Next, as shown in FIG. 9B, the polished semiconductor wafer 51 is placed on the spinner table 60. Then, the water adhering to the semiconductor wafer 51 in the back grinding process is removed by centrifugal force. Thereafter, the protective tape 53 is heated by the heater 61 built in the spinner table 60, and the adhesive 56 is expanded in the direction of the groove 52. And when the adhesive 56 expand | swells, the grinding | polishing waste 57 adhering to the cut surface 58 and the protective film 59 of the semiconductor wafer 51 sticks to the adhesive 56. FIG. Then, by removing the protective tape 53, the polishing dust 57 can be removed from the cut surface 58 and the protective film 59 (see, for example, Patent Document 1).

JP 2007-165437 A (page 5-7, Fig. 1-3)

  In the WLP structure, an alignment mark (not shown) is formed in the scribe region of the semiconductor wafer 51, and after the position of the scribe region is recognized by the alignment mark, the scribe region is cut. The protective film 59 and the insulating layer 62 covering the surface side of the semiconductor wafer 51 deteriorate the alignment mark recognition accuracy depending on the material used and the film thickness. Therefore, as indicated by a circle 63 in FIG. 9A, the protective film 59 and the insulating layer 62 in the scribe region are recessed with respect to other regions in order to improve the alignment mark recognition accuracy.

  FIG. 9C is an enlarged cross-sectional view of a region indicated by a circle 63 in FIG. In the back grinding process, polishing is performed from the rear surface side of the semiconductor wafer 51 in a state where the protective tape 53 is attached to the front surface side of the semiconductor wafer 51. At this time, in the scribe region, a stepped step is formed from the surface side of the semiconductor wafer 51 toward the groove 52 due to the shape of the protective film 59 and the insulating layer 62 described above. With this structure, the region indicated by the circle 63 becomes a space region having a width W6 wider than the width W5 of the groove 52. Note that the protective film 59 covers the upper surface of the step-shaped insulating layer 62, thereby forming a step with a shape that is less than the insulating layer 62.

  A region indicated by a circle 64 is an adhesive region between the pressure-sensitive adhesive 56 and the protective film 59, but the pressure-sensitive adhesive 56 and the protective film 59 are difficult to adhere to each other due to the level difference of the protective film 59 described above, and the two are bonded. This is a region where the strength tends to weaken. As a result, the back grinding process is performed in a state in which the treated water is supplied to the polished surface. Therefore, particularly in the region indicated by the circle 64, the adhesive surface between the adhesive 56 and the protective film 59 is easily peeled off. Then, the polishing dust 57 remains on the upper surface of the protective film 59 around the pad electrode 65 and hardens, thereby causing a problem of electrical short circuit through the polishing dust 57.

  Furthermore, in the conventional manufacturing method, as shown in FIG. 9B, the adhesive 56 is expanded toward the groove 52 and the protective tape 59 is peeled off, so that the cut surface 58 and the protective film 59 of the semiconductor wafer 51 are removed. The attached polishing waste 57 is removed. However, the adhesive 56 exposed to the scribe region is already attached with a large amount of polishing debris 57 during the back grinding process, so that the adhesive strength is also deteriorated. In addition, the adhesive strength of the adhesive 56 in the region indicated by the circle 63 or the adhesive surface between the adhesive 56 indicated by the circle 64 and the protective film 59 is also deteriorated by being exposed to treated water during the back grinding process. . As a result, there is a problem that the adhesive strength of the pressure-sensitive adhesive 56 in the expansion region deteriorates and it is difficult to remove the polishing dust 57.

  Further, as described above, in the conventional WLP structure, there is no method or means for inspecting a cut surface of a semiconductor device separated after scribing, and it is confirmed whether or not a suitable range of the scribe region has been scribed. I couldn't. And by delivering the semiconductor device separated to the user side without inspecting the cut surface, on the user side, with the circuit device or set product etc. mounting the semiconductor device scribed in an inappropriate area, There is a problem that poor quality occurs.

  In the semiconductor device of the present invention, at least one main surface side of the substrate is covered with a resin layer, an electrode is formed on the surface side of the resin layer, and a side surface located between the one main surface of the substrate and the other main surface In the semiconductor device serving as a scribe surface, at least the resin layer and the substrate are exposed on the side surface, and the resin layer exposed on the side surface is a flat surface perpendicular to the surface of the resin layer. To do. Therefore, in the present invention, polishing scraps do not adhere to the resin layer surface side on which the electrodes are disposed, and electrical leakage through the polishing scraps can be prevented.

  In the method for manufacturing a semiconductor device according to the present invention, a semiconductor wafer is prepared, semiconductor elements are formed in a plurality of element formation regions of the semiconductor wafer, and a resin layer is formed on one main surface side of the semiconductor wafer. Forming the electrode on the surface side of the resin layer, and forming a groove reaching the semiconductor wafer from the resin layer along the scribe region of the semiconductor wafer, and then bonding a protective tape to the surface side of the resin layer And polishing the semiconductor wafer from the other main surface side of the semiconductor wafer to at least the groove forming region, and singulating the semiconductor wafer for each element forming region to form a semiconductor device. The resin layer is exposed from the side surface of the groove, and a part of the adhesive layer constituting the protective tape enters the groove so as to come into contact with the exposed resin layer. And performing the step of polishing the semiconductor wafer. Therefore, according to the present invention, when the semiconductor wafer is polished, it is possible to prevent polishing scraps from reaching the resin layer surface side.

  In the present invention, the resin layer is disposed up to the side surface (cut surface) of the semiconductor device, thereby preventing the polishing debris from entering the surface side and preventing electrical leakage through the polishing debris.

  In the present invention, the position accuracy confirmation mark is exposed on the side surface of the semiconductor device, and the exposed shape is confirmed, so that quality inspection after scribing can be performed.

  Further, in the present invention, since the periphery of the position accuracy confirmation mark is covered with an insulating layer having excellent moisture resistance, quality deterioration does not occur from the position accuracy confirmation mark forming region.

  Further, in the present invention, by performing the back grinding process in a state in which the adhesive layer of the protective tape is inserted into the scribe groove, it is possible to prevent polishing debris from entering the semiconductor device surface side.

  In the present invention, the product quality of the semiconductor device is improved by determining the scribe surface using the position accuracy confirmation mark exposed on the cut surface after scribing.

  Moreover, in this invention, the process of expanding an adhesion layer can be skipped and manufacturing cost can be held down.

1A is a cross-sectional view and FIG. 1B is a perspective view illustrating a semiconductor device according to an embodiment of the present invention. 1A is a perspective view and FIG. 2B is a plan view illustrating a semiconductor device according to an embodiment of the present invention. 1A is a cross-sectional view, FIG. 1B is a cross-sectional view, FIG. 1C is a cross-sectional view, and FIG. 4D is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention; It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. 1A is a cross-sectional view and FIG. 2B is a cross-sectional view illustrating a method for manufacturing a semiconductor device in an embodiment of the present invention. It is (A) sectional drawing, (B) sectional drawing, (C) sectional drawing explaining the manufacturing method of the semiconductor device in conventional embodiment.

  The semiconductor device which is an embodiment of the present invention will be described below. FIG. 1A is a cross-sectional view illustrating a semiconductor device. FIG. 1B is a perspective view illustrating a semiconductor device. FIG. 2A is a perspective view illustrating a position accuracy confirmation mark. FIG. 2B is a plan view for explaining the scribe region. 3A to 3D are cross-sectional views illustrating a side surface (cut surface) of the semiconductor device.

  First, as shown in FIG. 1A, in the semiconductor device 1 having a WLP (Wafer Level Package) structure, a part of the scribe region W2 is arranged in a ring around the element formation region W1. This is because the width of the scribe region W2 (see FIG. 2B) is formed wider than the scribe blade 42 (see FIG. 7), and as described above, around the element formation region W1 after scribe. A part of the scribe area W2 is arranged. In the element formation region W1, although not shown, a semiconductor element such as a transistor is formed by the diffusion region. Although details will be described later, in the scribe region W2, the resin films 10 and 15 are arranged up to the package periphery, and the position accuracy confirmation mark 14 is exposed from the side surface.

  On the silicon substrate 2, an insulating layer 3 for insulation processing is formed. As the insulating layer 3, for example, at least one layer such as a silicon oxide film, an NSG (Nondoped Silicate Glass) film, a BPSG (Boron Phospho Silicate Glass) film, or the like is selected. The silicon substrate 2 may be a single crystal substrate or an epitaxial layer formed on the single crystal substrate. Further, a compound semiconductor substrate may be used instead of the silicon substrate 2.

  A wiring layer 4 is formed on the insulating layer 3. The wiring layer 4 has a three-layer structure, and a metal film is formed on the barrier metal film, and an antireflection film is formed on the metal film. The barrier metal film is made of a refractory metal such as titanium (Ti) or titanium nitride (TiN). The metal film is made of an alloy film mainly composed of Al, such as an aluminum (Al) film or an aluminum-silicon-copper (Al-Si-Cu) film. The antireflection film is made of a refractory metal such as TiN or titanium tungsten (TiW). And the film thickness of the wiring layer 4 is 0.4-3.0 micrometers, for example. The wiring layer 4 is electrically connected to a semiconductor element formed on the silicon substrate 2. The wiring layer 4 may be formed using copper as a main material.

  In the element formation region W1, the seal ring layer 5 is arranged in a ring shape on the outermost periphery of the element formation region W1, similarly to the scribe region W2. The seal ring layer 5 is formed by disposing a metal film 7 constituting the wiring layer 4 in and on the through hole 6 penetrating the insulating layer. The seal ring layer 5 prevents cracks from entering from the scribe region W2 to the element formation region W1 when the semiconductor wafer (not shown) is separated into individual semiconductor devices 1. Further, when the insulating layer 3 is rolled up at the time of cutting, the seal ring layer 5 prevents the rolling-up from proceeding to the element formation region W1.

  The shield layer 8 is formed on the insulating layer 3 including the wiring layer 4. The shield layer 8 is formed of a silicon nitride film, prevents moisture from entering the insulating layer 3, and prevents corrosion of the wiring layer 4 and the like. An opening region 9 is formed in the shield layer 8 on the wiring layer 4.

  The resin film 10 is formed on the upper surface of the shield layer 8 by, eg, spin coating. The resin film 10 is made of, for example, a polybenzoxazole (PBO) film or a polyimide resin film. The PBO film is a photosensitive resin and has characteristics such as high heat resistance, high mechanical characteristics, and low dielectric properties. Further, the PBO film prevents the semiconductor element from deteriorating from an external environment such as moisture and stabilizes the surface of the semiconductor element.

  An opening region 11 is formed in the resin film 10 on the wiring layer 4 and is formed inside the opening region 9. The plating metal layer 12 is arranged in a pattern on the resin film 10 including the inside of the opening region 11. The plating metal layer 12 is directly connected to the wiring layer 4 in the opening region 11.

  The plating metal layer 12 is formed by laminating two types of films. The first film is a refractory metal film, for example, a chromium (Cr) layer, a Ti layer, or a TiW layer, and is formed by a sputtering method. The first film is used as a seed layer when a plating layer is formed on the plating metal layer 12. Further, a Cu layer is formed on the first film as a second film by, for example, a sputtering method. The second film is used as a seed when a plating layer is formed on the plating metal layer 12.

  The Cu wiring layer 13 is formed on the upper surface of the plating metal layer 12 by, for example, electrolytic plating. The sheet resistance value of the Cu wiring layer 13 is about 2.0 μΩ · cm, and the sheet resistance value of the Al wiring layer is about 3.0 μΩ · cm. The wiring resistance value is reduced by using the Cu wiring layer 13. Furthermore, the film thickness of the Cu wiring layer 13 is, for example, 8.0 to 10.0 μm, and the wiring resistance value is also reduced by the film thickness.

  Then, the position accuracy confirmation mark 14 is formed from the element formation region W1 to the scribe region W2 side. Since the position accuracy confirmation mark 14 is formed in the process of forming the Cu wiring layer 13, for example, it is formed of a plating metal layer and a Cu plating layer.

  The resin film 15 is formed on the upper surface of the resin film 13 by, for example, a spin coat method. Similar to the resin film 10, the resin film 15 is made of, for example, a polybenzoxazole (PBO) film or a polyimide resin film.

  An opening region 16 is formed in the resin film 15 on the Cu wiring layer 13, and a bump electrode 17 is formed through the opening region 16. The bump electrode 17 has a structure in which, for example, an electroless plating layer such as Ni, Pd, or Au is disposed in the lower layer, and solder is laminated on the upper layer.

  Next, as shown in FIG. 1B, the side surfaces (cut surfaces) 18 and 19 of the semiconductor device 1 are located between the front surface 20 and the back surface 21 of the semiconductor device 1 and perpendicular to the front surface 20 and the back surface 21. It becomes a surface. Although details will be described later, since the resin films 10 and 15 cover the entire surface of the semiconductor wafer including the scribe region W2, from the side surfaces 18 and 19, the silicon substrate 2, the insulating layer 3, the shield layer 8, and the resin films 10 and 15 are covered. And the position accuracy confirmation mark 14 is exposed.

  As illustrated, the height T <b> 1 of the bump electrode 17 is, for example, 50 to 80 μm from the surface 20 of the semiconductor device 1. On the other hand, on the side surfaces 18 and 19 of the semiconductor device, a height T2 from the surface of the shield layer 8 to the surface 20 of the semiconductor device 1 is, for example, 30 to 50 μm. Therefore, as described above with reference to FIG. 9A, when the resin films 10 and 15 have a structure that does not cover the scribe region W2, recesses are formed on the side surfaces 18 and 19 of the semiconductor device. The height T3 is, for example, 80 to 130 μm. However, in the present embodiment, the resin films 10 and 15 are arranged up to the side surfaces 18 and 19, so that the step on the surface 20 side of the semiconductor device 1 is mainly the height T1 of the bump electrode 17, 50 to 80 μm.

  With this structure, the step on the surface 20 side of the semiconductor device 1 is reduced, and the back grinding process is performed in a state where the protective tape 44 (see FIG. 8A) is adhered and adhered to the surface 20 side. Further, it is possible to prevent the polishing scraps 22 of the silicon substrate 2 from reaching the surface 20 side of the semiconductor device 1. And although the grinding | polishing waste 22 is an electroconductive material, since it does not harden | cure the bump electrode 17 periphery, the electrical leak by the grinding | polishing waste 22 is prevented.

  Further, the position accuracy confirmation mark 14 is exposed on the side surfaces 18 and 19. And at the time of a back grinding process, treated water is supplied to a grinding | polishing surface etc., and the grinding | polishing waste 22 of the silicon substrate 2 is washed away. However, as shown in the drawing, the side surfaces 18 and 19 are in a state where some polishing scraps 22 are attached. Although details will be described later with reference to FIG. 3, the exposed surface of the position accuracy confirmation mark 14 is enlarged, and the visibility is improved, so that even if a small amount of polishing dust 22 is attached to the side surfaces 18, 19 It does not deteriorate the sex. That is, since the resin films 10 and 15 cover the scribe region W2, the position recognition accuracy of the alignment mark is slightly deteriorated. However, by exposing the position accuracy check marks 14 to the side surfaces 18 and 19, inspection of the position accuracy of the cut surface after scribing becomes possible, and product quality is not deteriorated.

  In FIG. 1B, the two side surfaces 18 and 19 of the semiconductor device 1 are shown. However, the semiconductor device 1 is, for example, a rectangular parallelepiped, and the other two side surfaces not shown are also the side surfaces 18 and 19. 19 is the same structure.

  Next, as shown in FIG. 2A, the position accuracy confirmation mark 14 is composed of, for example, four areas 23 to 26. The position accuracy confirmation mark 14 has, for example, a thickness T4 of 5 [mu] m, a width W3 of each of the areas 23 to 26 is 10 [mu] m, and a cut surface thereof is different depending on a cutting location. The area 23 is composed of a rectangular parallelepiped of X1 × W3 × T4, the area 24 is composed of a rectangular parallelepiped of X2 × W3 × T4, the area 25 is composed of a rectangular parallelepiped of X3 × W3 × T4, and the area 26 is X4 × It consists of a rectangular parallelepiped of W3 × T4. The position accuracy confirmation mark 14 has a shape in which one side of each of the areas 23 to 26 is aligned.

  Note that the thickness T4 and the width W3 of the position accuracy confirmation mark 14 can be arbitrarily changed according to the intended use. For example, the visibility is further improved by increasing the width W3 of the position accuracy confirmation mark 14. In addition, the number of areas of the position accuracy confirmation mark 14 can be arbitrarily changed depending on the intended use. For example, the positional accuracy confirmation mark 14 is composed of five or more areas, so that further positional accuracy is improved.

  Next, the area 23 is mainly disposed on the seal ring layer 5 (see FIG. 1), and when the area 23 is exposed on the side surface of the semiconductor device 1, the semiconductor device 1 is determined as a defective product. . On the other hand, the areas 24 to 26 are mainly arranged in the scribe region W2 (see FIG. 1), and when the areas 24 to 26 are exposed on the side surfaces of the semiconductor device 1, the semiconductor device 1 is determined as a non-defective product. The Further, the position accuracy confirmation mark 14 is formed in the same process as the Cu wiring layer 13, and the thickness of the Cu wiring layer 13 can be inspected by confirming the thickness T4 of the position accuracy confirmation mark 14.

  Even when all the areas 23 to 26 are not exposed on the side surface of the semiconductor device 1, only the scribe region W2 becomes wide, and it is determined as a non-defective product. Further, although the case where the four areas 23 to 26 of the position accuracy confirmation mark 14 are continuously formed has been described, the present invention is not limited to this case. For example, the four areas 23 to 26 may be arranged separately from each other.

  Next, in FIG. 2B, the solid line 27 is a region standardized as the outer shape of the semiconductor device 1. Depending on the scribing accuracy, the outer shape may shift inward or outward from the solid line 27 in some cases. A region surrounded by the dotted lines 28 and 29 is a region where the seal ring layer 5 is formed. In the adjacent semiconductor device 1, a region sandwiched between the dotted lines 28 is a scribe region W <b> 2 (see FIG. 1A). Then, for example, four position accuracy confirmation marks 14 are formed on each side of the semiconductor device 1 and are arranged from the seal ring 5 toward the scribe region W2. 3 shows the cut surfaces of the semiconductor device in FIG. 3. The position accuracy check marks 14 are inspected visually or with a microscope on the four cut surfaces of the semiconductor device 1 so that the cut surfaces are within the scribe region W2. It can be easily confirmed whether or not it is arranged at a suitable location.

  Next, a plurality of element formation regions W1 are arranged in a matrix on the wafer, and each element formation region W1 is surrounded by a scribe region W2 that runs in the vertical and horizontal directions of the wafer. The width of the scribe region W2 between the adjacent element formation regions 1 is, for example, 70 μm, and the line indicated by the alternate long and short dash line 30 is the center of the scribe region W2. Position recognition alignment marks 31 are arranged in regions where the four element formation regions W1 are adjacent to each other and the scribe regions W2 running vertically and horizontally intersect. The alignment mark 31 is formed using, for example, a wiring layer disposed in the insulating layer 3 (see FIG. 1A) or on the insulating layer 3, and is a mark for position recognition when performing a wiring pattern or scribe. Used as As described above, the two position accuracy confirmation marks 14 are arranged in the scribe region W2 so as to face each other with the center indicated by the alternate long and short dash line 30 therebetween. With this structure, the position accuracy confirmation marks 14 are exposed on the side surfaces of the semiconductor device 1 after scribing. Note that the position accuracy confirmation mark 14 does not necessarily have to be arranged facing the scribe region W2, and may be arranged only on one side. For example, when the position of each element formation region W1 in the wafer is coordinate-managed and the position determination of the position accuracy confirmation mark 14 in one adjacent element formation region W1 is determined to be non-defective, the other element formation region The determination of the scribe position of W1 is also determined as a non-defective product. As described above, the scribe region W2 is formed wider than the scribe blade 42 (see FIG. 7).

  3A shows a side surface (cut surface) 18 of the semiconductor device 1. From the side surface 18, the silicon substrate 2, the insulating layer 3, the shield layer 8, the resin films 10 and 15, and the positional accuracy confirmation. The mark 14 is exposed. Specifically, the area 18 of the position accuracy confirmation mark 14 having a width W3 and a thickness T4 is exposed slightly from the side surface 18 at the time of cutting. In this case, scribing is performed at and around the center of the scribe area W2 (see FIG. 2B), and it is determined as a non-defective product.

  Next, FIG. 3B shows a case where a region that is slightly displaced from the center of the scribe region W2 toward the element formation region W1 (see FIG. 2B) than the case of FIG. 3A is scribed. Specifically, from the side face 18, the areas 25 and 26 having a width W3 × 2 and a thickness T4 are exposed, although they are slightly slackened during cutting. In this case, scribing is performed within a suitable range in the scribe area W2, and it is determined that the product is non-defective.

  Next, FIG. 3C shows a case where a region that is slightly displaced from the center of the scribe region W2 to the element formation region W1 (see FIG. 2B) side than the case of FIG. 3B is scribed. Specifically, from the side surface 18, the area 24 to 26 having a width W3 × 3 and a thickness T4 is exposed, although it is slightly slackened during cutting. In this case, scribing is performed within a suitable range in the scribe area W2, and it is determined that the product is non-defective.

  Next, FIG. 3D shows a case where the element forming region W1 where the seal ring layer 5 is disposed is scribed. Specifically, from the side face 18, the area 23 to 26 having a width W3 × 4 and a thickness T4 is exposed, although it is slightly slackened during cutting. Further, the seal ring layer 5 is exposed from the side surface 18 below the areas 23 to 26. In this case, first, the seal ring layer 5 exposed from the side surface 18 is easily corroded by moisture. Further, moisture enters the semiconductor device 1 from the interface between the seal ring layer 5 and the shield layer 8 to corrode the wiring layer 4 (see FIG. 1A), the Cu wiring layer 13 (see FIG. 1A), and the like. . That is, since the product quality deteriorates when the seal ring layer 5 is exposed from the side surface 18, it is determined as a defective product. The position accuracy confirmation mark 14 and the seal ring layer 5 do not necessarily have to be associated with each other. For example, when the area 23 is exposed from the cut surface, it may be determined as a defective product.

  As shown in FIGS. 3A to 3C, also in the present embodiment, the position accuracy confirmation mark 14 formed from, for example, a Cu plating layer is used as the side surface 18 of the semiconductor device 1 in the same manner as in the prior art. Exposed from. However, the position accuracy confirmation mark 14 is not formed continuously with the Cu wiring layer 13, and even when the position accuracy confirmation mark 14 is oxidized, the Cu wiring layer 13 is not oxidized. Further, since the position accuracy confirmation mark 14 is covered with the resin films 10 and 15 having excellent moisture resistance, even when moisture enters from the interface of the position accuracy confirmation mark 14, only the periphery of the position accuracy confirmation mark 14 is obtained. The wiring layer 4 and the like are not corroded.

  In this embodiment, the semiconductor device having the WLP structure has been described. However, the present invention is not limited to this case. For example, even in a MAP (Mold Array Package) structure, the same effect can be obtained by arranging the position accuracy confirmation mark 14 in the scribe region. In addition, various modifications can be made without departing from the scope of the present invention.

  Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 4 to 8 are cross-sectional views illustrating a method for manufacturing a semiconductor device in the present embodiment. In the present embodiment, the same reference numerals are assigned to the same constituent members in order to describe the manufacturing method of the structure shown in FIG.

  First, as shown in FIG. 4, a silicon substrate (semiconductor wafer) 2 is prepared, and an insulating layer 3 is formed on the silicon substrate 2. In the silicon substrate 2 (including an epitaxial layer when an epitaxial layer is formed), a semiconductor element is formed by a diffusion region. As the insulating layer 3, at least one layer such as a silicon oxide film, an NSG film, and a BPSG film is selected.

  Next, the wiring layer 4 is formed on the insulating layer 3, and the seal ring layer 5 is formed on the insulating layer 3. Specifically, a barrier metal film, a metal film, and an antireflection film are stacked on the silicon substrate 2 by, for example, a sputtering method. Thereafter, the above-described barrier metal film, metal film, and antireflection film are patterned to form the wiring layer 4. Further, in the element formation region W1 in the vicinity of the scribe region W2, the through hole 6 penetrating the insulating layer 3 is formed and buried with the above-described barrier metal film, metal film, and antireflection film, and the seal ring layer 5 is formed.

  Next, the shield layer 8 is formed on the upper surface of the insulating layer 3. As the shield layer 8, for example, a silicon nitride film is deposited to about 3000 to 10,000 kg. Thereafter, the silicon nitride film is patterned to form an opening region 9.

  Next, as shown in FIG. 5, the resin film 10 is formed on the upper surface of the shield layer 8 by, for example, spin coating. As a material, a PBO film, a polyimide resin film, or the like is used. And the resin film 10 is patterned and the opening area | region 11 is formed. At this time, the scribe region W2 also remains in the state of covering the resin film 10.

  Next, a plating metal layer 12 is formed on the upper surface of the resin film 10 by, for example, a sputtering method. As described above, a Ti layer and a Cu layer are deposited as the plating metal layer 12. Thereafter, a photoresist layer (not shown) is formed in a portion excluding the formation region of the Cu wiring layer 13 and the position accuracy confirmation mark 14. Then, using the photoresist layer as a mask, the Cu wiring layer 13 and the position accuracy confirmation mark 14 are formed by electrolytic plating. Thereafter, the photoresist layer is removed, and the plating metal layer 12 is selectively removed by wet etching using the Cu wiring layer 13 and the position accuracy confirmation mark 14 as a mask.

  Next, as shown in FIG. 6, a resin film 15 is formed on the upper surface of the resin film 10 by, for example, a spin coating method. As a material, a PBO film, a polyimide resin film, or the like is used. And the resin film 15 is patterned and the opening area | region 16 is formed. At this time, the scribe region W2 also remains in the state of covering the resin film 15. Thereafter, a bump electrode 17 is formed on the Cu wiring layer 13 exposed from the opening region 16. As the bump electrode 17, for example, an electroless plating layer of Ni, Pd, Au or the like is formed in the lower layer, and solder is formed in the upper layer.

  Next, as shown in FIG. 7, for example, the periphery of the adhesive sheet 41 is fixed with a stainless steel ring-shaped metal frame (not shown), and the silicon substrate 2 (semiconductor wafer) side is attached to the upper surface of the adhesive sheet 41. Then, install the metal frame on the scribing device. Then, after the position of the scribe region W2 of the silicon substrate 2 is recognized using the alignment mark 31 (see FIG. 2B), the scribe region W2 is cut using the scribe blade 42, and a groove 43 that does not penetrate the silicon substrate 2 is formed. Form. At this time, the depth of the groove 43 is such that the silicon substrate 2 is separated into pieces in the next back grinding process. Thereafter, the metal frame is removed from the scribing device, and the silicon substrate 2 is peeled from the adhesive sheet 41.

  Next, as shown in FIG. 8A, the periphery of the protective tape 44 is fixed with a metal frame (not shown), and the resin film 15 side on which the bump electrode 17 is disposed is attached to the upper surface of the protective tape, and the metal The frame is placed on the table 45 of the back grinding apparatus. Then, while supplying treated water to the back surface side of the silicon substrate 2 (semiconductor wafer), the back grinding wheel 46 is rotated to polish the back surface side of the silicon substrate 2. Then, the silicon substrate 2 is polished until a desired film thickness is obtained, and the silicon substrate 2 is polished up to the formation region of the groove 43, whereby individual semiconductor devices are obtained. At this time, the polishing dust 22 adhering to the side surface of the groove 43 is washed away. Thereafter, the metal frame is removed from the back grind device to remove water adhering to the silicon substrate 2 and the like, and then the separated semiconductor device is peeled off from the protective tape 44.

  FIG. 8B is an enlarged cross-sectional view of a region indicated by a circle 47 in FIG. As the protective tape 44, for example, an adhesive layer 49 of about 3 μm is provided on the entire surface of a sheet 48 made of a PET material that has a high breaking strength and does not easily expand and contract. On the other hand, the width W4 of the groove 43 is equal to the width of the scribe blade 42 (see FIG. 7), and is, for example, about 50 μm. And the corner part 50 of the resin film 15 becomes substantially right-angled by being cut by the scribe blade 42.

  With this structure, the surface side of the resin film 15 is substantially flat except for the region where the bump electrode 17 is formed, so that the resin film 15 can be in close contact with the adhesive layer 49. The substantially entire surface of the resin film 15 enters the adhesive layer 49, and the adhesive layer 49 enters the groove 43. At this time, the adhesive layer 49 is in close contact with the side surface of the groove 43 in the vicinity of the corner portion 50, and the adhesive layer 49 enters the groove 43 so as to rise slightly. As a result, the polishing debris 22 adheres to the upper surface of the adhesive layer 49 in the groove 43, but prevents the polishing debris 22 from reaching the surface of the resin film 15 due to the adhesive state of the adhesive layer 49 in the vicinity of the corner portion 50. it can.

  Furthermore, in this embodiment, the step of expanding the adhesive layer 49 as before is not required. As a result, manufacturing costs can be suppressed. Further, in the conventional technique, when the adhesive 56 (see FIG. 9B) expands unevenly or its adhesiveness deteriorates, the polishing dust 57 (see FIG. 9B) is completely removed. As a result, the product quality was likely to vary. However, in the present embodiment, it is possible to prevent variations in product quality by preventing the polishing debris 22 from entering the surface of the resin film 15 in advance during the back grinding process.

  Finally, as described above with reference to FIGS. 3A to 3D, the scribe region is inspected by the position accuracy confirmation mark 14 exposed on the side surface (cut surface) of the separated semiconductor device 1, The semiconductor device 1 determined to be non-defective is packaged and delivered.

  In the present embodiment, the position accuracy confirmation mark 14 is formed in the same process when forming the Cu wiring layer 13 to reduce the manufacturing cost. However, the present invention is not limited to this case. . For example, the position accuracy confirmation mark 14 may be formed by electrolytic plating in a separate process, or may be formed by depositing a metal film by sputtering and etching. In other words, the position accuracy confirmation mark 14 formed of a material that can hardly be cut off when the scribing is performed and whose shape can be confirmed visually or with a microscope may be used. In addition, various modifications can be made without departing from the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 5 Seal ring layer 10 Resin film 13 Cu wiring layer 14 Position accuracy confirmation mark 15 Resin film

Claims (7)

In a semiconductor device in which at least one main surface side of a substrate is covered with a resin layer, an electrode is formed on the resin layer surface side, and a side surface located between one main surface and another main surface of the substrate is a scribe surface ,
At least the resin layer and the substrate are exposed on the side surface, and the resin layer exposed on the side surface is a flat surface perpendicular to the surface of the resin layer. A position accuracy confirmation mark for confirming the position accuracy of the scribe surface is exposed on the side surface, the substrate is polished from the other main surface side, and a part of the polishing debris generated by the polishing is The semiconductor device according to claim 1, wherein the semiconductor device adheres to the substrate. 3. The semiconductor device according to claim 2, wherein a seal ring layer is formed in a ring shape on the substrate, and the position accuracy confirmation mark is disposed between the side surface from above the seal ring layer. . 4. The semiconductor device according to claim 2, wherein the position accuracy confirmation mark has a staircase shape, and an area exposed from the side surface differs according to the scrubbing surface. A step of preparing a semiconductor wafer, forming semiconductor elements in a plurality of element forming regions of the semiconductor wafer, forming a resin layer on one main surface side of the semiconductor wafer, and then forming an electrode on the surface side of the resin layer When,
After forming a groove reaching the semiconductor wafer from the resin layer along the scribe region of the semiconductor wafer, bonding a protective tape to the surface side of the resin layer;
Polishing the semiconductor wafer from the other main surface side of the semiconductor wafer to at least the groove forming region, singulating the semiconductor wafer for each element forming region, and forming a semiconductor device;
The resin layer is exposed from the side surface of the groove, and a part of the adhesive layer constituting the protective tape is inserted into the groove so as to contact the exposed resin layer. A method for manufacturing a semiconductor device, comprising performing a polishing step. Forming a position accuracy confirmation mark disposed at least in the scribe region in the resin layer,
When forming the groove, the position accuracy confirmation mark is exposed from the groove side surface, the position accuracy confirmation mark exposed from the separated semiconductor device is confirmed, and the suitability of the scribe surface of the semiconductor device is determined. 6. A method of manufacturing a semiconductor device according to claim 5, wherein: The method for manufacturing a semiconductor device according to claim 5, wherein the resin layer is formed by spin coating, and is formed on an entire main surface of the semiconductor wafer including the scribe region. .

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