TWI433225B - Wafer structure and wafer treatment method - Google Patents

Description

Wafer structure and wafer processing method

The present invention relates to a wafer structure and a wafer processing method thereof, and more particularly to a wafer for avoiding damage to a wafer caused by a residue generated by a test or alignment metal pad during a dicing process. Structure and its processing methods.

Under the development of the integrated circuit, the back-end process of the integrated circuit also plays a very important role. Usually, when the integrated circuit layout of each die on the wafer is completed, the wafer is cut by the downstream packaging factory, and the wafer cutting process has a decisive influence on the working efficiency and yield of the die.

Specifically, the plurality of dies on the wafer are arranged in an array, and adjacent regions between the dies define a scribe line, and the scribe lines are provided with metal pads for Test the electrical properties of each layer of wiring or the alignment of the layers. Since the metal pads are made of a metal material, and the base material of the wafer is 矽, the flexibility of the two materials is greatly different, so when cutting a plurality of dies from the scribe line of the wafer, The problem of metal residue or scum splashing.

The splashed metal residue or slag may fall onto the die of the finished circuit layout, making the crystals splashed with the metal residue easy to be in the subsequent packaging process, causing leakage current or short circuit; The stress caused by splashing metal residue or slag falling on the die is too large, causing scratches on the grain surface and the protective layer, and causing electrical abnormalities and the like, which seriously affect the grain yield. In addition, if the width of the cutting blade is smaller than the width of the metal pad, some metal pad remains after cutting, and the residual metal pad may be flipped up to contact adjacent crystal grains. This will affect subsequent packaging and cause electrical shorts. Moreover, in order to increase the number of crystal grains available on the wafer, it is often possible to reduce the width of the scribe line as much as possible, thereby arranging more crystal grains. When the width of the scribe line is reduced to 60 to 65 microns or less, cutting the wafer is liable to cause a risk of chip cracking.

In view of this, how to avoid the generation of residue during the process of cutting the wafer, damage or short circuit the crystal on the completed circuit layout of the wafer, and improve the yield of the crystal is an issue that the industry is paying more and more attention to. .

An object of the present invention is to provide a wafer structure comprising a plurality of crystal grains, a plurality of metal pads, a protective layer and an insulating layer. The crystal grains are arranged in an array, and adjacent regions between the crystal grains are defined as a dicing street. The metal pad is formed on the dicing street, and the protective layer is formed on the dies and the dicing street and covers the metal pad. The insulating layer is formed on the dicing street. The protective layer is covered and at least partially covered with a metal pad.

Another object of the present invention is to provide a wafer processing method comprising the steps of: (a) providing a wafer having a plurality of crystal grains arranged in an array, wherein adjacent regions between the crystal grains are defined as a cutting track having a plurality of metal pads thereon, and the die and the cutting track are formed with a protective layer to cover the metal pads; (b) forming an insulating layer on the protective layer of the cutting track, the insulating layer At least partially covering the metal pad; (c) cutting the wafer along the scribe line to form a plurality of individual dies and at least partially removing the metal pad.

It is still another object of the present invention to provide another wafer structure including a plurality of crystal grains, a plurality of metal pads, a protective layer, and an insulating layer. The grains are arranged in an array, and adjacent regions between the grains are defined as a dicing street, from one surface of the scribe line to each crystal One of the side surfaces of each of the grains between the upper surfaces of the grains defines a vertical wall. A metal pad is formed on the scribe line, and a protective layer is formed on the dies and the scribe line and covers the metal pad. The insulating layer is formed on the protective layer of the scribe line, and the insulating layer is located between the metal pad and the die and covers at least the vertical walls of the dies.

It is still another object of the present invention to provide another wafer processing method comprising the steps of: (a) providing a wafer having a plurality of crystal grains arranged in an array, and defining adjacent regions between the crystal grains a dicing street defining a vertical wall from a surface of one of the dicing streets to a side surface of each of the grains between the upper surfaces of the dies, the dicing street having a plurality of metal pads, and the dies Forming a protective layer on the scribe line to cover the metal pads; (b) forming an insulating layer on the protective layer of the scribe line, the insulating layer is between the metal pad and the die, and covering at least the vertical wall of each die; (c) cutting the wafer along the scribe line to form a plurality of individual dies and at least partially removing the metal pads.

In summary, the wafer structure and the wafer processing method of the present invention cover the metal pad with an insulating layer, thereby avoiding the metal pad remaining after the wafer is flipped and flipped to contact the die, and also reducing any metal or The ruthenium residue splashes onto the die to damage or short-circuit the die of the completed circuit layout, or cover the side of the die with an insulating layer, so that even if the residual metal pad is turned over to contact the die, the insulating layer can be used. Preventing the occurrence of short circuits or leakage currents can improve the yield of the crystal grains. Moreover, the various wafer structures and wafer processing methods of the present invention can also be applied to narrower scribe lines for wafer dicing.

Other objects, advantages, and technical means and embodiments of the present invention will become apparent to those skilled in the <RTIgt;

The present invention will be explained by the following embodiments, however, the description of the embodiments is only intended to illustrate the technical content of the present invention, and is not intended to limit the present invention. It should be noted that in the following embodiments and drawings, elements that are not directly related to the present invention have been omitted and are not shown; and the dimensional relationship between the elements in the drawings is only for easy understanding, and is not intended to limit the actual ratio. .

1 is a top view of a wafer structure 1 according to a first embodiment of the present invention. In this embodiment, the wafer structure 1 is a wafer. The wafer structure 1 includes a plurality of dies 10, a plurality of metal pads 14, a protective layer 21, and an insulating layer 23. The crystal grains 10 are arranged in an array, and the adjacent regions between the crystal grains 10 are defined as a dicing street 12, wherein the crystal grains 10 are formed into a specific circuit layout through a plurality of processes, and a plurality of solder pads are formed (not shown) As shown, an electrical connection component, such as bumps 11, can be formed on the pad to electrically connect the die 10 to other components, such as a substrate. It will be appreciated by those skilled in the art that the number of dies and dicing streets shown in Figure 1 is merely illustrative of the invention and is not intended to limit the invention.

The metal pad 14 is formed on the dicing street 12, and the metal pad 14 is a test pad 141 or a pair of locating pads 143. The top surface of the test pad 141 is a rectangle, and the shape of the alignment pad 143 is ten. Glyph. The shape of the test pad 141 and the alignment pad 143 are not limited to the present invention. In addition, the test pad 141 and the alignment pad 143 in this embodiment are not limited to the positions of the above-mentioned top view and cross-sectional view; Those skilled in the art should be able to easily push other implementations. For the sake of explanation, only a part of the crystal grains 10a, 10b, 10c, 10d and their adjacent region portions in the crystal grains 10 will be explained below.

2 is a partial top view of the wafer structure 1 of the first embodiment of the present invention, illustrating the dicing streets 12, the metal pads 14, and the protective layer 21 of the dies 10a, 10b, 10c, 10d and their adjacent regions. And an insulating layer 23. 3 is a longitudinal cross-sectional view of the wafer structure 1 of the first embodiment of the present invention, and is a longitudinal cross-sectional view taken in the direction of the arrow after being sectioned along the line segment AB in FIG.

Referring to FIGS. 2 and 3, the protective layer 21 is formed on and around the crystal grains 10a, 10b, 10c, and 10d, and only partially exposes the pads 15 on the crystal grains 10a, 10b, 10c, and 10d. The bump 11 is formed over the partially exposed pad 15 and the protective layer 21. The protective layer 21 is formed on the scribe lines 12 between the dies 10a, 10b, 10c, 10d to cover the metal pads 14 on the scribe lines 12. The insulating layer 23 extends along the dicing street 12 and is formed on the protective layer 21 of the dicing street 12 and completely covers the metal pads 14.

In more detail, the test pad 141 is disposed in the dicing street 12 shown in FIG. 3, and the dies 10b and 10c are formed on both sides, and the bumps 11 are formed on the dies 10b and 10c for electrically connecting the die 10b. , 10c and other components. A protective layer 21 is formed over the test pad 141 to completely cover the test pad 141, and the protective layer 21 also covers the crystal grains 10b, 10c. The insulating layer 23 is formed over the protective layer 21 of the dicing street 12 and completely covers the test pad 141. The detailed structure of the crystal grains on both sides of the dicing street 12 is not an important technical feature of the present invention, and therefore will not be further described herein.

As described above, the thickness of the insulating layer 23 is not less than 1.5 times the thickness of the protective layer 21, wherein the protective layer 21 is the last process in the fabrication of the wafer, usually by tantalum nitride (SixNx) and/or yttrium oxide. A passivation layer of (SiOx) to prevent intrusion of moisture. The insulating layer 23 is composed of polyimide (PI), benzocyclobutene. (Benzocyclobutene, BCB) and one of polyquinol (Polyquinolin), and the insulating layer 23 is formed by spin coating, printing or attaching a dry film. The dry film is a preformed film. The metal pads 14 are formed simultaneously with the routing lines in the die 10 for testing the electrical properties of the various layers of wiring or for alignment during wafer fabrication. The metal pads 14 may be selected from copper, aluminum or other metal materials.

Please refer to FIG. 4, which is a flowchart of a wafer processing method applied to the wafer structure 1 of the first embodiment of the present invention. The wafer processing method comprises the following steps: First, in step S101, a wafer is provided, the wafer has a plurality of crystal grains, and the crystal grains are arranged in an array, and adjacent regions between the crystal grains are defined as one The cutting track has a plurality of metal pads on the cutting track, and a protective layer is formed on the die and the cutting track to cover the metal pads. In step S107, an insulating layer is formed on the protective layer of the dicing street, and the insulating layer extends along the scribe line and completely covers the metal pads, wherein the thickness of the insulating layer is not less than 1.5 times the thickness of the protective layer, and is formed. The step of insulating the layer is formed by a spin coating method, a printing method, or a dry film method, wherein the dry film is a preformed film. Up to the above completion steps, the wafer structure 1 described in the first embodiment is obtained. Finally, in step S115, the wafer is diced along the scribe line to form a plurality of individual dies, and the metal pads are at least partially removed.

Please refer to FIG. 5, which is a partial top view of the wafer structure of the second embodiment of the present invention. The wafer structure of the second embodiment is substantially the same as the wafer structure 1 of the first embodiment. The difference is that the insulating layer 23 is not elongated, but includes a plurality of insulating blocks 23a, 23b, 23c, 23d, 23e, and completely covers the metal pads respectively. 14. Specifically, the insulating blocks 23a, 23b, 23c, 23d, and 23e are formed on the metal pads 14 by patterning. Since the wafer structure of the second embodiment has a cross section of the same position as that of the first embodiment, the longitudinal cross-sectional views of the wafer are completely the same, and thus will not be further described herein.

Please refer to FIG. 6 , which is a flowchart of a wafer processing method for a wafer structure according to a second embodiment of the present invention. The wafer processing method is substantially the same as the wafer processing method of the first embodiment. The difference is that the step S107 of the wafer processing method of the first embodiment is replaced by performing step S109, forming an insulating layer on the protective layer of the dicing street, and patterning a plurality of insulating blocks to completely cover the insulating layer. Metal pad. The other processing steps S101 and S115 are the same as the first embodiment wafer processing method, and therefore will not be further described herein.

Please refer to FIG. 7, which is a partial top view of the wafer structure of the third embodiment of the present invention. The wafer structure of the third embodiment is substantially the same as the wafer structure of the first embodiment. The difference is that the insulating layer 23 extends along the dicing street 12 and covers the opposite sides of the metal pads 14; in other words, the intermediate portions of the metal pads 14 are not covered by the insulating layer 23. To disclose the wafer structure of this embodiment in more detail, please refer to Figure 7 and refer to Figure 8.

Fig. 8 is a longitudinal sectional view showing a wafer structure according to a third embodiment of the present invention, and is a longitudinal sectional view taken in the direction of the arrow after a section CD along the line segment in Fig. 7. It can be seen from FIG. 8 that a test pad 141 is disposed in the scribe line 12 on the wafer structure, and the dies 10b and 10c are formed on both sides, and bumps 11 are formed on the dies 10b and 10c for electrically connecting the dies. 10b, 10c and other components. A protective layer 21 is formed over the test pad 141 to completely cover the test pad 141, and the protective layer 21 also covers the die 10b, 10c. However, unlike FIG. 3, although the insulating layer 23 is formed on the protective layer 21, only the metal pads 14 are partially covered, that is, the insulating layer 23 covers only the opposite sides of the metal pads 14. The detailed structure of the crystal grains on both sides of the dicing street 12 is not an important technical feature of the present invention, and therefore will not be further described herein.

Please refer to FIG. 9 , which is a flowchart of a wafer processing method for a wafer structure according to a third embodiment of the present invention. The wafer processing method is substantially the same as the wafer processing method of the first embodiment. The difference is that step S107 of the wafer processing method of the first embodiment is replaced by performing step S111 to form an insulating layer on the protective layer of the dicing street, and the insulating layer extends along the dicing street and covers the metal pads. Relative to the two sides. The other processing steps S101 and S115 are the same as the first embodiment wafer processing method, and therefore will not be further described herein.

Please refer to FIG. 10, which is a partial top view of the wafer structure of the fourth embodiment of the present invention. The wafer structure of the fourth embodiment is substantially the same as that of the first embodiment. The difference is that the insulating layer 23 is not elongated, but includes a plurality of insulating blocks 23a, 23b, 23c, 23d, 23e, and is formed along one extending direction of the parallel cutting track 12, and the insulating layer 23 is respectively Covering the opposite sides of the metal pads 14. Specifically, the insulating blocks 23a, 23b, 23c, 23d, and 23e are formed on the metal pads 14 by patterning. Since the wafer structure of the fourth embodiment is sectioned in the same position as the line segment of the third embodiment, the longitudinal cross-sectional views of the wafer are completely the same, and thus will not be further described herein.

Please refer to FIG. 11 , which is a flowchart of a wafer processing method for a wafer structure according to a fourth embodiment of the present invention. The wafer processing method is substantially the same as the wafer processing method of the first embodiment. The only difference is that step S107 of the wafer processing method of the first embodiment And replacing with the step S113, forming an insulating layer on the protective layer of the dicing street, the insulating layer is patterned along the extending direction of one of the parallel dicing streets to form a plurality of insulating blocks, thereby covering the opposite sides of the metal pads . The other processing steps S101 and S115 are the same as the first embodiment wafer processing method, and therefore will not be further described herein.

Please refer to FIG. 12, which is a partial top view of the wafer structure of the fifth embodiment of the present invention. The wafer structure of the fifth embodiment comprises a plurality of crystal grains, a plurality of metal pads 14, a protective layer 21 and an insulating layer 23. The plurality of crystal grains include the crystal grains 10a, 10b, 10c, and 10d. However, the present embodiment only partially illustrates the crystal grains 10a, 10b, 10c, and 10d and their adjacent regions. It should be noted that the foregoing crystal grains and The number of metal pads is merely illustrative of the invention and is not intended to limit the invention.

Similar to the foregoing embodiments, the crystal grains 10a, 10b, 10c, and 10d are also arranged in an array, and adjacent regions between the crystal grains 10a, 10b, 10c, and 10d are defined as a dicing street 12 in which the crystal grains 10 are A specific circuit layout is formed by multiple processes, and a plurality of pads (not shown) are formed, and electrical connection elements, such as bumps 11, can be formed on the pads to electrically connect the die 10 and other components. , for example, a substrate.

The metal pad 14 is formed on the dicing street 12, and the metal pad 14 is a test pad 141 or a pair of locating pads 143. The protective layer 21 is formed on and around the crystal grains 10a, 10b, 10c, and 10d, and only partially exposes the pads 15 on the crystal grains 10a, 10b, 10c, and 10d, so that the bumps 11 are formed in the partially exposed solder. Above the pad 15 and the protective layer 21. The protective layer 21 is formed on the scribe lines 12 between the dies 10a, 10b, 10c, 10d to cover the metal pads 14 on the scribe lines 12. The insulating layer 23 is formed on the portion of the protective layer 21 of the dicing street 12.

It should be noted that the fifth embodiment is different from the foregoing embodiment in that the fifth embodiment The insulating layer 23 of the embodiment is located between the metal pads 14 and the crystal grains 10a, 10b, 10c, and 10d, and the insulating layer 23 of the foregoing embodiment at least partially covers the metal pads 14. For example, when the fifth embodiment is implemented, the insulating layer 23 may be formed around the partial crystal grains 10b, 10c, and the other portions of the crystal grains 10a, 10d may be adjacent to the crystal grains 10a, 10d and the metal pad 14. An insulating layer 23 is formed. The formation position of the foregoing insulating layer 23 is for illustrative purposes only, and those skilled in the art should be able to push and completely surround the die with an insulating layer, completely form an insulating layer by using adjacent sides of the die and the metal pad, or combine the above implementations. The example forms the implementation of the position.

Figure 13 is a longitudinal cross-sectional view showing a wafer structure according to a fifth embodiment of the present invention, and is a cross-sectional view taken along the line EF of Fig. 12 and viewed in the direction of the arrow. As shown in FIG. 13, a test pad 141 is disposed in the dicing street 12 on the wafer structure, and the dies 10b and 10c are formed on both sides, and bumps 11 are formed on the dies 10b and 10c for electrically connecting the dies. 10b, 10c and other components. A protective layer 21 is formed over the test pad 141 to completely cover the test pad 141, and the protective layer 21 also covers the crystal grains 10b, 10c.

However, the fifth embodiment differs from the first to fourth embodiments in that a surface of one of the crystal grains is defined by a surface from one surface of the scribe line 12 to an upper surface of each of the crystal grains 10b, 10c. The wall 81, and the insulating layer 23 covers at least the vertical walls 81 of the respective crystal grains 10b, 10c. The above description is not limited to only the vertical walls 81 defined by the respective crystal grains 10b, 10c. It should be understood by those skilled in the art that the vertical wall 81 can be deduced to the crystal when implemented as in the fifth embodiment. All or part of the grain on the circle. The detailed structure of the crystal grains on both sides of the dicing street 12 is not an important technical feature of the present invention, and therefore will not be further described herein.

As described above, the thickness of the insulating layer 23 is not less than 1.5 times the thickness of the protective layer 21, wherein the protective layer 21 is the last process in the fabrication of the wafer, usually by tantalum nitride (SixNx) and/or yttrium oxide. A passivation layer of (SiOx) to prevent intrusion of moisture. The insulating layer 23 is made of one of polyimide (PI), Benzocyclobutene (BCB) and Polyquinolin, and the insulating layer 23 is spin-coated ( It is formed by spin coating, printing or attaching a dry film, wherein the dry film is a preformed film. The metal pads 14 are formed simultaneously with the routing lines in the die 10 for testing the electrical properties of the various layers of wiring or for alignment during wafer fabrication. The metal pads 14 may be selected from copper, aluminum or other metal materials.

Figure 14 is a flow chart of a wafer processing method applied to a wafer structure of a fifth embodiment of the present invention. The wafer processing method comprises the following steps. First, in step S201, a wafer is provided, the wafer has a plurality of crystal grains, and the crystal grains are arranged in an array, and adjacent regions between the crystal grains are defined as one cut. a side wall defining a vertical wall from one surface of the cutting path to one of the upper surfaces of each of the crystal grains, wherein the cutting track has a plurality of metal pads, and the die and the cutting track are formed A protective layer covers the metal pads. In step S207, an insulating layer is formed on the protective layer of the dicing street, and the insulating layer is located between the metal pad and the die and covers at least the vertical wall of each die. An insulating layer between the metal pad and the die may be formed around the four sides of each of the dies, or may be formed only on one side of each of the dies adjacent to the metal pad. In addition, it should be noted that the thickness of one of the insulating layers is not less than 1.5 times the thickness of one of the protective layers, and the step of forming the insulating layer is performed by a spin coating method, a printing method, or a dry film. Formed by a dry film method in which the dry film is a preformed film. Up to the above completion steps, the wafer structure described in the fifth embodiment is obtained. At last, In step S209, the wafer is diced along the scribe line to form a plurality of individual dies, and the metal pads are at least partially removed.

In summary, the wafer structure and the wafer processing method disclosed in the present invention can cover the metal pad by the insulating layer, thereby avoiding the metal pad remaining after the wafer is flipped and flipped to contact the die, and can also reduce any The metal or ruthenium residue splashes onto the die to damage or short-circuit the die of the completed circuit layout, or cover the side of the die with an insulating layer, so that even if the residual metal pad is turned over to contact the die, the insulation may be insulated. The layer prevents the occurrence of short circuits or leakage currents, so that the grain yield can be improved.

The above-described embodiments are only intended to illustrate the embodiments of the present invention, and to explain the technical features of the present invention, and are not intended to limit the scope of the present invention. Any changes or equivalents that can be easily made by those skilled in the art are within the scope of the invention, and the scope of the invention should be determined by the scope of the claims.

1‧‧‧ Wafer structure

10‧‧‧ grain

10a, 10b, 10c, 10d‧‧‧ grain

11‧‧‧Bumps

12‧‧‧ cutting road

14‧‧‧Metal pad

141‧‧‧Test pad

143‧‧‧ alignment pad

15‧‧‧ solder pads

21‧‧‧Protective layer

23‧‧‧Insulation

23a, 23b, 23c, 23d, 23e‧‧‧ insulating blocks

81‧‧‧ vertical wall

1 is a top view of a wafer structure according to a first embodiment of the present invention; FIG. 2 is a partial top view of a wafer structure according to a first embodiment of the present invention; and FIG. 3 is a section along line AB of FIG. FIG. 4 is a flow chart of a wafer processing method according to a first embodiment of the present invention; FIG. 5 is a partial top view of a wafer structure according to a second embodiment of the present invention; A flow chart of a wafer processing method according to a second embodiment of the present invention; FIG. 7 is a partial top view of a wafer structure according to a third embodiment of the present invention; and FIG. 8 is a longitudinal sectional view taken along line CD of the seventh line segment; 9 is a flow chart of a wafer processing method according to a third embodiment of the present invention; FIG. 10 is a partial top view of a wafer structure according to a fourth embodiment of the present invention; 11 is a flow chart of a wafer processing method according to a fourth embodiment of the present invention; FIG. 12 is a partial top view of a wafer structure according to a fifth embodiment of the present invention; and FIG. 13 is a EF section along a line 12 of FIG. A longitudinal sectional view; and a 14th drawing is a flow chart of a wafer processing method according to a fifth embodiment of the present invention.

10b, 10c‧‧‧ grain

11‧‧‧Bumps

12‧‧‧ cutting road

141‧‧‧Test pad

15‧‧‧ solder pads

21‧‧‧Protective layer

23‧‧‧Insulation

Claims (26)

A wafer structure comprising: a plurality of dies arranged in an array, wherein adjacent regions between the dies are defined as a scribe line; a plurality of metal pads are formed on the scribe line; a protective layer formed on the dies and the scribe lines and covering the metal pads; and an insulating layer formed on the protective layer of the scribe lines and at least partially covering the metal pads. The wafer structure of claim 1, wherein the insulating layer extends along the scribe line and completely covers the metal pads. The wafer structure of claim 1, wherein the insulating layer extends along the scribe line and covers opposite sides of the metal pads. The wafer structure of claim 1, wherein the insulating layer comprises a plurality of insulating blocks and completely covers the metal pads. The wafer structure of claim 1, wherein the insulating layer comprises a plurality of insulating blocks and is formed in a direction parallel to one of the dicing streets, and the insulating layer covers opposite sides of the metal pads. The wafer structure of claim 1, wherein one of the insulating layers has a thickness of not less than 1.5 times a thickness of one of the protective layers. The wafer structure according to claim 1, wherein the insulating layer is made of one of polyimide (PI), Benzocyclobutene (BCB) and Polyquinolin. . The wafer structure of claim 1, wherein the metal pad is a test pad and One of the pair of cushions. The wafer structure of claim 1, wherein the insulating layer is formed by spin coating, printing, or attaching a dry film. A wafer structure comprising: a plurality of crystal grains arranged in an array, wherein adjacent regions between the crystal grains are defined as a dicing street from a surface of the dicing street to an upper surface of each of the dies One side surface of each of the crystal grains defines a vertical wall; a plurality of metal pads are formed on the cutting track; a protective layer is formed on the crystal grains and the cutting track, and covers the metal pads; An insulating layer is formed on the protective layer of the dicing pad, the insulating layer is located between the metal pads and the dies, and covers at least the vertical walls of each of the dies. The wafer structure of claim 10, wherein the insulating layer is formed around four sides of each of the crystal grains. The wafer structure of claim 10, wherein one of the insulating layers has a thickness of not less than 1.5 times a thickness of one of the protective layers. The wafer structure of claim 10, wherein the insulating layer is made of one of polyimide (PI), Benzocyclobutene (BCB), and polyquinol (Polyquinolin). . The wafer structure of claim 10, wherein the metal pad is one of a test pad and a pair of pad. The wafer structure of claim 10, wherein the insulating layer is spin coated (spin coating), printing (printing) or attaching a dry film (dry film). A wafer processing method comprising the steps of: providing a wafer having a plurality of crystal grains, the crystal grains being arranged in an array, wherein adjacent regions between the crystal grains are defined as a dicing street, The cutting track has a plurality of metal pads, and the die and the cutting track are formed with a protective layer to cover the metal pads; forming an insulating layer on the protective layer of the cutting track, the insulating layer at least partially covering the a metal pad; and cutting the wafer along the scribe line to form a plurality of individual dies and at least partially removing the metal pads. The wafer processing method of claim 16, wherein the step of forming the insulating layer extends along the scribe line and completely covers the metal pads. The wafer processing method of claim 16, wherein the step of forming the insulating layer extends along the scribe line and covers opposite sides of the metal pads. The wafer processing method of claim 16, wherein the step of forming the insulating layer is patterned to form a plurality of insulating blocks to completely cover the metal pads. The wafer processing method of claim 16, wherein the step of forming the insulating layer is patterned to form a plurality of insulating blocks in a direction parallel to one of the dicing streets to cover opposite side edges of the metal pads. The wafer processing method of claim 16, wherein one of the insulating layers has a thickness of not less than 1.5 times a thickness of one of the protective layers. The wafer processing method according to claim 16, wherein the step of forming the insulating layer is performed by a spin coating method, a printing method, or a labeling method. Formed by a dry film method. A wafer processing method comprising the steps of: providing a wafer having a plurality of crystal grains, the crystal grains being arranged in an array, wherein adjacent regions between the crystal grains are defined as a dicing street, a surface of one of the scribe lines to a side surface of each of the upper surfaces of the dies defines a vertical wall having a plurality of metal pads thereon, and the dies are formed on the scribe lines a protective layer covering the metal pads; forming an insulating layer on the protective layer of the dicing pad, the insulating layer is located between the metal pads and the dies, and covering at least the dies a vertical wall; and cutting the wafer along the scribe line to form a plurality of individual dies and at least partially removing the metal pads. The wafer processing method of claim 23, wherein the step of forming the insulating layer is formed around four sides of each of the crystal grains. The wafer processing method of claim 23, wherein one of the insulating layers has a thickness of not less than 1.5 times a thickness of one of the protective layers. The wafer processing method according to claim 23, wherein the step of forming the insulating layer is formed by a spin coating method, a printing method, or a dry film method.