TWI452618B - Scribe line structure and method for dicing a wafer - Google Patents

Description

Cutting track structure and method of cutting wafer

The present invention discloses a dicing track structure, and more particularly to a dicing track structure that can prevent wafer crack propagation when dicing a wafer.

The production of integrated circuits can be divided into three stages: 1) fabrication of the substrate, 2) fabrication of the integrated circuit, and 3) cutting, electrical testing, screening, and packaging of the integrated circuit. When an integrated circuit is fabricated on a substrate, the entire substrate is evenly divided into a plurality of repeating dies, and adjacent dies are separated by dicing streets. The step of cutting the integrated circuit is to cut the substrate into individual dies along the scribe line using a cutter.

In recent years, with the advancement of high-accumulation semiconductor processes, the dual damascene technology combined with low dielectric constant materials has become the most eye-catching metal interconnect. Line technology. This is because copper has a low resistance value, while low dielectric constant materials can help reduce the RC delay effect in multilayer metal wires. However, in order to achieve low dielectric properties, low dielectric constant materials are mostly loose in structure and unsatisfactory in mechanical strength, so they have characteristics of easy fragile. Therefore, when using a tool for grain cutting, the external force will easily cross the material's lodging strength, often due to chip cracking due to the cutting lateral stress, and damage to the die seal ring of the protected grain region. The region causes a metal layer delamination phenomenon in the so-called dielectric material, which causes many early failed products to be produced during the subsequent electrical test, and the yield is lowered.

SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide a scribe line structure that prevents wafer crack propagation, thereby preventing conventional dicing of wafers from damaging the entire die area due to metal layer damage in the scribe line.

According to a preferred embodiment of the present invention, a scribe line structure is disclosed, comprising a semiconductor substrate having a die region defined thereon and a die seal ring region disposed on the periphery of the die region a cutting path region is disposed at a periphery of the die sealing ring region and a dicing path is disposed on the cutting channel region, wherein a middle line of the cutting route is offset from a middle line of the cutting channel region toward a first direction .

The invention further discloses a method of cutting a wafer. First, a semiconductor substrate is provided, and the semiconductor substrate has a grain region, a die ring region is disposed at a periphery of the die region, and a scribe region is disposed at a periphery of the die ring region. A cutting path is then defined on the scribe line region, and the line in the cutting path is offset from the line in the first direction toward the scribe line region, and then the semiconductor wafer is cut along the cutting path.

Please refer to FIG. 1. FIG. 1 is a top view of a dicing structure according to a preferred embodiment of the present invention. As shown in FIG. 1, a semiconductor substrate 12, such as a germanium wafer, is first provided, and then a plurality of die regions 14, 16 and a plurality of die seal ring regions 18 are defined on the semiconductor substrate 12. 20 and a scribe line area 22. Wherein, the scribe line region 22 is disposed at the periphery of the die regions 14, 16 and the die seal regions 18, 20 and surrounds the entire die seal regions 18, 20, and the die seal regions 18, 20 are disposed at Between the die regions 14, 16 and the scribe region 22, the wafer is cut as a retaining wall structure and the grain regions 14, 16 are protected from stress damage. In this embodiment, although only one of the die sealing regions 18 and 20 is surrounded by the periphery of the die regions 14 and 16, the number of the die sealing regions 18 and 20 can be adjusted according to the process requirements. All are within the scope of the invention. In addition, a plurality of wafer acceptance test pads 24 (for example, only four wafer test pads are exemplified in the figure) may be disposed on the scribe line region 22, and the portion is dicing the wafer. It will be cut by the cutter.

Please refer to FIG. 2 and FIG. 3 next. FIG. 2 is a partial enlarged view of the scribe line region 22 between the die seal ring region 18 and the die seal ring region 20 in FIG. 1 , and FIG. 2 is a schematic cross-sectional view along the line AA'. As shown in FIG. 2, an actual cutting path 26 is defined on the scribe line region 22 of the present invention, and the center line of the cutting path 26 is offset from the center line of the scribe line region 22 in one direction, and the wafer test pad 24 is Deviate to the other direction. In accordance with a preferred embodiment of the present invention, in the scribe line region 22, the direction in which the cutting path 26 is offset is opposite to the direction in which the wafer test pad 24 is offset. As shown, the cutting path 26 is offset downwardly and immediately adjacent the edge of the die ring region 20, while the wafer test pad 24 is offset upwardly and immediately adjacent the edge of the die ring region 18.

At least one metal interconnect structure 32 is disposed under the wafer test pad 24, and the two can be completed along with the transistor and metal interconnect processes in the die regions 14, 16. For example, a plurality of MOS transistors (not shown) may be formed in the die regions 14 and 16 in accordance with a standard process. For example, a gate structure and a sidewall of the transistor may be sequentially formed on the semiconductor substrate 12. Standard transistor processes such as sub-, source/drain regions and deuterated metal layers. An interlayer dielectric layer (ILD) (not shown) is then formed and covers the transistor and die ring regions 18, 20 of the die regions 14, 16 and the semiconductor substrate 12 of the scribe region 22. Subsequently, a metal interconnect process is performed to form a plurality of dielectric layers 34 on the interlayer dielectric layers of the die regions 14, 16, the die seal regions 18, 20 and the scribe region 22, and to be embedded in the dielectric layer. The metal interconnect structure 32 formed by the patterned metal layer 28 and the conductive via 30 in FIG. 34 is as shown in FIG. Wherein, the metal interconnect structure 32 of the die regions 14, 16 directly or indirectly connect the transistor to other external lines, and the metal interconnect structure 32 of the die seal regions 18, 20 and the scribe region 22 may A separate retaining wall is selected for connection to the other lines or only to the dielectric layer 34 as the protective die areas 14, 16. A plurality of contact pads (not shown) are then formed on the dielectric layers of the die regions 14, 16 and a plurality of wafer test pads 24 are formed on the dielectric layer 34 of the scribe region 22. A wafer test pad (WAT pad) 24 can be electrically connected to various wafer test structures (WAT structures) under the scribe line region 22, by applying a voltage or current to the wafer test pads 24 to test the wafer test structure. Electrical reaction. Moreover, the wafer test pad 24 can be replaced by a monitoring block that monitors the film thickness of the stacked film layer or can be replaced by an alignment mark. In principle, the wafer test pad 24 can be any located in the scribe line region 22. structure.

In this embodiment, the wafer test pad 24 and the metal interconnect structure 32 disposed underneath are not connected to each other, but are not limited thereto, and the metal interconnect structure 32 and the metal interconnect structure 32 are connected according to the process requirements. a patterned aluminum test pad thereon, then forming a protective layer and covering the entire substrate including the test pad structure, and finally patterning the protective layer and exposing a portion of the test pad, which is also covered by the present invention range. Secondly, the wafer test pad 24 and the metal interconnect structure 32 are preferably made of conductive metals of different materials. For example, the wafer test pad 24 in this embodiment is preferably made of aluminum and its alloy, and the patterned metal layer 28 and the via hole 30 in the metal interconnect structure 32 are preferably made of copper. .

It should be noted that the cutting path 26 of the present invention overlaps only a portion of the edge of the wafer test pad 24, as shown in FIG. 2, and the cutting path 26 does not overlap the metal interconnect structure under the wafer test pad 24. 32, as shown in the cross-sectional view of Figure 3. Therefore, the present invention cuts only a portion of the wafer test pads 24 as the semiconductor substrate 12 is cut along the cutting path 26 of the scribe line region 22, and preferably does not cut into any of the metal disposed under the wafer test pads 24. Connection structure 32. However, it is not limited thereto, and the metal interconnect structure 32 of the portion of the dicing region 22 can be simultaneously cut while cutting the semiconductor substrate 12 according to the process requirements. This is also within the scope of the present invention. Since the present invention cuts only a portion of the edge of the wafer test pad 24 when the semiconductor substrate 12 is diced, and preferably does not cut the metal interconnect structure 32 disposed under the wafer test pad 24, the present invention can During the cutting process, the metal interconnect structure 32 in the dielectric layer 34 is prevented from being laterally bursting and destroyed to the adjacent grain seal ring regions 18, 20, and even affecting the inner grain of the grain seal ring regions 18, 20. District 14, 16.

4 and FIG. 5, FIG. 4 is a partially enlarged schematic view showing a dicing structure according to another embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along line BB' in FIG. 4. As shown in Fig. 4, a cutting path 26 is also defined on the scribe line region 22, and the center line of the cutting path 26 is offset downward from the center line of the scribe line region 22, and the wafer test pad 24 is upwardly offset. The center line of the kerf zone 22 is cut. In the present embodiment, the direction in which the cutting path 26 deviates is opposite to the direction in which the wafer test pad 24 is offset, and as shown in the embodiment of FIG. 4, in the scribe line region 22, the cutting path 26 The wafer test pad 24 is offset upwardly and immediately adjacent the edge of the die seal region 18.

At least one metal interconnect structure 32 is disposed under the wafer test pad 24, and the wafer test pad 24 and the metal interconnect structure 32 are preferably made of conductive metals of different materials. For example, the wafer test pad 24 in this embodiment is preferably made of aluminum and its alloy, and the patterned metal layer 28 and the via hole 30 in the metal interconnect structure 32 are preferably made of copper. .

Different from the previous embodiment, the wafer test pad 24 of the present embodiment is provided with an opening 36, and the opening 36 is preferably completed simultaneously when the wafer test pad 24 is defined. For example, a plurality of dielectric layers 34 and a metal formed by the patterned metal layer 28 and the via holes 30 embedded in the dielectric layer 34 may be formed in the dicing region 22 according to the process of fabricating the metal interconnect structure 32. The interconnect structure 32. Then, in conjunction with the contact pad process of the die regions 18 and 20, a portion of the portion of the wafer test pad 24 is removed while the wafer test pad 24 is patterned by the etch process in the scribe region 22 for wafers. An opening 36 is formed in the test pad 24. In the present embodiment, the relative position of the opening 36 is preferably disposed between the cutting path 26 and the metal interconnect structure 32. Therefore, when the semiconductor substrate 12 is cut, an isolation effect can be generated by the opening 36 to make the wafer When a portion of the edges of the test pad 24 are cut away, the cracks that avoid cutting are diffused and extend to the peripheral grain seal regions 18, 20, and even the grain regions 14, 16 that surround the die seal regions 18, 20. In addition, although the embodiment only forms an opening 36 in the wafer test pad 24, the number and position of the openings 36 can be adjusted according to the process requirements, which are all covered by the present invention.

In summary, the present invention mainly provides a scribe line structure that can avoid crack propagation when cutting a semiconductor substrate. According to a preferred embodiment of the present invention, at least one wafer test pad is disposed on the scribe line region in the scribe line structure and a cutting route is defined, and the center line of the cutting route is offset from the center line of the scribe line region in one direction. The wafer test pad is offset from the center line of the scribe line region in the opposite direction from the cutting path. Since the cutting route covers only a portion of the edge of the wafer test pad and preferably does not cover the metal interconnect structure under the wafer test pad, the present invention can cut only a portion of the wafer test pad edge when cutting the semiconductor substrate. The metal interconnect structure disposed underneath is not affected, so that cracks during cutting can be prevented from diffusing to the surrounding grain seal ring region and even affecting the entire grain region.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

12. . . Semiconductor substrate

14. . . Grain zone

16. . . Grain zone

18. . . Grain seal zone

20. . . Grain seal zone

twenty two. . . Cutting road area

twenty four. . . Wafer test pad

26. . . Cutting route

28. . . Patterned metal layer

30. . . Via

32. . . Metal interconnect structure

34. . . Dielectric layer

36. . . Opening

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a top plan view of a crack preventing structure in accordance with a preferred embodiment of the present invention.

Fig. 2 is a partially enlarged schematic view showing the scribe line area between the grain sealing zone and the grain sealing zone in Fig. 1.

Fig. 3 is a schematic cross-sectional view along the line AA' in Fig. 2.

Fig. 4 is a partially enlarged schematic view showing the structure of a dicing street according to another embodiment of the present invention.

Fig. 5 is a schematic cross-sectional view taken along line BB' in Fig. 4.

18. . . Grain seal zone

20. . . Grain seal zone

twenty two. . . Cutting road area

twenty four. . . Wafer test pad

26. . . Cutting route

Claims (15)

A dicing track structure comprising: a semiconductor substrate having a die region defined thereon, a die seal ring region disposed on a periphery of the die region, and a dicing region disposed on the die seal A peripheral portion of the ring region and a dicing path are disposed on the scribe line region, wherein a middle line of the cutting route is offset from a line in a first direction from the scribe line region, the scribe line region including at least one test pad. And the cutting route only overlaps a portion of the edge of the test pad. The scribe line structure of claim 1, wherein the test pad comprises a wafer acceptance test pad. The scribe line structure of claim 1, wherein the test pad comprises aluminum. The scribe line structure of claim 1, wherein the scribe line region comprises at least one metal interconnect structure connecting the test pads, and the cutting path does not overlap the metal interconnect structure. The scribe line structure of claim 4, wherein the metal interconnect structure comprises copper. The scribe line structure of claim 1, wherein the test pad is offset from the middle of the scribe line region in a second direction, and the first direction is opposite to the second direction. The scribe line structure of claim 4, wherein at least one opening is disposed in the test pad, and the opening is oppositely disposed between the cutting path and the metal interconnecting structure. A method of dicing a wafer, comprising: providing a semiconductor substrate, wherein the semiconductor substrate has a die region, a die ring region is disposed at a periphery of the die region, and a scribe region is disposed on the die seal a peripheral portion of the ring region; defining a cutting route on the cutting path region, and the middle line of the cutting route is offset from the middle line of the cutting channel region in a first direction; forming at least one test pad in the cutting channel region, the cutting route Only a portion of the edge of the test pad is overlapped; and only a portion of the edge of the test pad is cut as the semiconductor substrate is cut along the cutting path. The method of claim 8, wherein the test pad comprises a wafer acceptance test pad. The method of claim 8, wherein the test pad comprises aluminum. The method of claim 8, comprising forming at least one metal interconnect structure in the scribe line region and connecting the test pad, and the cutting route does not overlap the metal interconnect structure. The method of claim 11, wherein the metal interconnect structure is not cut when the semiconductor substrate is cut along the cutting path. The method of claim 11, wherein the metal interconnect structure comprises copper. The method of claim 8, wherein the test pad is offset from the middle of the scribe line region in a second direction, and the first direction is opposite to the second direction. The method of claim 8, further comprising forming at least one opening in the test pad, and the opening is disposed between the cutting path and the metal interconnect structure.