TWI438866B - Crack stopping structure and method for fabricating the same - Google Patents

Description

Crack prevention structure and manufacturing method thereof

The present invention relates to a structure for preventing cracks, and more particularly to a crack preventing structure provided in a wafer dicing area.

The production of integrated circuits can be divided into three phases: 1) wafer fabrication, 2) fabrication of integrated circuits, and 3) cutting, electrical testing, screening, and packaging of integrated circuits. When an integrated circuit is fabricated on a wafer, the entire wafer is evenly divided into a plurality of repeating dies, and adjacent dies are separated by dicing streets. The step of cutting the integrated circuit is to cut the wafer into individual dies along the scribe line using a cutter.

In recent years, with the advancement of high-accumulation semiconductor processes, the dual damascene technology combined with low dielectric constant materials has become the most eye-catching metal interconnect. Line technology. This is because copper has a low resistance value, while low dielectric constant materials can help reduce the RC delay effect in multilayer metal wires. However, in order to achieve low dielectric properties, low dielectric constant materials are mostly loose in structure and unsatisfactory in mechanical strength, so they have characteristics of easy fragile. Therefore, when using a tool for grain cutting, the external force will easily cross the material's lodging strength, often due to chip cracking due to the cutting lateral stress, and damage to the die seal ring of the protected grain region. The region, causing the phenomenon of metal layer delamination in the so-called dielectric material, causes many early mortality products to be produced during subsequent electrical testing, reducing yield.

SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide a structure that prevents the spread of cracks in the wafer to prevent conventional dicing of the wafer from damaging the entire die area due to destruction of the metal layer in the scribe line.

A preferred embodiment of the present invention discloses a crack preventing structure comprising a semiconductor substrate defining a grain region, a grain sealing region and a scribe region; and a plurality of dielectric layers are disposed in the grain region a semiconductor substrate on the die ring region and the scribe region; a metal interconnect structure disposed in the dielectric layer of the scribe region; a first opening exposing a surface of the metal interconnect structure of the scribe region; A second opening exposes a portion of the dielectric layer adjacent to the metal interconnect structure such that the metal interconnect structure forms a step with a portion of the dielectric layer.

Another embodiment of the invention is directed to a method of forming a structure that resists cracking. A semiconductor substrate is first provided, and the semiconductor substrate defines a die region, a die seal ring region, and a scribe region. A metal interconnect structure is then formed on the semiconductor substrate of the scribe region and a dielectric layer is formed on the metal interconnect. A portion of the dielectric layer is then removed to expose the surface of the metal interconnect structure, and then an exposed etching process is performed using the exposed metal interconnect structure surface as a mask to form an opening adjacent to the metal interconnect structure.

The invention mainly forms at least one opening beside the metal interconnect structure of the wafer dicing area, so that the metal interconnect and the dielectric layer exposed by the opening form at least one step, and the formed opening serves as a buffer. The cracks generated when the wafer is diced can be stopped at the opening without deepening the grain sealing zone surrounding the dicing zone or even affecting the entire grain zone. In the present invention, this structure can be respectively disposed in a region where the scribe line region is cut and not cut. For example, when disposed in a portion of the scribe line that is not cut, the structure can be used as a buffer, and when designed to be cut in the scribe line region, the design can greatly enhance the metal interconnection. The stability of the structure enables the cutting tool to cut the metal interconnect structure along the cutting path without causing problems such as dicing delamination due to doping of different metal materials.

1 to 4, FIG. 1 is a top view of a crack preventing structure according to a preferred embodiment of the present invention, and FIGS. 2 to 4 are views showing a dicing area on a semiconductor substrate of the present invention. A schematic cross-sectional view of a crack-preventing structure. As shown in FIG. 1, a semiconductor substrate 12, such as a germanium wafer, is first provided, and then a die region 14, a die seal ring region 16, and a dicing street are defined on the semiconductor substrate 12. Subscribe line) area 18. Wherein, the scribe line region 18 is disposed on the periphery of the grain region 14 and the grain seal ring region 16 and covers the entire grain seal ring region 16, and the grain seal ring region 16 is disposed in the grain region 14 and the scribe line Between the regions 18, the wafer is cut as a barrier structure and the die region 14 is protected from stress damage. In the present embodiment, the scribe line region 18 is mainly divided into two portions, including a first portion 20 and a second portion 22. The first portion 20 is adjacent to the die seal region 16 and is not cut by the cutter when the wafer is diced. The second portion 22 of the scribe line region 18 is disposed on the outer periphery of the first portion 20, and a plurality of wafer acceptance test pads 24 can be disposed on the process according to the process requirements. For example, four wafer test pads are used, and this part is cut by the tool when cutting the wafer.

Then, a plurality of MOS transistors (not shown) are formed in the die region 14 according to a standard process. For example, a gate structure, a sidewall, a source/drain of the transistor may be sequentially formed on the semiconductor substrate 12. Standard transistor processes such as areas and deuterated metal layers. An interlayer dielectric layer (ILD) (not shown) is then formed and covers the transistor of the die region 14 and the semiconductor substrate 12 of the die ring region 16 and the scribe region 18. Subsequently, a metal interconnect process is performed to form a plurality of dielectric layers 26 on the interlayer dielectric layer of the die region 14, the die seal region 16 and the scribe region 18, and a pattern embedded in the dielectric layer 26. The metal interconnect structure 32 formed by the metal layer 28 and the conductive via 30 is as shown in FIG. Wherein, the metal interconnect structure 32 of the die region 14 is directly connected to the other external circuit, and the metal interconnect structure 32 of the die seal region 16 and the scribe region 18 is selectively connectable to other lines or It is only embedded in the dielectric layer 26 as a separate retaining wall for the protective die area 14.

In order to simplify the description and highlight the main features of the present invention, the process of Figures 2 through 4 of the present invention only depicts the metal interconnect structure 32 of the scribe line region 18. As shown in the figure, in the present embodiment, the metal interconnect structure 32 disposed in the dicing street region 18 is mainly composed of a plurality of patterned metal layers 28 and via holes 30, but is not limited to this design. The metal interconnect structure 32 disposed in the dicing street region 18 may in turn be composed of a staggered stack of patterned metal layers 28 and dielectric layers that are not electrically connected to each other. This design is also within the scope of the present invention.

Next, as shown in FIG. 3, a lithography and etching process is performed on the dielectric layer 26 of the scribe region 18, for example, a patterned photoresist layer 34 is formed on the surface of the dielectric layer 26, and then as shown in FIG. An etching process is performed using the patterned photoresist layer 34 as a mask to form an opening 36 in the dielectric layer 26 and expose the top surface of the metal interconnect structure 32 of the scribe region 18 and the metal interconnect A portion of the dielectric layer 26 on the surface of the structure 32.

Subsequent etching process using the exposed metal interconnect structure 32 as a mask removes a portion of the dielectric layer 26 adjacent the metal interconnect structure 32 to form another opening 38 adjacent the metal interconnect structure 32. The sidewalls of the partially patterned metal layer 28 are exposed such that the upper surface of the metal interconnect structure 32 exposed by the opening 36 and the dielectric layer 26 at the bottom of the opening 38 together form a stepped opening. The patterned photoresist layer 34 is subsequently removed, thus completing one of the preferred embodiments of the present invention to prevent the crack structure 40.

It should be noted that although the above embodiments form the openings 36 and 38 respectively by a two-stage etching method, the present invention is not limited thereto. The present invention can simultaneously form the openings 36 in the dielectric layer 26 by using only one etching process. With 38. For example, the present invention may first perform an etching process using the patterned photoresist layer 34 to remove a portion of the dielectric layer 26 on a portion of the metal layer 28 and continue etching the metal layer 28 after etching to the surface of the metal layer 28. The dielectric layer 26 forms openings 36 and 38 simultaneously in the dielectric layer 26. This single etching process is also within the scope of the present invention.

In addition, the crack preventing structure 40 of the present invention can be fabricated in the first portion 20, the second portion 22 of the scribe line region 18 or both the first portion 20 and the second portion 22, depending on process requirements.

For example, when the crack preventing structure 40 is disposed on the first portion 20, the crack preventing structure 40 is not cut by the cutter when the wafer is cut, and the opening 38 adjacent to the metal interconnecting structure 32 can be utilized as a The buffer points allow cracks generated when the wafer is diced to stop at the opening 38 without reaching deep into the die seal region 16 or even affecting the entire die region 14.

In addition, the crack preventing structure 40 of the present invention can in turn be disposed in the second portion 22 of the dicing street region 18 as one of the sacrificial layers when the wafer is diced. In the present embodiment, when the crack preventing structure 40 is disposed on the second portion 22, the area of the patterned metal layer 28 of the metal interconnect structure 32 is approximately equal to the area of the wafer test pad 24, and the entire metal interconnect is connected. The structure 32 is composed of a material from top to bottom. For example, when the metal interconnect structure 32 and the external pads electrically connected thereto are made of two different materials, such as copper and aluminum, the upper aluminum can be removed by a lithography and etching process and exposed. The underlying copper metal makes the entire structure consist of only one type of copper metal. By this design, the second portion 22 of the scribe line region 18 of the present invention can greatly enhance the stability of the metal interconnect structure 32, so that the cutting tool can not cut the metal interconnect structure 32 along the scribe line. Different metal materials are noisy and cause problems such as dicing delamination.

In addition, in the present embodiment, the position of the opening 38 adjacent to the metal interconnect structure 32 can be adjusted according to process requirements. For example, the opening 38 can be disposed adjacent one side of the die seal ring region 16, or with respect to the other side of the die ring seal region 16, or both sides of the metal interconnect structure 32.

Please refer to FIG. 5. FIG. 5 is a schematic view showing a crack preventing structure 42 according to another embodiment of the present invention. As shown in the figure, a metal interconnect process is first performed to form a metal interconnect structure 50 embedded in the dielectric layer 44 of the scribe region 18. In the present embodiment, the metal interconnect structure 50 is formed by a plurality of patterned metal layers 46 and via holes 48 connecting the patterned metal layers 46, and the area of the patterned metal layer 46 is approximately decreasing from bottom to top. For example, the area of the patterned metal layer 46 of the first layer (ie, the uppermost layer) and the second layer is smaller than the area of the patterned metal layer 46 of the third layer, and the area of the patterned metal layer 46 of the third layer is smaller than the fourth layer. The area of the patterned metal layer 46 with the fifth layer. It should be noted that, in this embodiment, the five-layer patterned metal layer 46 and the five via holes 48 connecting the patterned metal layer 46 are taken as an example, but are not limited to this arrangement, and the patterned metal layer 46 and the via hole 48 are used. The quantity and area can be freely adjusted according to the process requirements, which are all covered by the present invention.

Then, a patterned photoresist layer (not shown) is formed on the surface of the dielectric layer 44, and an etching process is performed using the patterned photoresist layer as a mask to form an opening 52 in the dielectric layer 44 and expose it. The first layer of patterned metal layer 46 in the metal interconnect structure 50 and a portion of the dielectric layer (not shown) adjacent to the first patterned metal layer 46.

Then, an exposed etching process is performed using the exposed first patterned metal layer 46 as a mask to remove a portion of the dielectric layer 44 adjacent to the patterned metal layer 46 to form the metal layer 46 in the first layer and the second layer. Another opening 54 is formed adjacent to and exposes an upper surface of a portion of the third layer of patterned metal layer 46. Subsequently, another exposed process is performed using the exposed first layer and a portion of the third patterned metal layer 46 as a mask, and a portion of the dielectric layer 44 adjacent to the third patterned metal layer 46 is removed to the third layer. An opening 56 is formed adjacent to the patterned metal layer 46 and exposes a portion of the upper surface of the fourth patterned metal layer 46. As shown in FIG. 5, since the area of the patterned metal layer located in the upper layer is smaller than the area of the patterned metal layer located in the upper layer, the upper surface of the metal interconnect structure 50 exposed by the opening 52 and the bottom of the opening 54, the opening 56 are formed. The dielectric layers 44 together form a stepped opening. Thus, the crack preventing structure 42 of another embodiment of the present invention is completed.

It should be noted that, in this embodiment, the openings 52, 54, 56 are formed in three etching steps, respectively. However, as in the embodiments shown in FIGS. 2 to 3, the embodiment may also adopt a single etching method. Openings 52, 54, 56 are formed. For example, a patterned photoresist layer (not shown) may be formed on the surface of the dielectric layer 44 and an etching process may be performed to remove the portion of the dielectric layer 44 and expose the first metal layer 46 to continue etching the first layer of metal. Dielectric layer 44 next to layer 46 until openings 52, 54, 56 are formed.

In summary, the present invention mainly forms at least one opening beside the metal interconnect structure of the wafer dicing area, so that the metal interconnect and the dielectric layer exposed by the opening form at least one step, and the opening formed by the opening As a buffer, the cracks generated when the wafer is diced can be stopped at the opening, and the grain ring-sealing area surrounding the scribe line area can be affected even in the entire grain area. In the present invention, this structure can be respectively disposed in a region where the scribe line region is cut and not cut. As described above, this structure can be used as a buffer when it is disposed in a portion of the scribe line that is not cut, and the design can greatly enhance the metal interconnection when it is disposed in the cut portion of the scribe line region. The stability of the structure enables the cutting tool to cut the metal interconnect structure along the cutting path without causing problems such as dicing delamination due to the mixing of different metal materials.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

12. . . Semiconductor substrate

14. . . Grain zone

16. . . Grain seal zone

18. . . Cutting road area

20. . . first part

twenty two. . . the second part

twenty four. . . Wafer test pad

26. . . Dielectric layer

28. . . Patterned metal layer

30. . . Via

32. . . Metal interconnect structure

34. . . Patterned photoresist layer

36. . . Opening

38. . . Opening

40. . . Block crack structure

42. . . Block crack structure

44. . . Dielectric layer

46. . . Patterned metal layer

48. . . Via

50. . . Metal interconnect structure

52. . . Opening

54. . . Opening

56. . . Opening

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a top plan view of a crack preventing structure in accordance with a preferred embodiment of the present invention.

2 to 4 are schematic cross-sectional views showing a structure for preventing cracks in a scribe line region on a semiconductor substrate.

Fig. 5 is a schematic view showing the construction of a crack preventing structure according to another embodiment of the present invention.

12. . . Semiconductor substrate

26. . . Dielectric layer

28. . . Patterned metal layer

30. . . Via

32. . . Metal interconnect structure

36. . . Opening

38. . . Opening

40. . . Block crack structure

Claims (18)

A crack-preventing structure comprising: a semiconductor substrate defining a die region, a die seal ring region, and a scribe region; a metal interconnect structure disposed in the scribe region And the plurality of dielectric layers are disposed on the semiconductor substrate of the die region, the die seal region and the scribe region, and the dielectric layers have a first opening to expose the cut a surface of the metal interconnect structure of the track region, and a second opening exposing a portion of the dielectric layer adjacent to the metal interconnect structure, such that the metal interconnect structure forms a portion of the dielectric layer with the portion of the dielectric layer ladder. The crack prevention structure of claim 1, wherein the scribe line region comprises a first portion that is not cut and a second portion that is cut. The crack preventing structure according to claim 2, wherein the metal interconnecting structure is disposed in the first portion of the scribe line region. The crack preventing structure according to claim 2, wherein the metal interconnecting structure is disposed in the second portion of the scribe line region. A crack preventing structure as described in claim 4, wherein the metal interconnect structure is composed of a single material. A crack preventing structure as described in claim 5, wherein the material comprises copper. The crack preventing structure according to claim 1, wherein the second opening is located adjacent to one side of the cutting path region. The crack preventing structure according to claim 1, wherein the second opening is located adjacent to one side of the grain sealing zone. The crack prevention structure according to claim 1, wherein the second opening is simultaneously located on a side adjacent to the one of the cutting lanes and adjacent to one side of the grain sealing zone. A method of forming a structure for preventing cracks, comprising: providing a semiconductor substrate defining a die region, a die seal ring region, and a scribe region; forming a metal interconnect structure Cutting a semiconductor substrate on the track region; forming a dielectric layer on the metal interconnect; and removing a portion of the dielectric layer to expose the surface of the metal interconnect structure and removing portions of the metal interconnect structure The dielectric layer forms an opening adjacent to the metal interconnect structure. The method of claim 10, wherein the scribe line region comprises a first portion that is not cut and a second portion that is cut. The method of claim 11, wherein the metal interconnect structure is disposed in the first portion of the scribe line region. The method of claim 11, wherein the metal interconnect structure is disposed in the second portion of the scribe line region. The method of claim 13, wherein the metal interconnect structure is composed of a material. The method of claim 14, wherein the material comprises copper. The method of claim 10, wherein the opening is located adjacent one side of the cutting lane. The method of claim 10, wherein the opening is located adjacent to one side of the die ring region. The method of claim 10, wherein the opening is simultaneously located on a side adjacent to the scribe line region and adjacent to one side of the die seal ring region.