CN116913773B - Semiconductor chip and forming method thereof - Google Patents
Semiconductor chip and forming method thereof Download PDFInfo
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- CN116913773B CN116913773B CN202311167098.5A CN202311167098A CN116913773B CN 116913773 B CN116913773 B CN 116913773B CN 202311167098 A CN202311167098 A CN 202311167098A CN 116913773 B CN116913773 B CN 116913773B
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- annular groove
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 98
- 238000000034 method Methods 0.000 title claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
- 238000005520 cutting process Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims description 15
- 239000007769 metal material Substances 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 238000009713 electroplating Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 230000017525 heat dissipation Effects 0.000 claims description 5
- 238000007747 plating Methods 0.000 claims description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000005566 electron beam evaporation Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910052763 palladium Inorganic materials 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000002207 thermal evaporation Methods 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 238000007731 hot pressing Methods 0.000 claims description 2
- 229910002027 silica gel Inorganic materials 0.000 claims description 2
- 239000000741 silica gel Substances 0.000 claims description 2
- 230000003139 buffering effect Effects 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910001928 zirconium oxide Inorganic materials 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013013 elastic material Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000010329 laser etching Methods 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 238000009740 moulding (composite fabrication) Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000011417 postcuring Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Dicing (AREA)
Abstract
The invention relates to a semiconductor chip and a forming method thereof, and relates to the technical field of semiconductor packaging. In the method for forming the semiconductor chip, each semiconductor chip region comprises a plurality of semiconductor functional units, no cutting channel is arranged between adjacent semiconductor functional units in each semiconductor chip region, a buffer region and a cutting channel are arranged around each semiconductor chip region, further, a large-size first metal block and a large-size second metal block can be arranged in the buffer region, the plurality of first metal blocks and the plurality of second metal blocks are all arranged in an annular shape, the semiconductor chip region can be effectively protected from cutting damage, and the buffer medium blocks are formed in each buffer region to further inhibit the cutting damage.
Description
Technical Field
The present disclosure relates to semiconductor packaging technology, and more particularly, to a semiconductor chip and a method for forming the same.
Background
The semiconductor production process comprises wafer manufacturing, wafer testing, chip packaging and post-packaging testing. After plastic packaging, a series of operations such as post-curing, rib cutting and forming, electroplating, printing and the like are further carried out. The typical packaging process flow is: scribing, chip loading, bonding, plastic packaging, deburring, electroplating, printing, rib cutting and forming, appearance inspection, finished product testing and packaging and shipment. In the conventional dicing process, a semiconductor wafer is diced into a plurality of single dies, and the dicing process is complex, the dicing process is complicated, and the dicing yield is low.
Disclosure of Invention
It is an object of the present invention to overcome the drawbacks of the prior art and to provide a semiconductor chip and a method of forming the same.
More specifically, the present invention relates to a method for forming a semiconductor chip, comprising the steps of:
providing a wafer, wherein the wafer comprises a plurality of semiconductor chip areas, each semiconductor chip area comprises a plurality of semiconductor functional units, no dicing channel is arranged between adjacent semiconductor functional units in each semiconductor chip area, a buffer area and dicing channels are arranged around each semiconductor chip area, and the buffer area is positioned between the corresponding semiconductor chip area and the dicing channels.
A first annular groove and a second annular groove are formed in each buffer zone, each second annular groove surrounds the corresponding first annular groove, the first annular groove comprises a plurality of first grooves which are arranged separately, and the second annular groove comprises a plurality of second grooves which are arranged separately.
A metallic material is deposited in the first recess and the second recess, a first metal block is formed in the first recess and a second metal block is formed in the second recess.
A plurality of third grooves are formed in each buffer area, and then buffer medium blocks are formed in the third grooves.
Dicing the wafer along the dicing streets to form a plurality of separated semiconductor chips, each semiconductor chip including a plurality of semiconductor functional units.
According to an embodiment of the present invention, a carrier substrate is preset before each buffer zone forms the first annular groove and the second annular groove, and the carrier substrate carries the wafer.
According to an embodiment of the present invention, the first groove and the second groove have the same size, and both the first groove and the second groove penetrate through the wafer.
According to the embodiment of the invention, the first groove and the second groove are formed in the same etching process by utilizing a photoresist mask.
According to an embodiment of the present invention, the metal material is one or more of copper, aluminum, silver, titanium, palladium, and nickel, and the method for depositing the metal material is electroplating, magnetron sputtering, thermal evaporation, chemical plating, electron beam evaporation, or chemical vapor deposition.
According to the embodiment of the invention, the buffer medium block is made of one of organic resin, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and zirconium oxide.
According to an embodiment of the present invention, the carrier substrate is removed before dicing the wafer along the dicing streets.
The invention also relates to a semiconductor chip, which is prepared and formed by adopting the method for forming the semiconductor chip.
Compared with the prior art, the invention has the following beneficial effects:
in the method for forming the semiconductor chip, each semiconductor chip region comprises a plurality of semiconductor functional units, no cutting channel is arranged between the adjacent semiconductor functional units in each semiconductor chip region, and a buffer region and the cutting channel are arranged around each semiconductor chip region, so that a first metal block and a second metal block with large sizes can be arranged in the buffer region. The first metal blocks and the second metal blocks are all annular, so that the semiconductor chip area can be effectively protected from cutting damage, and the buffer medium blocks are formed in each buffer area to further inhibit the cutting damage. And because of the existence of the first metal block and the second metal block, the heat generated during the working of the semiconductor chip area can be rapidly led out to play the role of a heat dissipation column, so that the heat dissipation column is not required to be additionally arranged, the production process is simplified, and the durability of the semiconductor chip is effectively improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic view of a wafer according to the present invention;
FIG. 2 is a schematic view of the structure of the present invention in which a first annular groove and a second annular groove are formed in each buffer area;
FIG. 3 is a schematic diagram showing a structure of forming a first metal block in a first groove and a second metal block in a second groove according to the present invention;
FIG. 4 is a schematic diagram of a structure in which a plurality of third grooves are formed in each buffer area and a buffer medium block is formed in each third groove according to the present invention;
fig. 5 is a schematic structural view of forming a plurality of separated semiconductor chips in the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
The invention provides a method for forming a semiconductor chip, which comprises the following steps:
providing a wafer, wherein the wafer comprises a plurality of semiconductor chip areas, each semiconductor chip area comprises a plurality of semiconductor functional units, no dicing channel is arranged between adjacent semiconductor functional units in each semiconductor chip area, a buffer area and dicing channels are arranged around each semiconductor chip area, and the buffer area is positioned between the corresponding semiconductor chip area and the dicing channels.
A first annular groove and a second annular groove are formed in each buffer zone, each second annular groove surrounds the corresponding first annular groove, the first annular groove comprises a plurality of first grooves which are arranged separately, and the second annular groove comprises a plurality of second grooves which are arranged separately.
A metallic material is deposited in the first recess and the second recess, a first metal block is formed in the first recess and a second metal block is formed in the second recess.
A plurality of third grooves are formed in each buffer area, and then buffer medium blocks are formed in the third grooves.
Dicing the wafer along the dicing streets to form a plurality of separated semiconductor chips, each semiconductor chip including a plurality of semiconductor functional units.
Further, before forming the first annular groove and the second annular groove in each buffer area, a carrier substrate is preset, and the carrier substrate carries the wafer.
Further, the first groove and the second groove have the same size, and both the first groove and the second groove penetrate through the wafer.
Further, the first groove and the second groove are formed in the same etching process by using a photoresist mask.
Further, the metal material is one or more of copper, aluminum, silver, titanium, palladium and nickel, and the method for depositing the metal material is electroplating, magnetron sputtering, thermal evaporation, chemical plating, electron beam evaporation or chemical vapor deposition.
Further, the buffer medium block is made of one of organic resin, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and zirconium oxide.
Further, the carrier substrate is removed before dicing the wafer along the dicing streets.
The invention also provides a semiconductor chip which is prepared and formed by adopting the method for forming the semiconductor chip.
Please refer to fig. 1-5. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1 to 5, the present embodiment provides a method for forming a semiconductor chip, including the steps of:
as shown in fig. 1, a wafer 100 is provided, and the wafer includes a plurality of semiconductor chip regions 101, each semiconductor chip region 101 includes a plurality of semiconductor functional units 102, and no scribe line is provided between adjacent semiconductor functional units 102 in each semiconductor chip region 101. A buffer area 103 and a dicing channel 104 are disposed around each semiconductor chip area 101, and the buffer area 103 is located between the corresponding semiconductor chip area 101 and the dicing channel 104.
In a specific embodiment, the wafer 100 is a silicon wafer or a silicon carbide wafer.
In a specific embodiment, the plurality of semiconductor chip regions 101 in the wafer 100 are arranged in a matrix, and the plurality of semiconductor functional units 102 in each of the semiconductor chip regions 101 are arranged in a matrix. More specifically, the plurality of semiconductor function units 102 arranged in a matrix may be specifically (3-20) × (3-20) semiconductor function units 102. The arrangement of the structure can effectively save the area occupied by the cutting channel in the wafer 100, further can be provided with more active functional units 101, further improves the proportion of the effective area of the wafer 100, and can improve the flexibility of the semiconductor chip area 101.
As shown in fig. 2, a first annular groove and a second annular groove are formed in each of the buffer areas 103, each of the second annular grooves surrounds the corresponding first annular groove, the first annular groove includes a plurality of first grooves 201 disposed separately, and the second annular groove includes a plurality of second grooves 202 disposed separately.
In a specific embodiment, before each buffer area 103 forms the first annular groove and the second annular groove, a carrier substrate (not shown) is preset, and the carrier substrate carries the wafer.
In a specific embodiment, the carrier substrate may be a suitable rigid substrate, such as a metal plate, a plastic plate, a glass plate, a ceramic plate, etc., so as to facilitate forming the first annular groove and the second annular groove, and the carrier substrate may avoid damaging the wafer 100 when forming the first annular groove and the second annular groove.
In a specific embodiment, the first groove 201 and the second groove 202 have the same size, and the first groove 201 and the second groove 202 extend through the wafer 100.
In a specific embodiment, the first recess 201 and the second recess 202 are formed in the same etching process using a photoresist mask, more specifically, the first recess 201 and the second recess 202 are formed by a wet etching process, and in other embodiments, the first recess 201 and the second recess 202 are formed by a laser etching process.
As shown in fig. 3, a metal material is then deposited in the first recess 201 and the second recess 202, a first metal block 301 is formed in the first recess 201 and a second metal block 302 is formed in the second recess 202.
In a specific embodiment, the metal material is one or more of copper, aluminum, silver, titanium, palladium, and nickel, and the method for depositing the metal material is electroplating, magnetron sputtering, thermal evaporation, chemical plating, electron beam evaporation, or chemical vapor deposition.
In a more specific embodiment, a metallic material is selectively deposited by an electrolytic copper plating process, thereby forming copper blocks as the first and second metal blocks 301 and 302.
As shown in fig. 4, a plurality of third grooves are formed in each of the buffer areas 103, and then a buffer medium block 303 is formed in the third grooves.
In a specific embodiment, the plurality of third grooves are formed by a laser ablation process, so as to precisely locate the third grooves in the buffer region 103, thereby avoiding damage to the first metal block 301 and the second metal block 302 during the formation of the third grooves.
In a specific embodiment, the material of the buffer medium block 303 is selected from one of organic resin, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and zirconium oxide. In a more specific embodiment, the organic resin may be an elastic material such as silica gel, and the buffer medium block 303 is formed by a hot pressing, slot coating, or the like, and when the buffer medium block 303 is one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and zirconium oxide, the buffer medium block is formed by a PECVD or ALD process.
In a specific embodiment, the buffer dielectric block 303 can effectively buffer the mismatch between the thermal expansion coefficients of the first metal block 301 and the second metal block 302 and the thermal expansion coefficient of the wafer material in the buffer region 103.
As shown in fig. 5, the wafer 100 is diced along the dicing streets 104 to form a plurality of separated semiconductor chips 400, and each semiconductor chip 400 includes a plurality of semiconductor functional units 102.
In an embodiment, the carrier substrate is removed before dicing the wafer 100 along the dicing streets 104.
As shown in fig. 5, the present invention further provides a semiconductor chip, which is formed by using the method for forming a semiconductor chip.
In the method for forming the semiconductor chip, each semiconductor chip region comprises a plurality of semiconductor functional units, no cutting channel is arranged between adjacent semiconductor functional units in each semiconductor chip region, a buffer region and a cutting channel are arranged around each semiconductor chip region, further, a large-size first metal block and a large-size second metal block can be arranged in the buffer region, the plurality of first metal blocks and the plurality of second metal blocks are all arranged in an annular shape, the semiconductor chip region can be effectively protected from cutting damage, and the buffer medium blocks are formed in each buffer region to further inhibit the cutting damage. And because of the existence of the first metal block and the second metal block, the heat generated during the working of the semiconductor chip area can be rapidly led out to play the role of a heat dissipation column, so that the heat dissipation column is not required to be additionally arranged, the production process is simplified, and the durability of the semiconductor chip is effectively improved.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (6)
1. A method of forming a semiconductor chip, characterized by: the method comprises the following steps:
providing a wafer, wherein the wafer comprises a plurality of semiconductor chip areas, each semiconductor chip area comprises a plurality of semiconductor functional units, no dicing channel is arranged between adjacent semiconductor functional units in each semiconductor chip area, a buffer area and dicing channels are arranged around each semiconductor chip area, and the buffer area is positioned between the corresponding semiconductor chip area and the dicing channels;
forming a first annular groove and a second annular groove in each buffer zone, wherein each second annular groove surrounds the corresponding first annular groove, the first annular groove comprises a plurality of first grooves which are arranged separately, the second annular groove comprises a plurality of second grooves which are arranged separately, the sizes of the first grooves and the second grooves are the same, and the first grooves and the second grooves penetrate through the wafer;
depositing a metal material in the first groove and the second groove, forming a first metal block in the first groove and forming a second metal block in the second groove;
forming a plurality of third grooves in each buffer area, wherein one part of the third grooves are positioned in the area between the adjacent first grooves, the other part of the third grooves are positioned in the area between the adjacent second grooves, then forming a buffer medium block in the third grooves, wherein the buffer medium block is made of silica gel, and the buffer medium block is formed through a hot pressing process;
dicing the wafer along the dicing streets to form a plurality of separated semiconductor chips, each semiconductor chip including a plurality of semiconductor functional units;
the buffer medium block is used for buffering mismatch between the thermal expansion coefficients of the first metal block and the second metal block and the thermal expansion coefficient of the wafer material in the buffer zone;
the first metal block and the second metal block are heat dissipation columns.
2. The method of forming a semiconductor chip according to claim 1, wherein: before each buffer zone forms a first annular groove and a second annular groove, a carrier substrate is preset, and the carrier substrate carries the wafer.
3. The method of forming a semiconductor chip according to claim 1, wherein: and forming the first groove and the second groove in the same etching process by using a photoresist mask.
4. The method of forming a semiconductor chip according to claim 1, wherein: the metal material is one or more of copper, aluminum, silver, titanium, palladium and nickel, and the method for depositing the metal material is electroplating, magnetron sputtering, thermal evaporation, chemical plating, electron beam evaporation or chemical vapor deposition.
5. The method of forming a semiconductor chip according to claim 2, wherein: and removing the carrier substrate before cutting the wafer along the cutting path.
6. A semiconductor chip, wherein the semiconductor chip is formed by the method for forming a semiconductor chip according to any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311167098.5A CN116913773B (en) | 2023-09-12 | 2023-09-12 | Semiconductor chip and forming method thereof |
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| CN202311167098.5A CN116913773B (en) | 2023-09-12 | 2023-09-12 | Semiconductor chip and forming method thereof |
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| CN116913773A CN116913773A (en) | 2023-10-20 |
| CN116913773B true CN116913773B (en) | 2024-01-26 |
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