CN112331614A - Cutting method of semiconductor chip - Google Patents
Cutting method of semiconductor chip Download PDFInfo
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- CN112331614A CN112331614A CN202011348504.4A CN202011348504A CN112331614A CN 112331614 A CN112331614 A CN 112331614A CN 202011348504 A CN202011348504 A CN 202011348504A CN 112331614 A CN112331614 A CN 112331614A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 106
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000005520 cutting process Methods 0.000 title claims abstract description 22
- 229920005989 resin Polymers 0.000 claims abstract description 86
- 239000011347 resin Substances 0.000 claims abstract description 86
- 229910052751 metal Inorganic materials 0.000 claims abstract description 72
- 239000002184 metal Substances 0.000 claims abstract description 72
- 239000002070 nanowire Substances 0.000 claims abstract description 62
- 239000010410 layer Substances 0.000 claims abstract description 51
- 238000007789 sealing Methods 0.000 claims abstract description 19
- 239000011241 protective layer Substances 0.000 claims abstract description 5
- 239000006185 dispersion Substances 0.000 claims description 24
- 238000004528 spin coating Methods 0.000 claims description 22
- 239000007769 metal material Substances 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 19
- 239000007788 liquid Substances 0.000 claims description 17
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 13
- 229920002873 Polyethylenimine Polymers 0.000 claims description 12
- 239000003822 epoxy resin Substances 0.000 claims description 12
- 229920000647 polyepoxide Polymers 0.000 claims description 12
- 239000004925 Acrylic resin Substances 0.000 claims description 10
- 229920000178 Acrylic resin Polymers 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 9
- 239000002042 Silver nanowire Substances 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 9
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 239000004793 Polystyrene Substances 0.000 claims description 5
- 239000004372 Polyvinyl alcohol Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 238000001704 evaporation Methods 0.000 claims description 5
- 230000008020 evaporation Effects 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 5
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 5
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229920002050 silicone resin Polymers 0.000 claims description 5
- 229920002379 silicone rubber Polymers 0.000 claims description 5
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
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- 229920003023 plastic Polymers 0.000 description 2
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- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a method for cutting a semiconductor chip, which comprises the following steps: providing a plurality of sealing ring regions on a semiconductor wafer, forming first and second grooves on the upper surface of each sealing ring region, forming third and fourth grooves on the lower surface of each sealing ring region, arranging the semiconductor wafer with the third and fourth grooves facing a first carrier plate, forming a first resin layer in the first groove, forming a first metal nanowire/resin laminated structure in the second groove, forming a dielectric layer, a first metal layer and a second metal layer on the semiconductor wafer, bonding the second carrier plate to the semiconductor wafer, removing the first carrier plate, and forming a second resin layer in the third groove; forming a second metal nanowire/resin laminated structure in the fourth groove, and forming a protective layer on the semiconductor wafer; and carrying out a cutting process on the semiconductor wafer to form separated semiconductor chips.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a cutting method of a semiconductor chip.
Background
In the conventional semiconductor chip manufacturing process, dicing streets are required to be formed in the semiconductor wafer so as to facilitate the dicing of the wafer to form the separated semiconductor chips. In the existing wafer preparation process, it is usually necessary to provide a guard ring member near the dicing streets to protect the semiconductor chips during the dicing of the wafer. In a conventional dicing process of a wafer, a sealing structure is generally provided on one surface of a semiconductor wafer, and then a single-surface dicing process is performed. How to change the structure of the protection ring member in order to improve the yield of the cutting has attracted a great deal of attention.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned deficiencies of the prior art and to provide a method for cutting a semiconductor chip.
In order to achieve the purpose, the invention adopts the technical scheme that:
a method for dicing a semiconductor chip, comprising the steps of:
1) providing a semiconductor wafer, arranging a plurality of sealing ring areas on the semiconductor wafer, and then forming a first groove and a second groove on the upper surface of each sealing ring area, wherein the first groove surrounds the second groove, and then forming a third groove and a fourth groove on the lower surface of each sealing ring area, wherein the third groove surrounds the fourth groove, the first groove and the third groove are correspondingly arranged in the vertical direction, and the second groove and the fourth groove are correspondingly arranged in the vertical direction.
2) Providing a first carrier plate, and arranging the semiconductor wafer on the first carrier plate in a manner that the third groove and the fourth groove face the first carrier plate;
3) and then filling a resin material in the first groove to form a first resin layer.
4) Then, a mask is formed on the semiconductor wafer to expose the second recess, then, a dispersion containing metal nanowires and a solution containing resin are alternately spin-coated on the semiconductor wafer a plurality of times to form a first metal nanowire/resin laminated structure in the second recess, and then, the mask is removed.
5) A dielectric material is then deposited on the semiconductor wafer to form a dielectric layer covering the semiconductor wafer, a fifth recess is formed in the dielectric layer exposing the first resin layer and a sixth recess is formed exposing the first metal nanowire/resin laminate structure, a metal material is then deposited in the fifth recess to form a first metal layer, and a metal material is deposited in the sixth recess to form a second metal layer.
6) Providing a second carrier plate, bonding the second carrier plate to the semiconductor wafer, and removing the first carrier plate to expose the lower surface of the semiconductor wafer, the third groove and the fourth groove.
7) And then filling a resin material in the third groove to form a second resin layer.
8) Then, a mask is formed on the semiconductor wafer to expose the fourth groove, then, a dispersion containing metal nanowires and a solution containing resin are alternately spin-coated on the semiconductor wafer a plurality of times to form a second metal nanowire/resin laminated structure in the fourth groove, and then, the mask is removed.
9) A dielectric material is then deposited on the semiconductor wafer to form a protective layer covering the semiconductor wafer.
10) And then, carrying out a cutting process on the semiconductor wafer to form separated semiconductor chips.
Preferably, in step 1), the depth of the first groove is the same as the depth of the second groove, the depth of the third groove is the same as the depth of the fourth groove, and the ratio of the depth of the third groove to the depth of the first groove is 1.5 to 5.
Preferably, in the steps 3) and 7), the resin material is one of epoxy resin, acrylic resin, silicone resin, rubber, and polyethyleneimine.
Preferably, in the steps 4) and 8), the metal nanowire in the dispersion liquid containing the metal nanowire is one of silver nanowire, copper nanowire, gold nanowire and nickel nanowire, the resin in the solution containing the resin is one of polyvinyl alcohol, polyethyleneimine, polymethyl methacrylate, polystyrene, epoxy resin and acrylic resin, the rotation speed of the dispersion liquid containing the metal nanowire in spin coating is 3000-5000 r/min, and the rotation speed of the solution containing the resin in spin coating is 2000-4000 r/min.
Preferably, in the step 5), the metal material is one or more of copper, aluminum, titanium and nickel, and the metal material is layer-deposited by electroplating, electroless plating, evaporation, magnetron sputtering or chemical vapor deposition.
Preferably, in the step 9), the dielectric material is one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and zirconium oxide, and is formed by magnetron sputtering, atomic layer deposition, or PECVD.
Compared with the prior art, the invention has the following advantages:
in the method for cutting a semiconductor chip of the present invention, a first groove and a second groove are formed on the upper surface of each sealing ring region, a third groove and a fourth groove are formed on the lower surface of each sealing ring region, and a resin layer and a metal nanowire/resin lamination structure are respectively formed in the first, second, third and fourth grooves, which can absorb cutting stress and avoid stress cracking, and a fifth groove exposing the first resin layer and a sixth groove exposing the first metal nanowire/resin lamination structure are formed in the dielectric layer, and a metal material is deposited in the fifth groove to form a first metal layer, and a metal material is deposited in the sixth groove to form a second metal layer, which can effectively block moisture, and finally, a cutting process is performed from the back surface of the semiconductor wafer, the influence of cutting stress on the semiconductor chip is eliminated to the maximum extent.
Drawings
Fig. 1 to 6 are schematic structural views of steps of a method for cutting a semiconductor chip according to the present invention.
Detailed Description
In order to better understand the technical scheme of the invention, the following detailed description of the embodiments of the invention is provided with the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that although the terms first, second, etc. may be used to describe semiconductor chips in embodiments of the present invention, these semiconductor chips should not be limited to these terms. These terms are only used to distinguish the semiconductor chips from one another. For example, the first semiconductor chip may also be referred to as a second semiconductor chip, and similarly, the second semiconductor chip may also be referred to as a first semiconductor chip, without departing from the scope of embodiments of the present invention.
Please refer to fig. 1 to 6. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 to 6, the present embodiment provides a method for cutting a semiconductor chip, including the steps of:
first, as shown in fig. 1, in step 1), a semiconductor wafer 1 is provided, a plurality of seal ring regions 2 are disposed on the semiconductor wafer 1, and then a first groove 21 and a second groove 22 are formed on an upper surface of each seal ring region 2, wherein the first groove 21 surrounds the second groove 22, and then a third groove 23 and a fourth groove 24 are formed on a lower surface of each seal ring region 2, wherein the third groove 23 surrounds the fourth groove 24, the first groove 21 and the third groove 23 are disposed in a vertical direction, and the second groove 22 and the fourth groove 24 are disposed in a vertical direction.
In step 1), the depth of the first groove 21 is the same as that of the second groove 22, the depth of the third groove 23 is the same as that of the fourth groove 24, and the ratio of the depth of the third groove 23 to that of the first groove 21 is 1.5-5.
In a specific embodiment, the semiconductor wafer 1 may specifically be a silicon substrate, a germanium substrate, a silicon germanium substrate, or an SOI substrate, a plurality of integrated circuit regions are disposed on the semiconductor wafer 1, each sealing ring region 2 surrounds one corresponding integrated circuit region, and a dicing channel region is disposed on the periphery of each sealing ring region 2, where the integrated circuit regions include functional devices such as a field effect transistor, a resistor, a capacitor, an inductor, and a diode.
In a specific embodiment, the first, second, third, and fourth grooves are formed by a wet etching process or a dry etching process, respectively, a ratio of a depth of the third groove 23 to a depth of the first groove 21 is 1.5 to 5, and specifically, a ratio of a depth of the third groove 23 to a depth of the first groove 21 is 2, 3, or 4.
As shown in fig. 2, in step 2), a first carrier plate 3 is provided, and the semiconductor wafer 1 is disposed on the first carrier plate 1 in such a manner that the third recess 23 and the fourth recess 24 face the first carrier plate 3.
In a specific embodiment, the first carrier 3 may be one of a stainless steel carrier, a glass carrier, a sapphire carrier, a plastic carrier, and a silicon carrier, and further, a temporary bonding layer is disposed on the first carrier 3, and the temporary bonding layer may lose its adhesiveness in a heating or lighting manner, so that the semiconductor wafer 1 is bonded on the first carrier 1 in a manner that the third groove 23 and the fourth groove 24 face the first carrier 3.
As shown in fig. 2, 3) next, a resin material is filled in the first groove 21 to form a first resin layer 41.
Wherein, in the step 3), the resin material is one of epoxy resin, acrylic resin, silicone resin, rubber and polyethyleneimine.
Specifically, the resin material is specifically an epoxy resin, and specifically, may be formed by slit coating, spin coating or spray coating. In other embodiments, the resin material may be embedded in the first groove 21 by thermal compression, so as to remove the resin material outside the first groove 21.
As shown in fig. 2, in step 4), a mask is then formed on the semiconductor wafer 1 to expose the second recess 22, and then a dispersion containing metal nanowires and a solution containing resin are alternately spin-coated on the semiconductor wafer 1 a plurality of times to form a first metal nanowire/resin stacked structure 42 in the second recess, and then the mask is removed.
In the step 4), the metal nanowire in the dispersion liquid containing the metal nanowire is one of a silver nanowire, a copper nanowire, a gold nanowire and a nickel nanowire, the resin in the solution containing the resin is one of polyvinyl alcohol, polyethyleneimine, polymethyl methacrylate, polystyrene, epoxy resin and acrylic resin, the rotation speed of the dispersion liquid containing the metal nanowire in spin coating is 3000-5000 r/min, and the rotation speed of the solution containing the resin in spin coating is 2000-4000 r/min.
In a specific embodiment, the mask may be a photoresist mask, the concentration of the metal nanowires in the dispersion liquid containing the metal nanowires is 5-15mg/ml, more specifically, the concentration of the metal nanowires in the dispersion liquid containing the metal nanowires is 8mg/ml, 10mg/ml or 12mg/ml, the length of the metal nanowires may be 1-5 micrometers, specifically 2-3 micrometers, the distance between the metal nanowires is 10-60 nanometers, specifically 30-50 nanometers, the metal nanowires may be silver nanowires, the rotation speed of spin-coating the dispersion liquid containing the silver nanowires may be 3500 rpm, 4000 rpm or 4500 rpm, the spin-coating time is 1 minute, the resin in the solution containing the resin is polyethyleneimine, the spin coating of the resin-containing solution is performed at a rotation speed of 2500 rpm, 3000 rpm or 3500 rpm, and the number of alternation may be 3 to 8 times, and more preferably may be 5 or 6 times. And each metal nanowire and each resin layer can be formed in a proper thickness through a plurality of spin coating processes.
As shown in fig. 3, in step 5), a dielectric material is then deposited on the semiconductor wafer 1 to form a dielectric layer 5 covering the semiconductor wafer 1, a fifth groove 51 exposing the first resin layer 41 and a sixth groove 52 exposing the first metal nanowire/resin laminated structure 42 are formed in the dielectric layer 5, a metal material is then deposited in the fifth groove 51 to form a first metal layer 61, and a metal material is deposited in the sixth groove 52 to form a second metal layer 62.
In the step 5), the dielectric material is one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and zirconium oxide, and is formed by magnetron sputtering, atomic layer deposition or PECVD method, the metal material is one or more of copper, aluminum, titanium and nickel, and the metal material is layer-deposited by electroplating, electroless plating, evaporation, magnetron sputtering or chemical vapor deposition method.
In a specific embodiment, the dielectric material may be silicon oxide and is formed by a PECVD method, and then the dielectric layer 5 is dry-etched by using a mask to form the fifth recess 51 and the sixth recess 52, the metal material is aluminum, and the first and second metal layers 61 and 62 are formed by an evaporation process.
As shown in fig. 4, in step 6), a second carrier board 7 is provided, the second carrier board 7 is bonded to the semiconductor wafer 1, and then the first carrier board 3 is removed to expose the lower surface of the semiconductor wafer 1, the third recess 23 and the fourth recess 24.
In a specific embodiment, the second carrier 7 may be one of a stainless steel carrier, a glass carrier, a sapphire carrier, a plastic carrier, and a silicon carrier, and further, a temporary bonding layer is disposed on the second carrier 7, and the temporary bonding layer may lose its adhesiveness in a heating or lighting manner, and then the first carrier 3 is removed to expose the lower surface of the semiconductor wafer 1, the third groove 23, and the fourth groove 24.
As shown in fig. 5, in step 7), a resin material is then filled in the third groove 23 to form a second resin layer 81.
Wherein, in the step 7), the resin material is one of epoxy resin, acrylic resin, silicone resin, rubber and polyethyleneimine.
Specifically, the resin material is specifically an epoxy resin, and specifically, may be formed by slit coating, spin coating or spray coating. In other embodiments, the resin material may be embedded in the third groove 23 by thermal compression, so as to remove the resin material outside the third groove 23.
As shown in fig. 5, in step 8), a mask is then formed on the semiconductor wafer 1 to expose the fourth groove 24, and then a dispersion containing metal nanowires and a solution containing resin are alternately spin-coated on the semiconductor wafer 1 a plurality of times to form a second metal nanowire/resin laminated structure 82 in the fourth groove 24, and then the mask is removed.
In the step 8), the metal nanowire in the dispersion liquid containing the metal nanowire is one of a silver nanowire, a copper nanowire, a gold nanowire and a nickel nanowire, the resin in the solution containing the resin is one of polyvinyl alcohol, polyethyleneimine, polymethyl methacrylate, polystyrene, epoxy resin and acrylic resin, the rotation speed of the dispersion liquid containing the metal nanowire in spin coating is 3000-5000 r/min, and the rotation speed of the solution containing the resin in spin coating is 2000-4000 r/min.
In a specific embodiment, the mask may be a photoresist mask, the concentration of the metal nanowires in the dispersion liquid containing the metal nanowires is 5-15mg/ml, more specifically, the concentration of the metal nanowires in the dispersion liquid containing the metal nanowires is 8mg/ml, 10mg/ml or 12mg/ml, the length of the metal nanowires may be 1-5 micrometers, specifically 2-3 micrometers, the distance between the metal nanowires is 10-60 nanometers, specifically 30-50 nanometers, the metal nanowires may be silver nanowires, the rotation speed of spin-coating the dispersion liquid containing the silver nanowires may be 3500 rpm, 4000 rpm or 4500 rpm, the spin-coating time is 1 minute, the resin in the solution containing the resin is polyethyleneimine, the spin coating of the resin-containing solution is performed at a rotation speed of 2500 rpm, 3000 rpm or 3500 rpm, and the number of alternation may be 3 to 8 times, and more preferably may be 5 or 6 times. And each metal nanowire and each resin layer can be formed in a proper thickness through a plurality of spin coating processes.
As shown in fig. 5, in step 9), a dielectric material is then deposited on the semiconductor wafer 1 to form a protective layer 9 covering the semiconductor wafer 1.
In the step 9), the dielectric material is one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and zirconium oxide, and is formed by magnetron sputtering, atomic layer deposition or PECVD.
In a specific embodiment, the dielectric material may be silicon oxide and is formed by a PECVD process.
As shown in fig. 6, in step 10), a dicing process is then performed on the semiconductor wafer along the scribe line regions to form separated semiconductor chips 10.
In the method for cutting a semiconductor chip of the present invention, a first groove and a second groove are formed on the upper surface of each sealing ring region, a third groove and a fourth groove are formed on the lower surface of each sealing ring region, and a resin layer and a metal nanowire/resin lamination structure are respectively formed in the first, second, third and fourth grooves, which can absorb cutting stress and avoid stress cracking, and a fifth groove exposing the first resin layer and a sixth groove exposing the first metal nanowire/resin lamination structure are formed in the dielectric layer, and a metal material is deposited in the fifth groove to form a first metal layer, and a metal material is deposited in the sixth groove to form a second metal layer, which can effectively block moisture, and finally, a cutting process is performed from the back surface of the semiconductor wafer, the influence of cutting stress on the semiconductor chip is eliminated to the maximum extent.
The invention provides a method for cutting a semiconductor chip.
Item 1: a method for dicing a semiconductor chip, comprising the steps of:
1) providing a semiconductor wafer, arranging a plurality of sealing ring areas on the semiconductor wafer, and then forming a first groove and a second groove on the upper surface of each sealing ring area, wherein the first groove surrounds the second groove, and then forming a third groove and a fourth groove on the lower surface of each sealing ring area, wherein the third groove surrounds the fourth groove, the first groove and the third groove are correspondingly arranged in the vertical direction, and the second groove and the fourth groove are correspondingly arranged in the vertical direction.
2) Providing a first carrier plate, and arranging the semiconductor wafer on the first carrier plate in a manner that the third groove and the fourth groove face the first carrier plate;
3) and then filling a resin material in the first groove to form a first resin layer.
4) Then, a mask is formed on the semiconductor wafer to expose the second recess, then, a dispersion containing metal nanowires and a solution containing resin are alternately spin-coated on the semiconductor wafer a plurality of times to form a first metal nanowire/resin laminated structure in the second recess, and then, the mask is removed.
5) A dielectric material is then deposited on the semiconductor wafer to form a dielectric layer covering the semiconductor wafer, a fifth recess is formed in the dielectric layer exposing the first resin layer and a sixth recess is formed exposing the first metal nanowire/resin laminate structure, a metal material is then deposited in the fifth recess to form a first metal layer, and a metal material is deposited in the sixth recess to form a second metal layer.
6) Providing a second carrier plate, bonding the second carrier plate to the semiconductor wafer, and removing the first carrier plate to expose the lower surface of the semiconductor wafer, the third groove and the fourth groove.
7) And then filling a resin material in the third groove to form a second resin layer.
8) Then, a mask is formed on the semiconductor wafer to expose the fourth groove, then, a dispersion containing metal nanowires and a solution containing resin are alternately spin-coated on the semiconductor wafer a plurality of times to form a second metal nanowire/resin laminated structure in the fourth groove, and then, the mask is removed.
9) A dielectric material is then deposited on the semiconductor wafer to form a protective layer covering the semiconductor wafer.
10) And then, carrying out a cutting process on the semiconductor wafer to form separated semiconductor chips.
Item 2: in the step 1), the depth of the first groove is the same as that of the second groove, the depth of the third groove is the same as that of the fourth groove, and the ratio of the depth of the third groove to that of the first groove is 1.5-5.
Item 3: in the steps 3) and 7), the resin material is one of epoxy resin, acrylic resin, silicone resin, rubber, and polyethyleneimine.
Item 4: in the steps 4) and 8), the metal nanowire in the dispersion liquid containing the metal nanowire is one of a silver nanowire, a copper nanowire, a gold nanowire and a nickel nanowire, the resin in the solution containing the resin is one of polyvinyl alcohol, polyethyleneimine, polymethyl methacrylate, polystyrene, epoxy resin and acrylic resin, the rotation speed of the dispersion liquid containing the metal nanowire in spin coating is 3000-4000 revolutions per minute, and the rotation speed of the solution containing the resin in spin coating is 3000-5000 revolutions per minute.
Item 5: in the step 5), the metal material is one or more of copper, aluminum, titanium and nickel, and the metal material is deposited by electroplating, chemical plating, evaporation, magnetron sputtering or chemical vapor deposition.
Item 6: in the step 9), the dielectric material is one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and zirconium oxide, and is formed by magnetron sputtering, atomic layer deposition, or PECVD.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (6)
1. A method for cutting a semiconductor chip, comprising: the method comprises the following steps:
1) providing a semiconductor wafer, arranging a plurality of sealing ring regions on the semiconductor wafer, and then forming a first groove and a second groove on the upper surface of each sealing ring region, wherein the first groove surrounds the second groove, and then forming a third groove and a fourth groove on the lower surface of each sealing ring region, wherein the third groove surrounds the fourth groove, the first groove and the third groove are arranged in a vertical direction correspondingly, and the second groove and the fourth groove are arranged in a vertical direction correspondingly;
2) providing a first carrier plate, and arranging the semiconductor wafer on the first carrier plate in a manner that the third groove and the fourth groove face the first carrier plate;
3) then filling resin materials in the first grooves to form a first resin layer;
4) then forming a mask on the semiconductor wafer to expose the second groove, then alternately spin-coating a dispersion containing the metal nanowires and a solution containing resin on the semiconductor wafer for a plurality of times to form a first metal nanowire/resin laminated structure in the second groove, and then removing the mask;
5) then depositing a dielectric material on the semiconductor wafer to form a dielectric layer covering the semiconductor wafer, forming a fifth groove in the dielectric layer exposing the first resin layer and a sixth groove exposing the first metal nanowire/resin laminate structure, then depositing a metal material in the fifth groove to form a first metal layer, and depositing a metal material in the sixth groove to form a second metal layer;
6) providing a second carrier plate, bonding the second carrier plate to the semiconductor wafer, and then removing the first carrier plate to expose the lower surface of the semiconductor wafer, the third groove and the fourth groove;
7) then filling resin materials in the third grooves to form second resin layers;
8) then, forming a mask on the semiconductor wafer to expose the fourth groove, then alternately spin-coating a dispersion liquid containing the metal nanowires and a solution containing resin on the semiconductor wafer for a plurality of times to form a second metal nanowire/resin laminated structure in the fourth groove, and then removing the mask;
9) then depositing a dielectric material on the semiconductor wafer to form a protective layer covering the semiconductor wafer;
10) and then, carrying out a cutting process on the semiconductor wafer to form separated semiconductor chips.
2. The method for dicing a semiconductor chip according to claim 1, characterized in that: in the step 1), the depth of the first groove is the same as that of the second groove, the depth of the third groove is the same as that of the fourth groove, and the ratio of the depth of the third groove to that of the first groove is 1.5-5.
3. The method for dicing a semiconductor chip according to claim 1, characterized in that: in the steps 3) and 7), the resin material is one of epoxy resin, acrylic resin, silicone resin, rubber, and polyethyleneimine.
4. The method for dicing a semiconductor chip according to claim 1, characterized in that: in the steps 4) and 8), the metal nanowire in the dispersion liquid containing the metal nanowire is one of a silver nanowire, a copper nanowire, a gold nanowire and a nickel nanowire, the resin in the solution containing the resin is one of polyvinyl alcohol, polyethyleneimine, polymethyl methacrylate, polystyrene, epoxy resin and acrylic resin, the rotation speed of the dispersion liquid containing the metal nanowire in spin coating is 3000-4000 revolutions per minute, and the rotation speed of the solution containing the resin in spin coating is 3000-5000 revolutions per minute.
5. The method for dicing a semiconductor chip according to claim 1, characterized in that: in the step 5), the metal material is one or more of copper, aluminum, titanium and nickel, and the metal material is deposited by electroplating, chemical plating, evaporation, magnetron sputtering or chemical vapor deposition.
6. The method for dicing a semiconductor chip according to claim 1, characterized in that: in the step 9), the dielectric material is one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and zirconium oxide, and is formed by magnetron sputtering, atomic layer deposition, or PECVD.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011348504.4A CN112331614A (en) | 2020-11-26 | 2020-11-26 | Cutting method of semiconductor chip |
| PCT/CN2021/114630 WO2022110935A1 (en) | 2020-11-26 | 2021-08-26 | Cutting method for semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011348504.4A CN112331614A (en) | 2020-11-26 | 2020-11-26 | Cutting method of semiconductor chip |
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| CN112331614A true CN112331614A (en) | 2021-02-05 |
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| CN202011348504.4A Withdrawn CN112331614A (en) | 2020-11-26 | 2020-11-26 | Cutting method of semiconductor chip |
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| Country | Link |
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| CN (1) | CN112331614A (en) |
| WO (1) | WO2022110935A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114161591A (en) * | 2021-12-03 | 2022-03-11 | 江西省纳米技术研究院 | Nondestructive cleavage method for semiconductor chip |
| CN114551251A (en) * | 2022-02-23 | 2022-05-27 | 威海艾迪科电子科技股份有限公司 | Multi-chip package with antenna structure and preparation method thereof |
| WO2022110935A1 (en) * | 2020-11-26 | 2022-06-02 | 苏州矽锡谷半导体科技有限公司 | Cutting method for semiconductor chip |
| CN116913773A (en) * | 2023-09-12 | 2023-10-20 | 威海市泓淋电力技术股份有限公司 | Semiconductor chip and forming method thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115083903B (en) * | 2022-07-21 | 2022-11-15 | 山东中清智能科技股份有限公司 | Wafer cutting method and single chip package |
| CN118380337B (en) * | 2024-06-25 | 2024-09-06 | 日月新半导体(威海)有限公司 | Packaging structure of semiconductor wafer and forming method thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3529050B2 (en) * | 2002-07-12 | 2004-05-24 | 沖電気工業株式会社 | Method for manufacturing semiconductor device |
| CN106992159A (en) * | 2016-12-07 | 2017-07-28 | 王伟 | Double-face adhesive chip electronic component and its method for packing |
| CN110690160A (en) * | 2019-10-16 | 2020-01-14 | 上海先方半导体有限公司 | Chip protection structure and manufacturing method thereof |
| CN111564411B (en) * | 2020-06-08 | 2022-12-23 | 深圳铨力半导体有限公司 | Semiconductor device and forming method thereof |
| CN112331614A (en) * | 2020-11-26 | 2021-02-05 | 苏州矽锡谷半导体科技有限公司 | Cutting method of semiconductor chip |
-
2020
- 2020-11-26 CN CN202011348504.4A patent/CN112331614A/en not_active Withdrawn
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2021
- 2021-08-26 WO PCT/CN2021/114630 patent/WO2022110935A1/en active Application Filing
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022110935A1 (en) * | 2020-11-26 | 2022-06-02 | 苏州矽锡谷半导体科技有限公司 | Cutting method for semiconductor chip |
| CN114161591A (en) * | 2021-12-03 | 2022-03-11 | 江西省纳米技术研究院 | Nondestructive cleavage method for semiconductor chip |
| CN114551251A (en) * | 2022-02-23 | 2022-05-27 | 威海艾迪科电子科技股份有限公司 | Multi-chip package with antenna structure and preparation method thereof |
| CN116913773A (en) * | 2023-09-12 | 2023-10-20 | 威海市泓淋电力技术股份有限公司 | Semiconductor chip and forming method thereof |
| CN116913773B (en) * | 2023-09-12 | 2024-01-26 | 威海市泓淋电力技术股份有限公司 | Semiconductor chip and forming method thereof |
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| Publication number | Publication date |
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| WO2022110935A1 (en) | 2022-06-02 |
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