CN110690160A - Chip protection structure and manufacturing method thereof - Google Patents
Chip protection structure and manufacturing method thereof Download PDFInfo
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- CN110690160A CN110690160A CN201910981695.9A CN201910981695A CN110690160A CN 110690160 A CN110690160 A CN 110690160A CN 201910981695 A CN201910981695 A CN 201910981695A CN 110690160 A CN110690160 A CN 110690160A
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- chip
- seal ring
- protection
- deep groove
- deep trench
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
Abstract
The invention provides a chip protection structure, which comprises a deep groove structure arranged on a chip, wherein the chip comprises a chip area, a substrate oxidation layer and a silicon substrate; the chip area comprises an effective area and a sealing ring; the deep groove structure penetrates through the chip area and the substrate oxide layer to reach the inside of the silicon substrate; and the deep groove structure is internally provided with a hole wall protective layer.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a chip protection structure and a manufacturing method thereof.
Background
A chip, a miniature electronic device or component, typically a semiconductor material, is known as an industrially produced "heart". As the demand for lighter and thinner electronic products increases, the manufacture of chips is moving towards smaller, thinner, and higher performance.
Wafer thinning of integrated chips presents a series of problems. One of the main problems is that in the fabrication of semiconductor chips, chip cutting often causes defects at the chip edge, such as cracks, edge chipping, delamination, etc., and once the cracks expand to the active area of the chip, the performance and reliability of the final electronic device are reduced, so a structure is required to be designed to prevent the cracks of the integrated chip from expanding so as to improve the reliability of the chip.
In the prior art, a crack stop block (crack stop) is usually added in the fabrication of a seal ring (seal ring) at the edge of a chip to prevent a crack generated in a process from expanding from a scribe line to an active device (active device) inside the chip. However, the crack stoppers cannot effectively prevent cracks generated in the oxide layer and the silicon substrate of the chip substrate, and such cracks expand to the effective region inside the chip, which may eventually affect the reliability of the chip and even cause the chip to fail.
Therefore, it is necessary to provide a new chip structure to solve the above problems.
Disclosure of Invention
The invention aims to provide a structure for improving the reliability of a chip and a manufacturing method thereof, which prevent cracks generated on a chip substrate oxidation layer and a silicon substrate from expanding towards the inside of the chip.
In order to solve the above technical problems, the present invention provides a chip protection structure, which includes a deep trench structure; the deep groove structure penetrates through a chip area of the chip and the substrate oxide layer to reach the inside of the silicon substrate, and a hole wall protection layer is arranged inside the deep groove structure; the chip area of the chip comprises an effective area and a sealing ring.
In an embodiment of the invention, the deep groove structure has two, one at the edge of the chip outside the sealing ring and the other in the sealing ring.
In an embodiment of the invention, the deep groove structure is located at the chip edge outside the sealing ring.
In an embodiment of the invention, the deep groove structure is located in the sealing ring.
In an embodiment of the present invention, the deep trench structure is processed by etching or laser process.
In an embodiment of the present invention, the hole wall protection layer is made of a metal or a resin material.
According to another embodiment of the present invention, a method for manufacturing a deep trench structure in a chip protection structure is provided, including:
forming a deep groove structure on a wafer with a manufactured chip, and etching or laser drilling on the edge of the chip outside the sealing ring and/or the surface of the sealing ring vertically towards the silicon substrate;
and forming a hole wall protective layer in the deep groove structure, and sputtering, depositing or coating a metal or resin material in the deep groove structure.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the present invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 shows a schematic cross-sectional view of a chip structure in the prior art.
Fig. 2 shows three cracks generated by the dicing of the chip.
Fig. 3 shows a cross-sectional schematic view of a chip protection architecture 300 according to an embodiment of the invention.
Fig. 4 illustrates an effect of the chip protection structure 300 to block crack propagation according to an embodiment of the present invention.
Fig. 5 shows a schematic cross-sectional view of a chip protection structure 500 according to another embodiment of the invention.
Fig. 6 is a schematic diagram illustrating the effect of the chip protection structure 500 on resisting crack propagation according to another embodiment of the present invention.
Fig. 7 shows a schematic cross-sectional view of a chip protection architecture 700 according to yet another embodiment of the invention.
Fig. 8 is a schematic diagram illustrating the effect of the chip protection structure 700 on blocking crack propagation according to still another embodiment of the present invention.
Fig. 9 illustrates a flow diagram for forming a chip protection structure 300 according to an embodiment of the invention.
Detailed Description
In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that, in the embodiments of the present invention, the process steps are described in a specific order, however, this is only for convenience of distinguishing the steps, and the order of the steps is not limited, and in different embodiments of the present invention, the order of the steps may be adjusted according to the adjustment of the process.
FIG. 1 is a cross-sectional view of a chip structure in the prior art; fig. 2 shows three cracks generated by the dicing of the chip. As shown in fig. 1 and fig. 2, the chip structure 100 of the prior art cannot effectively prevent the crack 202 generated in the chip substrate oxide layer 120 and the crack 203 generated in the silicon substrate 130 from expanding from the scribe line 113 to the chip active region 111. In order to solve the technical problem, the invention provides a chip protection structure which can effectively prevent cracks from expanding to an effective area of a chip through manufacturing a deep groove structure. Meanwhile, the structure is simple in processing technology and easy to realize.
Fig. 3 shows a cross-sectional schematic view of a chip protection architecture 300 according to an embodiment of the invention. The chip protection structure 300 includes a first deep trench structure 315 and a second deep trench structure 316 disposed on the chip; the chip comprises a chip area 310, a substrate oxidation layer 320 and a silicon substrate 330, wherein the chip area 310 comprises an effective area 311 and a sealing ring 312; the seal ring includes a crack stop block 314; the first deep trench structure 315 penetrates through the chip region 310 and the substrate oxide layer 320 below the corresponding position of the seal ring 312 to the inside of the silicon substrate 330; the second deep trench structure 316 is located on one side of the scribe line 313 close to the seal ring 312, and penetrates through the chip region 310 and the substrate oxide layer 320 below the corresponding position to reach the inside of the silicon substrate 330; the first deep trench structure 315 and the second deep trench structure 316 have a hole wall protection layer 317 therein. Fig. 4 is a schematic diagram illustrating the effect of the chip structure 300 in resisting crack propagation, as shown in fig. 4, after the cracks 401, 402, and 403 generated on the chip propagate to the deep trench structure 316, they cannot continue to propagate to the chip active region 311, and thus the chip is effectively protected.
In one embodiment of the present invention, the first deep trench structure 315 and the second deep trench structure 316 are formed by etching or laser processing.
In another embodiment of the present invention, the hole wall protection layer 317 is made of metal or resin material.
Fig. 5 is a schematic cross-sectional view of a chip protection structure 500 according to another embodiment of the present invention, and in a difference from the embodiment shown in fig. 3, the chip protection structure 500 includes only one deep trench structure 516 located at a position of the scribe line 513 near the seal ring, and the deep trench structure 516 penetrates through the chip region 510 and the substrate oxide layer 520 below the corresponding position to an inside of the silicon substrate 530. Fig. 6 is a schematic diagram illustrating the effect of the chip protection structure 500 in resisting crack propagation according to another embodiment of the present invention, as shown in fig. 6, after the cracks 601, 602, and 603 generated on the chip propagate to the deep groove mechanism 516, they cannot continue to propagate to the chip active region 511, so as to provide effective protection for the chip.
Fig. 7 is a schematic cross-sectional view of a chip protection structure 700 according to another embodiment of the invention, which differs from the embodiment shown in fig. 3 in that the chip protection structure 700 includes only one deep trench structure 715 at the seal ring 712, and the deep trench structure 715 penetrates through the chip region 710 and the substrate oxide layer 720 below the corresponding position to the inside of the silicon substrate 730. Fig. 8 is a schematic diagram illustrating the effect of the chip structure 700 in resisting crack propagation according to still another embodiment of the present invention, and as shown in fig. 8, after the cracks 801, 802, 803 generated on the chip propagate to the deep trench structure 715, the cracks cannot continue to propagate to the chip active area 711, so as to provide effective protection for the chip.
Fig. 9 illustrates a flow diagram for forming a chip protection structure 300 according to an embodiment of the invention.
First, in step 901, a first deep trench structure and a second deep trench structure are formed. The first deep groove structure is formed by vertically etching or laser drilling from the surface of one side, close to the sealing ring, of the chip cutting channel to the silicon substrate, and penetrates through the chip area and the substrate oxidation layer below the corresponding position to the inside of the substrate.
Next, in step 902, a metal or resin is sputtered, deposited or coated inside the first deep trench structure and the second deep trench structure to form a hole wall protection layer.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (10)
1. A chip protection structure comprising a deep trench structure disposed in a chip, the chip comprising:
a chip region having an active area and a seal ring;
a base oxide layer disposed below the chip region; and
a silicon substrate disposed below the substrate oxide layer;
the deep groove structure penetrates through the chip area and the substrate oxide layer until the inside of the silicon substrate, and a hole wall protection layer is arranged inside the deep groove structure.
2. The chip protection structure of claim 1, wherein said deep trench structure has two, one located at the chip edge outside said seal ring and the other located in said seal ring.
3. The chip protection structure of claim 1, wherein said deep trench structure is located at an edge of the chip outside of said seal ring.
4. The chip protection structure of claim 1, wherein said deep trench structure is located in said seal ring.
5. The chip protection structure according to claim 1, 2, 3 or 4, wherein said deep trench structure is processed by etching or laser process.
6. The chip protection structure according to claim 1, 2, 3 or 4, wherein the hole wall protection layer is a metal or resin material.
7. A method for manufacturing a chip protection structure comprises the following steps:
forming a deep groove structure on the wafer with the manufactured chip; and
and forming a hole wall protection layer in the deep groove structure.
8. The method of claim 7, wherein the deep groove structure has two, one at the edge of the dicing groove outside the chip sealing ring and one in the chip sealing ring.
9. The method of claim 7, wherein the deep groove structure is located at a cut groove edge outside the chip seal ring or in the chip seal ring.
10. The method of claim 7, wherein the forming of the pore wall protection layer is forming a metal layer on the pore wall or coating a resin material on the pore wall.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910981695.9A CN110690160A (en) | 2019-10-16 | 2019-10-16 | Chip protection structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910981695.9A CN110690160A (en) | 2019-10-16 | 2019-10-16 | Chip protection structure and manufacturing method thereof |
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| CN110690160A true CN110690160A (en) | 2020-01-14 |
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| CN201910981695.9A Pending CN110690160A (en) | 2019-10-16 | 2019-10-16 | Chip protection structure and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022110935A1 (en) * | 2020-11-26 | 2022-06-02 | 苏州矽锡谷半导体科技有限公司 | Cutting method for semiconductor chip |
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| CN1770432A (en) * | 2004-09-13 | 2006-05-10 | 台湾积体电路制造股份有限公司 | Seal ring structure for integrated circuit chips |
| CN102110696A (en) * | 2009-11-30 | 2011-06-29 | 索尼公司 | Solid-state imaging device, method for manufacturing solid-state imaging device, method for manufacturing solid-state imaging element, and semiconductor device |
| CN102655127A (en) * | 2011-03-01 | 2012-09-05 | 中芯国际集成电路制造(上海)有限公司 | Chip protecting structure and forming method |
| CN103854964A (en) * | 2012-11-30 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Method for improving wafer internal stress of trench gate discrete power device |
| CN105448866A (en) * | 2014-08-20 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and manufacturing method thereof |
| CN109119481A (en) * | 2018-09-04 | 2019-01-01 | 盛世瑶兰（深圳）科技有限公司 | A kind of chip and preparation method thereof |
| CN209087831U (en) * | 2018-11-21 | 2019-07-09 | 长鑫存储技术有限公司 | Wafer and semiconductor devices |
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2019
- 2019-10-16 CN CN201910981695.9A patent/CN110690160A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1734764A (en) * | 2004-07-15 | 2006-02-15 | 台湾积体电路制造股份有限公司 | Semiconductor device with crack prevention ring and method of manufacture thereof |
| CN1770432A (en) * | 2004-09-13 | 2006-05-10 | 台湾积体电路制造股份有限公司 | Seal ring structure for integrated circuit chips |
| CN102110696A (en) * | 2009-11-30 | 2011-06-29 | 索尼公司 | Solid-state imaging device, method for manufacturing solid-state imaging device, method for manufacturing solid-state imaging element, and semiconductor device |
| CN102655127A (en) * | 2011-03-01 | 2012-09-05 | 中芯国际集成电路制造(上海)有限公司 | Chip protecting structure and forming method |
| CN103854964A (en) * | 2012-11-30 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Method for improving wafer internal stress of trench gate discrete power device |
| CN105448866A (en) * | 2014-08-20 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and manufacturing method thereof |
| CN109119481A (en) * | 2018-09-04 | 2019-01-01 | 盛世瑶兰（深圳）科技有限公司 | A kind of chip and preparation method thereof |
| CN209087831U (en) * | 2018-11-21 | 2019-07-09 | 长鑫存储技术有限公司 | Wafer and semiconductor devices |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022110935A1 (en) * | 2020-11-26 | 2022-06-02 | 苏州矽锡谷半导体科技有限公司 | Cutting method for semiconductor chip |
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Application publication date: 20200114 |