CN105448866A - Semiconductor device structure and manufacturing method thereof - Google Patents
Semiconductor device structure and manufacturing method thereof Download PDFInfo
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- CN105448866A CN105448866A CN201410410171.1A CN201410410171A CN105448866A CN 105448866 A CN105448866 A CN 105448866A CN 201410410171 A CN201410410171 A CN 201410410171A CN 105448866 A CN105448866 A CN 105448866A
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Abstract
The invention provides a semiconductor device structure and a manufacturing method thereof. The semiconductor device structure at least comprises a semiconductor substrate, a metallic layer, and a metallic column. The surface of the semiconductor substrate comprises a chip region and a virtual graphic region. The metallic layer is formed on the semiconductor substrate and comprises a metallic interconnection structure, a virtual graphic structure, and a sealing ring structure. The metallic interconnection structure is located over the chip structure and comprises a contact plug and a metallic wiring structure. The virtual graphic structure is located over the virtual graphic region. The sealing ring structure is located between the chip region and the virtual graphic region. The metallic column is formed between the sealing ring structure and the chip region or between the sealing ring structure and the virtual graphic region. Both ends of the metallic column at least extend to be aligned with the metallic wiring structure. The metallic column disposed in the semiconductor device structure effectively stops a crack, generated when a silicon chip is cut, from entering the metallic interconnection structure in the chip region.
Description
Technical field
The present invention relates to a kind of technical field of semiconductors, particularly relate to a kind of semiconductor device structure and preparation method thereof.
Background technology
Along with the development of integrated circuit technology, in order to reduce the dielectric constant of interlayer dielectric layer, more and more use low-K material (advanced low-k materials) as interlayer dielectric layer.And low-K material has poor adhesiveness and weak mechanical strength usually.Therefore, in the process of carrying out wafer scribe, easily in low-K material, there is crackle.
As shown in Figure 1, be metal interconnect structure common in existing integrated circuit technology.Wherein, comprise Semiconductor substrate 100, described Semiconductor substrate 100 comprises chip region 51 and virtual pattern district 53, and the sealing ring district 52 between described chip region 51 and virtual pattern district 53.
The top of described Semiconductor substrate 100 is formed with metal level, and described metal level comprises: interlayer dielectric layer 200 and the metal structure being arranged in described interlayer dielectric layer.Be formed with the Primary Component of described chip in the Semiconductor substrate 100 of described chip region 51 correspondence, having in corresponding metal level to have in corresponding metal level above virtual pattern structure 203 and described sealing ring district 52 above metal interconnect structure 201, described virtual pattern district 53 above described chip region 51 has seal ring structure 202 in corresponding metal level.
In addition, the weld pad 400 that described metal level also comprises passivation layer 300 and is formed in described passivation layer 300, described weld pad 400 is connected with described metal structure.
Described seal ring structure 202 can prevent electrostatic on the impact of chip region 51, and machinery can be avoided to switch to chip region 51, and prevent steam or other contaminative, corrosive factor enters chip region 51.
As shown in Figure 2, when cut crystal, cutter, along Cutting Road 700 cut crystal being positioned at virtual pattern district 53, make wafer-separate.And in said structure, the stress that cutting produces can make the interlayer dielectric layer 200 of the use low-K material being arranged in Cutting Road 700 edge crack 500.As shown in FIG., described crackle 500 also very can along dielectric material Es-region propagations such as the interlayer dielectric layer 200 of the use low-K material in metal level and passivation layers 300, finally propagate in described chip region 51, make chip internal crack even levels and be separated, cause chip failure.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of semiconductor device structure and preparation method thereof, for solving the problem that stress that in prior art, cutting produces when cut crystal can make the low-K material layer being arranged in Cutting Road edge crack.
For achieving the above object and other relevant objects, technical scheme of the present invention provides a kind of semiconductor device structure, and described semiconductor device structure at least comprises:
Semiconductor substrate, the surface of described Semiconductor substrate comprises chip region and virtual pattern district, wherein, is provided with Cutting Road in described virtual pattern district;
Metal level, described metal level is formed on a semiconductor substrate, comprising metal interconnect structure, virtual pattern structure and seal ring structure;
Described metal interconnect structure is positioned at above described chip region, comprises contact plunger and metal wiring structure, and described contact plunger is positioned at described semiconductor substrate surface, and described metal wiring structure is positioned on institute's contact plunger;
Described virtual pattern structure is positioned at above described virtual pattern district, and described seal ring structure is between described chip region and virtual pattern district;
Metal column, described metal column is formed between described seal ring structure and chip region, or is formed between described seal ring structure and described virtual pattern district, and the two ends of described metal column at least extend to and flush with described metal wiring structure.
Preferably, described metal level also comprises interlayer dielectric layer, and described metal interconnect structure, virtual pattern structure and seal ring structure are arranged in described interlayer dielectric layer.
Preferably, the material of described contact plunger is tungsten, and the material of described metal wiring structure is copper.
Preferably, described metal level also comprises the passivation layer be formed on described interlayer dielectric layer, metal interconnect structure, virtual pattern structure and seal ring structure and the weld pad be formed in described passivation layer, described weld pad is connected with described metal interconnect structure, and the material of described metal column is identical with the material of described weld pad.
Preferably, the upper surface flush of described metal column upper surface and described weld pad.
Preferably, the base section of described metal column embeds described Semiconductor substrate.
Preferably, the width of described metal column is 2.5 μm ~ 3.5 μm.
Preferably, described interlayer dielectric layer is low-K material layer.
Accordingly, technical scheme of the present invention additionally provides a kind of manufacture method of semiconductor device, and the manufacture method of described semiconductor device at least comprises:
There is provided Semiconductor substrate, the surface of described Semiconductor substrate comprises chip region and virtual pattern district, wherein, is provided with Cutting Road in described virtual pattern district;
Form metal level on the semiconductor substrate, described metal level is formed on a semiconductor substrate, comprising interlayer dielectric layer and the metal interconnect structure be positioned among described interlayer dielectric layer, virtual pattern structure and seal ring structure, and described metal interconnect structure is positioned at above described chip region, comprise contact plunger and metal wiring structure, described contact plunger is positioned at described semiconductor substrate surface, described metal wiring structure is positioned on institute's contact plunger, described virtual pattern structure is positioned at above described virtual pattern district, described seal ring structure is between described chip region and virtual pattern district,
Described metal level is formed the first passivation layer;
Photoetching and etching technics is utilized to etch described first passivation layer between described seal ring structure and virtual pattern structure and described interlayer dielectric layer, to form the through hole run through in described first passivation layer and described interlayer dielectric layer, the bottom of described through hole at least flushes with the bottom of described metal wiring structure;
Metal is filled to form metal column in described through hole.
Preferably, the opening forming weld pad figure in described first passivation layer is also included in when described first passivation layer utilizing photoetching and etching technics to etch between described seal ring structure and virtual pattern structure; Fill metal in described through hole while, be also included in the opening of described weld pad figure and fill metal.
Preferably, the metal of filling in the opening and described through hole of described weld pad figure is aluminium.
Preferably, fill metal in the opening of described through hole and described weld pad figure after, also comprise step: utilize etching technics to remove the unnecessary metal of the overthe openings of described through hole and weld pad figure, to form described metal column and weld pad.
Preferably, utilize etching technics remove the step of the unnecessary metal of the overthe openings of described through hole and weld pad figure after also comprise step: above described first passivation layer, described metal column and described weld pad, form the second passivation layer.
Preferably, the width of described through hole is 2.5 μm ~ 3.5 μm.
Preferably, being formed in the step of described through hole, also comprise step: etching described through hole to exposing described Semiconductor substrate; Etch the segment thickness of the described Semiconductor substrate that described via bottoms exposes.
Preferably, the technique forming interlayer dielectric layer is on the semiconductor substrate: form low-K material layer on the semiconductor substrate.
As mentioned above, semiconductor device structure of the present invention and preparation method thereof, has following beneficial effect:
In the semiconductor device structure provided in technical scheme of the present invention, by between described seal ring structure and metal interconnect structure, or between described seal ring structure and virtual pattern structure, metal column is set, the two ends of described metal column at least extend to and flush with described metal wiring structure, effectively can stop that crack enters into the metal interconnect structure on chip region, thus can effectively prevent when cutting silicon wafer, the gravitation that cutting produces is propagated around metal structure always, finally cause chip layering to be lost efficacy, even depart from.
Accompanying drawing explanation
Fig. 1 to Fig. 2 is shown as the schematic diagram of semiconductor device structure of the prior art.
Fig. 3 is shown as the schematic diagram of the semiconductor device structure provided in prior art.
Fig. 4 to Fig. 8 is shown as the schematic diagram of the semiconductor device structure provided in embodiments of the invention.
Element numbers explanation
100 Semiconductor substrate
51 chip region
52 sealing ring districts
53 virtual pattern districts
200 interlayer dielectric layers
201 metal interconnect structures
202 seal ring structures
203 virtual pattern structures
300 passivation layers
400 weld pads
500 crackles
700 Cutting Roads
S1 ~ S5 step
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 3.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Present embodiments provide a kind of semiconductor device structure, time to prevent cut crystal, crackle is diffused in chip region 51, causes the mode of chip failure.
As shown in Figure 3, at least comprise at described semiconductor device structure:
Semiconductor substrate 100, the surface of described Semiconductor substrate 100 comprises chip region 51, sealing ring district 52 and virtual pattern district 53.Be virtual pattern district 53 in the periphery of described chip region 51, described sealing ring district 52 is between described chip region 51 and virtual pattern district 53.Wherein, Cutting Road 700 is provided with in described virtual pattern district 53.
In the present embodiment, described Semiconductor substrate 100 can be the Semiconductor substrate such as silicon substrate, three or five compounds of group substrates, diamond substrate, SOI substrate, is wherein formed with the device layer as semiconductor device such as resistance, electric capacity, MOS transistor, memories.
The Cutting Road 700 arranged in described virtual pattern district 53, be suitable for after metal level is formed, before encapsulation, the position along described Cutting Road 700 is cut wafer, to be suitable for single chip to be separated from wafer, thus the integrated circuit (IC) chip that packed formation is complete.
The corresponding seal ring structure in described sealing ring district 52 202 (follow-up introduction) on the surface of described Semiconductor substrate 100.
Described Semiconductor substrate 100 is also formed with metal level.Described metal level comprises: interlayer dielectric layer 200 and the metal structure being arranged in described interlayer dielectric layer 200.
Described metal structure comprises metal interconnect structure 201, virtual pattern structure 203 and seal ring structure 202.As shown in FIG., metal structure in described interlayer dielectric layer 200 above described chip region 51 is metal interconnect structure 201, metal structure in described interlayer dielectric layer 200 in described virtual pattern district 53 is virtual pattern structure 203, metal structure in described interlayer dielectric layer 200 in described sealing ring district 52 is seal ring structure 202, and namely described seal ring structure 202 is between described chip region and virtual pattern district 53; Wherein, described metal interconnect structure 201 is connect the semiconductor device in the Semiconductor substrate of chip region 51 correspondence, to realize its electrical functions.Concrete, described metal interconnect structure 201 comprises contact plunger and metal wiring structure, described contact plunger is positioned at described semiconductor substrate surface, described contact plunger is suitable for connecting the active area in described device layer, as the two poles of the earth of resistance or electric capacity, or the source region of MOS transistor, drain region or gate surface etc.; Described metal wiring structure is positioned on institute's contact plunger.
Described seal ring structure 202 can prevent electrostatic on the impact of chip region 51, and machinery can be avoided to switch to chip region 51, and prevent steam or other contaminative, corrosive factor enters chip region 51.
Described virtual pattern structure 203 is filled up above the non-chip region of semiconductor substrate surface, to ensure above Semiconductor substrate 100 consistent in density of metal structure everywhere, thus avoid needing to carry out at subsequent technique local large concave surface is produced at these to the cmp of metal, thus cause the residual of metal, produce and lost efficacy, and then ensure the uniformity of cmp.
In the present embodiment, the height of whole metal level is 7.5 μm ~ 8.5 μm, and metal interconnect structure 201 is less than or equal to 8.5 μm with the distance of seal ring structure 202, and the distance between seal ring structure 202 and virtual pattern structure 203 is less than or equal to 4 μm.
Described interlayer dielectric layer 200 is filled between metal structure, as insulating material and backing material.General, the material of interlayer dielectric layer 200 is silica, phosphorus silicon compound or low K organo-silicon compound etc.In the present embodiment, the material of the described interlayer dielectric layer 200 between described contact plunger is the dielectric material as silica, phosphorus silicon compound etc., and the material of described interlayer dielectric layer 200 between described metal wiring structure is low-K material layer (dielectric constant K is less than 3), as fluorine silica, silicon oxide carbide or nano-structure porous silicon etc.Along with semiconductor technology enters deep sub-micron era, along with the reduction of very lagre scale integrated circuit (VLSIC) characteristic size and the increase of the metal interconnected number of plies, the power consumption that parasitic capacitance produces and time delay also increase.Because the dielectric constant K of low-K material layer is less than 3, utilize low-K material layer to be filled between metal wiring structure can to effectively reduce interconnection capacitance as interlayer dielectric layer, the performance of integrated circuit interconnection system can be improved significantly.Low-K material layer is adopted to become during semiconductor technology is produced the means commonly used with the problem solving above-mentioned interconnect delay as interlevel dielectric material.
Those skilled in the art are it is understood that the adhesiveness between unlike material can be far short of what is expected compared to the adhesiveness between same material inside, therefore the density difference of adjacent two kinds of materials is larger, and the adhesiveness between two kinds of materials is also poorer.In the present embodiment, described interlayer dielectric layer 200 is two kinds of materials with metal.And metal structure is very fine and close, mechanical strength is comparatively large, and the quality of relative described interlayer dielectric layer 200 is more sparse, and mechanical strength is also lower, and the adhesiveness thus between described metal structure and interlayer dielectric layer 200 can unusual difference.And when cutting wafer, shearing force (shearstress) can produce stress, these stress can discharge along the hierarchical structure that chip is the weakest.Thus, interface between metal structure and interlayer dielectric layer, described interlayer dielectric layer particularly between metal wiring structure is the low-K material layer that mechanical strength is lower, and the interface between described metal wiring structure and interlayer dielectric layer easily becomes the breach of Stress Release.Thus the stress cutting generation is easier along low-K material Es-region propagations, even can propagate around metal wiring structure time serious always, finally causes chip layering to be lost efficacy, even departs from.
In addition, described metal level also comprises passivation layer 300 and the weld pad 400 be formed in described passivation layer 300.Described weld pad 400 is connected with described metal line, is suitable for bond wire line, thus realizes the connection of metal line and pin.
Metal column 410, described metal column 410 is formed between described seal ring structure 202 and metal interconnect structure 201, or be formed in (illustrate and be formed between described seal ring structure 202 and metal interconnect structure 201 for described metal column 410, the situation that described metal column 410 is formed between described seal ring structure 202 and virtual pattern structure 203 is similar) between described seal ring structure 202 and virtual pattern structure 203.The upper surface flush of described metal column 410 upper surface and described weld pad 400.Preferably, the bottom of described metal column 410 embeds described Semiconductor substrate 100.In the present embodiment, the width of described metal column 410 is 2.5 μm ~ 3.5 μm.
In the present embodiment, owing to adding described metal column 410, the crack formed time described metal column 410 can stop cutting enters into the metal interconnect structure 201 on chip region 51, also would not produce inefficacy.
Verify by experiment, the crack formed when cutting to be appeared in more top metal level.Concrete, described crack can along the interface between metal and interlayer dielectric layer, or completely along the low-K material Es-region propagations as interlayer dielectric layer.And the upper surface flush of described metal column 410 upper surface and described weld pad 400.Can stop that crackle conducts to chip region 51 through the interface weld pad and metal wire completely.
In addition, due to the difference (different vertical direction stress can be produced) of metal level, thickness, density, the path of the release of stress is also different, the two ends of metal column 410 at least extend to and flush with the two ends up and down of described metal wiring structure, even also can the bottom of described metal column 410 be embedded in described Semiconductor substrate, chip region 51 can be conducted to by crackle preventing all sidedly.
In addition, the present embodiment additionally provides a kind of manufacture method of semiconductor device, and shown in figure 4, the manufacture method of described semiconductor device at least comprises:
First, step S1 is performed: shown in figure 5, provide Semiconductor substrate, the surface of described Semiconductor substrate comprises chip region 51, sealing ring district 52 and virtual pattern district 53, wherein, is provided with Cutting Road 700 in described virtual pattern district;
In the present embodiment, described Semiconductor substrate 100 can be the Semiconductor substrate such as silicon substrate, three or five compounds of group substrates, diamond substrate, SOI substrate.Those skilled in the art are accessible is, described Semiconductor substrate 100 comprises device layer (not shown), and have in the described device layer of corresponding described chip region 51 and to be formed by the semiconductor FEOL such as doping, deposition, photoetching and etching, comprise as semiconductor device such as resistance, electric capacity, MOS transistor, memories.
Described Semiconductor substrate 100 also comprises the contact layer (not shown) be positioned on device layer, and described contact layer utilizes Damascus technics to be formed, comprising the contact plunger be formed on device layer and the insulating barrier be filled between described contact plunger.Described contact plunger is suitable for connecting the active area in described device layer, as the two poles of the earth of resistance or electric capacity, or the source region of MOS transistor, drain region or gate surface etc.Described insulating barrier is suitable for supporting described contact plunger.
Next, perform step S2: shown in figure 6, described Semiconductor substrate 100 forms metal interconnecting layer, described metal interconnecting layer comprises seal ring structure 202, in the described interlayer dielectric layer of described seal ring structure 202 between described chip region and described virtual pattern district 53, concrete described seal ring structure 202 correspondence be described sealing ring district 52 in described Semiconductor substrate 100;
Described metal interconnecting layer adopts Damascus or dual damascene process to be formed.Wherein a kind of execution mode is: form interlayer dielectric layer on the semiconductor substrate, utilize photoetching and etching technics in described interlayer dielectric layer, form the opening comprising every layer of metal structure figure, plated metal in the opening of described metal structure figure again, to form every layer of metal structure; Wherein, the metal deposited is mainly copper.
Wherein, described metal structure comprises the described metal interconnect structure 201 in the described interlayer dielectric layer laid respectively on chip region, the virtual pattern structure 203 being arranged in the described interlayer dielectric layer in described virtual pattern district 53 and seal ring structure 202, in the described interlayer dielectric layer of wherein said seal ring structure 202 between described metal interconnect structure 201 and virtual pattern structure 203.
Its technology is known for those skilled in the art, and concrete structure as mentioned before, no longer elaborates at this.
Next, step S3 is performed: shown in figure 7, described metal interconnecting layer forms the first passivation layer 301;
Described first passivation layer 301 is silicon nitride or silicon oxynitride layer, and generation type is deposition.
Next, perform step S4: continue with reference to shown in figure 7, photoetching and etching technics is utilized to etch described first passivation layer 301 between described seal ring structure 202 and virtual pattern structure 203 and described interlayer dielectric layer 200, to form the through hole 41 running through described first passivation layer 301 and described interlayer dielectric layer 200;
In the conventional technology, described first passivation layer 301 can completely cut off moisture and invade metal level, and protects and support the weld pad formed in subsequent technique.In the operation of similar step, in the first passivation layer 301, photoetching and etching technics is only utilized to form the opening 40 of weld pad figure.
In the present embodiment, also comprise when utilizing photoetching and etching technics to form opening 40 of weld pad figure in the first passivation layer 301 and utilize photoetching and etching technics to etch described first passivation layer 301 between described seal ring structure 202 and virtual pattern structure 203, to form the through hole 41 running through described first passivation layer 301 and described interlayer dielectric layer 200.
Next, step S5 is performed: shown in figure 8, in described through hole 40, fill metal, to form the metal column 410 running through described first passivation layer 301 and described interlayer dielectric layer 200.
In the present embodiment, in this step, in the opening 41 and described through hole 40 of described weld pad figure, fill metal, to form weld pad 400 and metal column 410, the metal material of described filling is aluminium simultaneously.In other embodiments, also other metal can be filled in described through hole 40, as copper, tungsten, molybdenum, titanium etc.
In addition, continue with reference to shown in figure 8, in the present embodiment, after executing described step S5, also comprise and form passivation material layer again, to form with described first passivation layer the passivation layer 300 covering and support described metal column 410 and weld pad 400 upper end.
In the present embodiment, due at described seal ring structure 202 and metal interconnect structure 201, or between described seal ring structure 202 and virtual pattern structure 203, define metal column 410, in subsequent technique, when cutting along Cutting Road 700 pairs of wafers, effectively can stop that crack enters into the metal interconnect structure 201 on chip region.
In sum, in semiconductor device structure provided by the invention, by between described seal ring structure 202 and metal interconnect structure 201, or between described seal ring structure 202 and virtual pattern structure 203, metal column 410 is set, the two ends of described metal column 410 at least extend to and flush with described metal wiring structure, effectively can stop that crack enters into the metal interconnect structure 201 on chip region, thus can effectively prevent when cutting silicon wafer, the gravitation that cutting produces is propagated around metal structure always, chip layering is finally caused to be lost efficacy, even depart from.So in the manufacture method of semiconductor device provided by the invention, the formation of described metal column 410 together with the formation of weld pad, can not increase new technique.The present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (16)
1. a semiconductor device structure, is characterized in that, described semiconductor device structure at least comprises:
Semiconductor substrate, the surface of described Semiconductor substrate comprises chip region and virtual pattern district, wherein, is provided with Cutting Road in described virtual pattern district;
Metal level, described metal level is formed on a semiconductor substrate, comprising metal interconnect structure, virtual pattern structure and seal ring structure;
Described metal interconnect structure is positioned at above described chip region, comprises contact plunger and metal wiring structure, and described contact plunger is positioned at described semiconductor substrate surface, and described metal wiring structure is positioned on institute's contact plunger;
Described virtual pattern structure is positioned at above described virtual pattern district, and described seal ring structure is between described chip region and virtual pattern district;
Metal column, described metal column is formed between described seal ring structure and chip region, or is formed between described seal ring structure and described virtual pattern district, and the two ends of described metal column at least extend to and flush with described metal wiring structure.
2. semiconductor device structure according to claim 1, is characterized in that: described metal level also comprises interlayer dielectric layer, and described metal interconnect structure, virtual pattern structure and seal ring structure are arranged in described interlayer dielectric layer.
3. semiconductor device structure according to claim 1, is characterized in that: the material of described contact plunger is tungsten, and the material of described metal wiring structure is copper.
4. semiconductor device structure according to claim 2, it is characterized in that: described metal level also comprises the passivation layer be formed on described interlayer dielectric layer, metal interconnect structure, virtual pattern structure and seal ring structure and the weld pad be formed in described passivation layer, described weld pad is connected with described metal interconnect structure, and the material of described metal column is identical with the material of described weld pad.
5. semiconductor device structure according to claim 4, is characterized in that: the upper surface flush of described metal column upper surface and described weld pad.
6. semiconductor device structure according to claim 1, is characterized in that: the base section of described metal column embeds described Semiconductor substrate.
7. semiconductor device structure according to claim 1, is characterized in that: the width of described metal column is 2.5 μm ~ 3.5 μm.
8. semiconductor device structure according to claim 1, is characterized in that: described interlayer dielectric layer is low-K material layer.
9. a manufacture method for semiconductor device, is characterized in that: the manufacture method of described semiconductor device at least comprises:
There is provided Semiconductor substrate, the surface of described Semiconductor substrate comprises chip region and virtual pattern district, wherein, is provided with Cutting Road in described virtual pattern district;
Form metal level on the semiconductor substrate, described metal level is formed on a semiconductor substrate, comprising interlayer dielectric layer and the metal interconnect structure be positioned among described interlayer dielectric layer, virtual pattern structure and seal ring structure, and described metal interconnect structure is positioned at above described chip region, comprise contact plunger and metal wiring structure, described contact plunger is positioned at described semiconductor substrate surface, described metal wiring structure is positioned on institute's contact plunger, described virtual pattern structure is positioned at above described virtual pattern district, described seal ring structure is between described chip region and virtual pattern district,
Described metal level is formed the first passivation layer;
Photoetching and etching technics is utilized to etch described first passivation layer between described seal ring structure and virtual pattern structure and described interlayer dielectric layer, to form the through hole run through in described first passivation layer and described interlayer dielectric layer, the bottom of described through hole at least flushes with the bottom of described metal wiring structure;
Metal is filled to form metal column in described through hole.
10. the manufacture method of semiconductor device according to claim 9, it is characterized in that: during described first passivation layer utilizing photoetching and etching technics to etch between described seal ring structure and virtual pattern structure, be also included in the opening forming weld pad figure in described first passivation layer; Fill metal in described through hole while, be also included in the opening of described weld pad figure and fill metal.
The manufacture method of 11. semiconductor device according to claim 10, is characterized in that: the metal of filling in the opening and described through hole of described weld pad figure is aluminium.
The manufacture method of 12. semiconductor device according to claim 10, it is characterized in that: fill metal in the opening of described through hole and described weld pad figure after, also comprise step: utilize etching technics to remove the unnecessary metal of the overthe openings of described through hole and weld pad figure, to form described metal column and weld pad.
The manufacture method of 13. semiconductor device according to claim 12, is characterized in that: utilize etching technics remove the step of the unnecessary metal of the overthe openings of described through hole and weld pad figure after also comprise step: above described first passivation layer, described metal column and described weld pad, form the second passivation layer.
The manufacture method of 14. semiconductor device according to claim 9, is characterized in that: the width of described through hole is 2.5 μm ~ 3.5 μm.
The manufacture method of 15. semiconductor device according to claim 9, is characterized in that: formed in the step of described through hole, also comprise step: etch described through hole to exposing described Semiconductor substrate; Etch the segment thickness of the described Semiconductor substrate that described via bottoms exposes.
The manufacture method of 16. semiconductor device according to claim 9, is characterized in that: the technique forming interlayer dielectric layer is on the semiconductor substrate: form low-K material layer on the semiconductor substrate.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1734764A (en) * | 2004-07-15 | 2006-02-15 | 台湾积体电路制造股份有限公司 | Semiconductor device with crack prevention ring and method of manufacture thereof |
| US20100314720A1 (en) * | 2004-09-24 | 2010-12-16 | Panasonic Corporation | Electronic device and method for fabricating the same |
| US20140027928A1 (en) * | 2012-07-25 | 2014-01-30 | Renesas Electronics Corporation | Semiconductor device having crack-resisting ring structure and manufacturing method thereof |
| JP2014090012A (en) * | 2012-10-29 | 2014-05-15 | Yamaha Corp | Semiconductor wafer and semiconductor integrated circuit manufacturing method |
-
2014
- 2014-08-20 CN CN201410410171.1A patent/CN105448866B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1734764A (en) * | 2004-07-15 | 2006-02-15 | 台湾积体电路制造股份有限公司 | Semiconductor device with crack prevention ring and method of manufacture thereof |
| US20100314720A1 (en) * | 2004-09-24 | 2010-12-16 | Panasonic Corporation | Electronic device and method for fabricating the same |
| US20140027928A1 (en) * | 2012-07-25 | 2014-01-30 | Renesas Electronics Corporation | Semiconductor device having crack-resisting ring structure and manufacturing method thereof |
| JP2014090012A (en) * | 2012-10-29 | 2014-05-15 | Yamaha Corp | Semiconductor wafer and semiconductor integrated circuit manufacturing method |
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| CN115050645A (en) * | 2022-08-11 | 2022-09-13 | 广州粤芯半导体技术有限公司 | Method for improving adhesive film residue on surface of wafer |
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