CN105448866B - Semiconductor device structure and preparation method thereof - Google Patents
Semiconductor device structure and preparation method thereof Download PDFInfo
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- CN105448866B CN105448866B CN201410410171.1A CN201410410171A CN105448866B CN 105448866 B CN105448866 B CN 105448866B CN 201410410171 A CN201410410171 A CN 201410410171A CN 105448866 B CN105448866 B CN 105448866B
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Abstract
The present invention provides a kind of semiconductor device structure and preparation method thereof, and the semiconductor device structure includes at least: surface includes the semiconductor substrate of chip region and virtual pattern area；Metal layer on a semiconductor substrate is formed, including metal interconnection structure, virtual pattern structure and seal ring structure；The metal interconnection structure is located above the chip region, including contact plunger and metal wiring structure；The virtual pattern structure is located above the virtual pattern area, and the seal ring structure is between the chip region and virtual pattern area；Metal column, the metal column are formed between the seal ring structure and chip region, or are formed between the seal ring structure and the virtual pattern area, and the both ends of the metal column at least extend to and flush with the metal wiring structure.In the semiconductor device structure, by the way that metal column is arranged, the crack generated when being effectively blocked in cutting silicon wafer is entered in the metal interconnection structure on chip region.
Description
Technical field
The present invention relates to a kind of technical field of semiconductors, more particularly to a kind of semiconductor device structure and its production side
Method.
Background technique
With the development of integrated circuit technology, in order to reduce the dielectric constant of interlayer dielectric layer, low K is more and more used
Material (advanced low-k materials) is used as interlayer dielectric layer.And low-K material usually has the adhesiveness and weak mechanical strength of difference.
Therefore, it during carrying out wafer scribe, is easy cracked in low-K material.
As shown in Figure 1, for common metal interconnection structure in existing integrated circuit technology.Wherein, including semiconductor serves as a contrast
Bottom 100, the semiconductor substrate 100 include chip region 51 and virtual pattern area 53, and positioned at the chip region 51 and virtually
Sealing ring region 52 between graph area 53.
The top of the semiconductor substrate 100 is formed with metal layer, and the metal layer includes: interlayer dielectric layer 200 and position
Metal structure in the interlayer dielectric layer.The chip is formed in the corresponding semiconductor substrate 100 in the chip region 51
Primary Component, corresponding in metal layer above the chip region 51 has metal interconnection structure 201, in the virtual pattern area 53
Have to correspond to above virtual pattern structure 203 and the sealing ring region 52 in the corresponding metal layer in side and has seal ring structure in metal layer
202。
In addition, the metal layer further includes passivation layer 300 and the weld pad 400 that is formed in the passivation layer 300, the weldering
Pad 400 is connected with the metal structure.
The seal ring structure 202 can prevent influence of the electrostatic to chip region 51, and can switch to core to avoid machinery
Section 51, and prevent steam or other pollutions, corrosive factor from entering chip region 51.
As shown in Fig. 2, in cut crystal, cutter along 700 cut crystal of Cutting Road for being located at virtual pattern area 53,
So that chip separates.And in said structure, the stress for cutting generation can make positioned at 700 edge of Cutting Road using low K material
500 are cracked in the interlayer dielectric layer 200 of material.As shown in the figure, the crackle 500 can also make along in metal layer very much
With the equal dielectric materials Es-region propagations of the interlayer dielectric layer 200 and passivation layer 300 of low-K material, it is eventually spread in the chip region 51,
So that chip interior cracks even upper and lower level separation, lead to chip failure.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of semiconductor device structure and its
Production method can make for solving the stress that cutting generates in cut crystal in the prior art positioned at the low of Cutting Road edge
The problem of being cracked in K material layer.
In order to achieve the above objects and other related objects, technical solution of the present invention provides a kind of semiconductor device structure,
The semiconductor device structure includes at least:
Semiconductor substrate, the surface of the semiconductor substrate include chip region and virtual pattern area, wherein the virtual graph
Shape is provided with Cutting Road in area；
Metal layer, the metal layer are formed on a semiconductor substrate, including metal interconnection structure, virtual pattern structure
And seal ring structure；
The metal interconnection structure is located above the chip region, including contact plunger and metal wiring structure, described to connect
Touching plug is located at the semiconductor substrate surface, and the metal wiring structure is located on institute's contact plunger；
The virtual pattern structure is located above the virtual pattern area, the seal ring structure be located at the chip region with
Between virtual pattern area；
Metal column, the metal column are formed between the seal ring structure and chip region, or are formed in the sealing
Between ring structure and the virtual pattern area, and the both ends of the metal column at least extend to it is neat with the metal wiring structure
It is flat.
Preferably, the metal layer further includes interlayer dielectric layer, the metal interconnection structure, virtual pattern structure and sealing
Ring structure is located in the interlayer dielectric layer.
Preferably, the material of the contact plunger is tungsten, and the material of the metal wiring structure is copper.
Preferably, the metal layer further includes being formed in the interlayer dielectric layer, metal interconnection structure, virtual pattern structure
With the passivation layer on seal ring structure and the weld pad being formed in the passivation layer, the weld pad and the metal interconnection structure phase
Even, the material of the metal column is identical as the material of the weld pad.
Preferably, the metal column upper surface is flushed with the upper surface of the weld pad.
Preferably, the bottom part of the metal column is embedded in the semiconductor substrate.
Preferably, the width of the metal column is 2.5 μm~3.5 μm.
Preferably, the interlayer dielectric layer is low-K material layer.
Correspondingly, technical solution of the present invention additionally provides a kind of production method of semiconductor devices, the semiconductor device
The production method of part includes at least:
Semiconductor substrate is provided, the surface of the semiconductor substrate includes chip region and virtual pattern area, wherein the void
Cutting Road is provided in quasi- graph area；
Metal layer is formed on the semiconductor substrate, and the metal layer is formed on a semiconductor substrate, including layer
Between dielectric layer and metal interconnection structure, virtual pattern structure and seal ring structure among the interlayer dielectric layer, and institute
It states metal interconnection structure to be located above the chip region, including contact plunger and metal wiring structure, the contact plunger are located at
The semiconductor substrate surface, the metal wiring structure are located on institute's contact plunger, and the virtual pattern structure is located at described
Above virtual pattern area, the seal ring structure is between the chip region and virtual pattern area；
The first passivation layer is formed on the metal layer；
First passivation between the seal ring structure and virtual pattern structure is etched using lithography and etching technique
Layer and the interlayer dielectric layer, with the through-hole formed in first passivation layer and the interlayer dielectric layer, the through-hole
Bottom at least flushed with the bottom of the metal wiring structure；
Fill metal in the through hole to form metal column.
Preferably, described between the seal ring structure and virtual pattern structure is etched using lithography and etching technique
It further include the opening that weld pad figure is formed in first passivation layer when one passivation layer；Metal is filled in the through hole
It meanwhile further including filling metal in the opening of the weld pad figure.
Preferably, the metal filled in the opening of the weld pad figure and the through-hole is aluminium.
Preferably, it is further comprised the steps of: after filling metal in the opening of the through-hole and the weld pad figure and utilizes etching
Technique removes the extra metal of overthe openings of the through-hole and weld pad figure, to form the metal column and weld pad.
Preferably, the overthe openings for removing the through-hole and weld pad figure using the etching technics extra metal the step of
It further comprises the steps of: later and forms the second passivation layer in the top of first passivation layer, the metal column and the weld pad.
Preferably, the width of the through-hole is 2.5 μm~3.5 μm.
Preferably, in the step of forming the through-hole, the etching through-hole is further comprised the steps of: to exposing the semiconductor
Substrate；Etch the segment thickness of the semiconductor substrate of the via bottoms exposure.
Preferably, the technique of interlayer dielectric layer is formed on the semiconductor substrate are as follows: shape on the semiconductor substrate
At low-K material layer.
As described above, semiconductor device structure and preparation method thereof of the invention, has the advantages that
In the semiconductor device structure provided in technical solution of the present invention, by mutual in the seal ring structure and metal
Link between structure, or metal column is set between the seal ring structure and virtual pattern structure, the both ends of the metal column
It at least extends to and is flushed with the metal wiring structure, the metal that can effectively stop crack to enter on chip region mutually links
In structure, so as to effectively prevent the gravitation for cutting generation when cutting silicon wafer from propagating always around metal structure, most
Lead to chip layering failure eventually, or even is detached from.
Detailed description of the invention
Fig. 1 to Fig. 2 is shown as the schematic diagram of semiconductor device structure in the prior art.
Fig. 3 is shown as the schematic diagram of the semiconductor device structure provided in the prior art.
Fig. 4 to Fig. 8 is shown as the schematic diagram of the semiconductor device structure provided in the embodiment of the present invention.
Component label instructions
100 semiconductor substrates
51 chip regions
52 sealing ring regions
53 virtual pattern areas
200 interlayer dielectric layers
201 metal interconnection structures
202 seal ring structures
203 virtual pattern structures
300 passivation layers
400 weld pads
500 crackles
700 Cutting Roads
S1~S5 step
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Please refer to Fig. 3.It should be noted that illustrating what only the invention is illustrated in a schematic way provided in the present embodiment
Basic conception, only shown in schema then with related component in the present invention rather than component count, shape when according to actual implementation
And size is drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its assembly layout
Kenel may also be increasingly complex.
A kind of semiconductor device structure is present embodiments provided, when to prevent cut crystal, crackle is diffused into chip region
In 51, cause the mode of chip failure.
As shown in figure 3, being included at least in the semiconductor device structure:
Semiconductor substrate 100, the surface of the semiconductor substrate 100 include chip region 51, seal ring region 52 and virtual graph
Shape area 53.It is virtual pattern area 53 in the periphery of the chip region 51, the sealing ring region 52 is located at the chip region 51 and void
Between quasi- graph area 53.Wherein, Cutting Road 700 is provided in the virtual pattern area 53.
In the present embodiment, the semiconductor substrate 100 can for silicon substrate, three-five compound substrate, diamond substrate,
The semiconductor substrates such as SOI substrate are formed with the device of such as resistance, capacitor, MOS transistor, memory semiconductor devices
Layer.
The Cutting Road 700 being arranged in the virtual pattern area 53, suitable for after metal layer is formed, before encapsulation, edge
The position of the Cutting Road 700 wafer is cut, be suitable for separating single chip from wafer, thus packed
Form complete IC chip.
The sealing ring region 52 on the surface of the semiconductor substrate 100 is corresponding seal ring structure 202 (subsequent introduction).
Metal layer is also formed in the semiconductor substrate 100.The metal layer includes: interlayer dielectric layer 200 and is located at
Metal structure in the interlayer dielectric layer 200.
The metal structure includes metal interconnection structure 201, virtual pattern structure 203 and seal ring structure 202.In such as figure
Shown, the metal structure in the interlayer dielectric layer 200 of 51 top of chip region is metal interconnection structure 201, the void
The metal structure in the interlayer dielectric layer 200 on quasi- graph area 53 is virtual pattern structure 203, in the sealing ring region 52
The interlayer dielectric layer 200 in metal structure be seal ring structure 202, i.e., the described seal ring structure 202 is located at the core
Between section and virtual pattern area 53；Wherein, the metal interconnection structure 201 is the connection corresponding semiconductor substrate in chip region 51
In semiconductor devices, to realize its electrical functions.Specifically, the metal interconnection structure 201 includes contact plunger and metal
Wire structures, the contact plunger are located at the semiconductor substrate surface, and the contact plunger is adapted in the device layer
Active area, such as the resistance perhaps source region of the two poles of the earth of capacitor or MOS transistor, drain region or gate surface etc.；The metal
Wire structures are located on institute's contact plunger.
The seal ring structure 202 can prevent influence of the electrostatic to chip region 51, and can switch to core to avoid machinery
Section 51, and prevent steam or other pollutions, corrosive factor from entering chip region 51.
The virtual pattern structure 203 fills up the top in the non-chip region of semiconductor substrate surface, guarantees semiconductor substrate
The consistent in density of the metal structure of 100 tops everywhere, to avoid the chemical machinery to metal for needing to carry out in subsequent technique
It grinds and generates big concave surface in these places, to cause the residual of metal, generate failure, and then guarantee chemical mechanical grinding
Uniformity.
In the present embodiment, the height of entire metal layer is 7.5 μm~8.5 μm, metal interconnection structure 201 and seal ring structure
202 distance is less than or equal to 8.5 μm, and the distance between seal ring structure 202 and virtual pattern structure 203 are less than or equal to 4 μm.
The interlayer dielectric layer 200 is filled between metal structure, as insulating materials and backing material.In general, layer
Between the material of dielectric layer 200 be silica, phosphorus silicon compound or low K organo-silicon compound etc..In the present embodiment, the contact is inserted
The material of the interlayer dielectric layer 200 between plug is such as silica, the general dielectric material of phosphorus silicon compound, and the gold
The material for belonging to the interlayer dielectric layer 200 between wire structures is low-K material layer (dielectric constant K is less than 3), as fluorine aoxidizes
Silicon, silicon oxide carbide or nano-structure porous silicon etc..As semiconductor technology enters deep sub-micron era, with super large-scale integration
The reduction of characteristic size and the increase of metal interconnecting layer number, the power consumption and delay that parasitic capacitance generates also increase.Due to low-K material
For the dielectric constant K of layer less than 3, being filled between metal wiring structure using low-K material layer as interlayer dielectric layer can be effective
Reduction interconnection capacitance, can significantly improve the performance of integrated circuit interconnection system.Using low-K material layer as inter-level dielectric
Material is to solve the problems, such as that above-mentioned interconnection delay has become common means in semiconductor technology production.
It will be appreciated to those of skill in the art that the adhesiveness between unlike material is compared between same substance inside
Adhesiveness can be far short of what is expected, therefore the consistency difference of adjacent two kinds of materials is bigger, and the adhesiveness between two kinds of materials is also poorer.This
In embodiment, the interlayer dielectric layer 200 and metal are two kinds of materials.And metal structure is very fine and close, mechanical strength is larger, and phase
Pair the interlayer dielectric layer 200 quality than sparse, mechanical strength is also relatively low, thus the metal structure and interlayer are situated between
Adhesiveness between matter layer 200 can be very poor.And when being cut to wafer, shearing force (shear stress) meeting
Stress is generated, these stress can be discharged along chip hierarchical structure the weakest.Thus, metal structure and interlayer dielectric layer it
Between interface, the interlayer dielectric layer especially between metal wiring structure is the relatively low low-K material layer of mechanical strength,
Interface between the metal wiring structure and interlayer dielectric layer easily becomes the breach of stress release.Thus cutting generates
Stress more easily along low-K material Es-region propagations, when serious even can be propagated always around metal wiring structure, eventually lead to core
Piece layering failure, or even be detached from.
In addition, the metal layer further includes passivation layer 300 and the weld pad 400 that is formed in the passivation layer 300.The weldering
Pad 400 is connected with the metal line, is suitable for bond wire line, to realize the connection of metal line and pin.
Metal column 410, the metal column 410 are formed between the seal ring structure 202 and metal interconnection structure 201,
Or it is formed between the seal ring structure 202 and virtual pattern structure 203 and (illustrates and institute is formed in the metal column 410
For stating between seal ring structure 202 and metal interconnection structure 201, the metal column 410 is formed in the seal ring structure 202
The case where between virtual pattern structure 203, is similar).410 upper surface of metal column and the upper surface of the weld pad 400 are neat
It is flat.Preferably, the bottom of the metal column 410 is embedded in the semiconductor substrate 100.In the present embodiment, the metal column 410
Width is 2.5 μm~3.5 μm.
In the present embodiment, due to increasing the metal column 410, the metal column 410 can stop to be formed when cutting
Crack enter in the metal interconnection structure 201 on chip region 51, would not also generate failure.
By experimental verification, the crack that cutting when is formed more is appeared in more top metal layer.Specifically,
It the crack can be along the interface between metal and interlayer dielectric layer, or completely along the low K material as interlayer dielectric layer
The bed of material is propagated.And 410 upper surface of metal column is flushed with the upper surface of the weld pad 400.Completely crackle can be stopped to be worn
The interface crossed between weld pad and metal wire is conducted to chip region 51.
In addition, due to metal level, thickness, density difference (different vertical direction stress can be generated), stress is released
The path put is also different, and the both ends of metal column 410 are at least extended to be flushed with the upper and lower ends of the metal wiring structure,
Possibly even the bottom of the metal column 410 is embedded in the semiconductor substrate, can comprehensively prevent crack conduct to
Chip region 51.
In addition, the present embodiment additionally provides a kind of production method of semiconductor devices, refering to what is shown in Fig. 4, the semiconductor
The production method of device includes at least:
Firstly, executing step S1: refering to what is shown in Fig. 5, providing semiconductor substrate, the surface of the semiconductor substrate includes core
Section 51, sealing ring region 52 and virtual pattern area 53, wherein be provided with Cutting Road 700 in the virtual pattern area；
In the present embodiment, the semiconductor substrate 100 can for silicon substrate, three-five compound substrate, diamond substrate,
The semiconductor substrates such as SOI substrate.Skilled artisans will appreciate that in the semiconductor substrate 100 (not including device layer
Diagram), and have in the device layer of the corresponding chip region 51 by before the semiconductors such as doping, deposition, lithography and etching
What segment process was formed, including such as resistance, capacitor, MOS transistor, memory semiconductor devices.
The semiconductor substrate 100 further includes the contact layer (not shown) on device layer, and the contact layer is using greatly
Ma Shige technique is formed, including the contact plunger being formed on device layer and the insulation being filled between the contact plunger
Layer.The contact plunger is adapted to the active area in the device layer, such as resistance perhaps the two poles of the earth of capacitor or MOS crystal
Source region, drain region or gate surface of pipe etc..The insulating layer is suitable for supporting the contact plunger.
Next, executing step S2: refering to what is shown in Fig. 6, metal interconnecting layer is formed in the semiconductor substrate 100, institute
Stating metal interconnecting layer includes seal ring structure 202, and the seal ring structure 202 is located at the chip region and the virtual pattern area
In the interlayer dielectric layer between 53, the specific corresponding institute in the semiconductor substrate 100 of the seal ring structure 202
State sealing ring region 52；
The metal interconnecting layer is formed using Damascus or dual damascene process.One of embodiment are as follows:
Interlayer dielectric layer is formed on the semiconductor substrate, is formed in the interlayer dielectric layer using lithography and etching technique and is included
The opening of every layer of metal structure figure, then the deposited metal in the opening of the metal structure figure, to form every layer of metal knot
Structure；Wherein, the metal deposited is mainly copper.
Wherein, the metal structure includes the metal interconnection in the interlayer dielectric layer being located on chip region
Structure 201, the virtual pattern structure 203 in the interlayer dielectric layer in the virtual pattern area 53 and seal ring structure
202, wherein the layer of the seal ring structure 202 between the metal interconnection structure 201 and virtual pattern structure 203
Between in dielectric layer.
Its technology is known to those skilled in the art, specific structure as it was noted above, no longer elaborates herein.
Next, executing step S3: refering to what is shown in Fig. 7, forming the first passivation layer 301 on the metal interconnecting layer；
First passivation layer 301 is silicon nitride or silicon oxynitride layer, and generation type is deposition.
Next, executing step S4: with continued reference to shown in Fig. 7, etching the sealing ring knot using lithography and etching technique
First passivation layer 301 and the interlayer dielectric layer 200 between structure 202 and virtual pattern structure 203 run through institute to be formed
State the through-hole 41 of the first passivation layer 301 and the interlayer dielectric layer 200；
In the conventional technology, first passivation layer 301 can completely cut off moisture intrusion metal layer, and protect and support subsequent
The weld pad formed in technique.In the operation of this similar step, lithography and etching technique shape is only utilized in the first passivation layer 301
At the opening 40 of weld pad figure.
In the present embodiment, the opening 40 of weld pad figure is formed using lithography and etching technique in the first passivation layer 301
When further include using lithography and etching technique etch it is described between the seal ring structure 202 and virtual pattern structure 203
First passivation layer 301, to form the through-hole 41 for running through first passivation layer 301 and the interlayer dielectric layer 200.
Next, executing step S5: refering to what is shown in Fig. 8, fill metal in the through-hole 40, to be formed through described the
The metal column 410 of one passivation layer 301 and the interlayer dielectric layer 200.
In the present embodiment, in this step, while gold is filled in the opening 41 of the weld pad figure and the through-hole 40
Belong to, to form weld pad 400 and metal column 410, the metal material of the filling is aluminium.It in other embodiments, can also be
Other metals, such as copper, tungsten, molybdenum, titanium are filled in the through-hole 40.
In addition, further including re-forming after having executed the step S5 in the present embodiment with continued reference to shown in Fig. 8
Passivation material layer, to cover and support the passivation of 400 upper end of the metal column 410 and weld pad with first passivation layer formation
Layer 300.
In the present embodiment, due in the seal ring structure 202 and metal interconnection structure 201, or in the sealing ring
Metal column 410 is formd between structure 202 and virtual pattern structure 203, in the subsequent process, along 700 pairs of crystalline substances of Cutting Road
Circle is when cut, in the metal interconnection structure 201 that can effectively stop crack to enter on chip region.
In conclusion in semiconductor device structure provided by the invention, by mutual in the seal ring structure 202 and metal
Link between structure 201, or metal column 410 is set between the seal ring structure 202 and virtual pattern structure 203, it is described
The both ends of metal column 410 are at least extended to be flushed with the metal wiring structure, effectively crack can be stopped to enter chip
In metal interconnection structure 201 in area, so as to effectively prevent from cutting when cutting silicon wafer the gravitation of generation around
Metal structure is propagated always, eventually leads to chip layering failure, or even be detached from.So semiconductor devices provided by the invention
In production method, the formation of the metal column 410 can not increase new technique together with the formation of weld pad.The present invention has
Effect overcomes various shortcoming in the prior art and has high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (12)
1. a kind of semiconductor device structure, which is characterized in that the semiconductor device structure includes at least:
Semiconductor substrate, the surface of the semiconductor substrate include chip region and virtual pattern area, wherein the virtual pattern area
In be provided with Cutting Road；
Metal layer, the metal layer is formed on a semiconductor substrate, including metal interconnection structure, virtual pattern structure and close
Seal ring structure；The metal layer further includes passivation layer and the weld pad that is formed in the passivation layer；
The metal interconnection structure is located above the chip region, including contact plunger and metal wiring structure, and the contact is inserted
Plug is located at the semiconductor substrate surface, and the metal wiring structure is located on institute's contact plunger, the weld pad and the metal
Wire structures are connected；
The virtual pattern structure is located above the virtual pattern area, and the seal ring structure is located at the chip region and virtually
Between graph area；
Metal column, the metal column are formed between the seal ring structure and chip region, and the bottom of the metal column is at least
It extending to and is flushed with the bottom of the metal wiring structure, the upper surface of the metal column is flushed with the upper surface of the weld pad,
And the metal column is formed simultaneously with the weld pad, the width of the metal column is 2.5 μm~3.5 μm, the height of the metal layer
Degree is 7.5 μm~8.5 μm, and the metal interconnection structure is less than or equal to 8.5 μm at a distance from the seal ring structure, the sealing
The distance between ring structure and the virtual pattern structure are less than or equal to 4 μm.
2. semiconductor device structure according to claim 1, it is characterised in that: the metal layer further includes inter-level dielectric
Layer, the metal interconnection structure, virtual pattern structure and seal ring structure are located in the interlayer dielectric layer.
3. semiconductor device structure according to claim 1, it is characterised in that: the material of the contact plunger is tungsten, institute
The material for stating metal wiring structure is copper.
4. semiconductor device structure according to claim 1, it is characterised in that: the material of the metal column and the weld pad
Material it is identical.
5. semiconductor device structure according to claim 1, it is characterised in that: the bottom part of the metal column is embedded in institute
State semiconductor substrate.
6. semiconductor device structure according to claim 2, it is characterised in that: the interlayer dielectric layer is low-K material layer.
7. a kind of production method of semiconductor devices, it is characterised in that: the production method of the semiconductor devices includes at least:
Semiconductor substrate is provided, the surface of the semiconductor substrate includes chip region and virtual pattern area, wherein the virtual graph
Shape is provided with Cutting Road in area；
Metal layer is formed on the semiconductor substrate, and the metal layer forms on a semiconductor substrate, is situated between including interlayer
Matter layer and metal interconnection structure, virtual pattern structure and seal ring structure among the interlayer dielectric layer, and the gold
Belong to interconnection structure to be located above the chip region, including contact plunger and metal wiring structure, the contact plunger is located at described
Semiconductor substrate surface, the metal wiring structure are located on institute's contact plunger, and the virtual pattern structure is located at described virtual
Above graph area, the seal ring structure is between the chip region and virtual pattern area；
The first passivation layer is formed on the metal layer；
First passivation layer and the layer between the seal ring structure and chip region are etched using lithography and etching technique
Between dielectric layer, to form the through-hole in first passivation layer and the interlayer dielectric layer, the bottom of the through-hole is at least
It is flushed with the bottom of the metal wiring structure；It simultaneously further include the opening that weld pad figure is formed in first passivation layer,
The opening of the weld pad figure is connected with the metal wiring structure；Metal is filled in the through hole to form metal column, together
When further include filling metal in the opening of the weld pad figure to form weld pad, the upper surface of the metal column and the weld pad
Upper surface flushes, and the width of the metal column is 2.5 μm~3.5 μm, and the height of the metal layer is 7.5 μm~8.5 μm, described
Metal interconnection structure is less than or equal to 8.5 μm at a distance from the seal ring structure, the seal ring structure and the virtual pattern
The distance between structure is less than or equal to 4 μm.
8. the production method of semiconductor devices according to claim 7, it is characterised in that: in the opening of the weld pad figure
It is aluminium with the metal filled in the through-hole.
9. the production method of semiconductor devices according to claim 7, it is characterised in that: in the through-hole and the weld pad
The overthe openings that the through-hole and weld pad figure are removed using etching technics are further comprised the steps of: after filling metal in the opening of figure
Extra metal, to form the metal column and weld pad.
10. the production method of semiconductor devices according to claim 9, it is characterised in that: removed using etching technics
Further comprised the steps of: after the step of overthe openings of the through-hole and weld pad figure extra metal first passivation layer,
The top of the metal column and the weld pad forms the second passivation layer.
11. the production method of semiconductor devices according to claim 7, it is characterised in that: the step of forming the through-hole
In, the etching through-hole is further comprised the steps of: to exposing the semiconductor substrate；Etch described the half of the via bottoms exposure
The segment thickness of conductor substrate.
12. the production method of semiconductor devices according to claim 7, it is characterised in that: on the semiconductor substrate
The technique for forming interlayer dielectric layer are as follows: form low-K material layer on the semiconductor substrate.
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| CN109935548B (en) * | 2017-12-19 | 2020-12-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN110310938A (en) * | 2018-03-20 | 2019-10-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and electronic device |
| CN110690160A (en) * | 2019-10-16 | 2020-01-14 | 上海先方半导体有限公司 | Chip protection structure and manufacturing method thereof |
| US11699663B2 (en) * | 2020-04-27 | 2023-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Passivation scheme design for wafer singulation |
| CN112510001B (en) * | 2020-11-30 | 2023-06-30 | 珠海天成先进半导体科技有限公司 | Chip structure with TSV through holes and preparation method |
| CN112885778B (en) * | 2021-01-19 | 2023-05-16 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| CN113066763B (en) * | 2021-03-24 | 2022-04-26 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| CN116504746A (en) * | 2022-01-18 | 2023-07-28 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| CN115050645A (en) * | 2022-08-11 | 2022-09-13 | 广州粤芯半导体技术有限公司 | Method for improving adhesive film residue on surface of wafer |
| CN117080163B (en) * | 2023-10-11 | 2024-02-23 | 芯耀辉科技有限公司 | Chip structure and forming method thereof, chip packaging structure and forming method thereof |
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