JP2014090012A - Semiconductor wafer and semiconductor integrated circuit manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a connection structure of an inspection pad which can be used in combination with a structure where a seal ring is substrate potential and achieve area reduction of a semiconductor integrated circuit and improvement in tamper resistance in a simple composition.SOLUTION: A semiconductor integrated circuit manufacturing method comprise: forming on a semiconductor substrate of a semiconductor wafer formed on a first conductivity type semiconductor substrate, a plurality of chip regions 10 including a semiconductor integrated circuit and scribe regions 20 among the chip regions, a second conductivity type deep well DN which crosses each dicing line DL to serve as a border between each chip region 10 and each scribe region 20 and extends from inside the chip region 10 to inside the scribe region 20; and connecting in the chip region, the deep well DN with the semiconductor integrated circuit via a wiring layer, and connecting in the scribe region 20, the deep well DN with a pad via a second conductivity type diffusion layer N2.

Description

  The present invention relates to a semiconductor integrated circuit.

  As the chip area of the semiconductor integrated circuit has been reduced, it has become difficult to provide a sufficient number of test pads in the chip region. Therefore, as shown in FIG. 3A, pads (inspection PAD 50 and control PAD 83 in FIG. 3A) used in the inspection process of the semiconductor integrated circuit are provided in the scribe region 20, and the chip region 10 In Japanese Patent Application Laid-Open No. H11-260260, it is proposed to connect to a circuit under test 52 via a MOS transistor 81 and a metal wiring 82 (see Patent Document 1: Prior Art). The scribe region 20 is cut out by dicing prior to product shipment. For this reason, if the pads used in the inspection process are provided in the scribe region 20, it is possible to conceal what signal input / output is performed in the inspection process after the product is shipped. There is also an effect of improving.

  Further, in Patent Document 1, a dicing detector 53 is provided so as to straddle the scribe region 20 and the chip region 10 as shown in FIG. A switching circuit 51 is provided in the input / output path 54 of the signal reaching the circuit to be inspected 52. When dicing is detected by the dicing detector 53, the switching circuit 51 executes processing for setting the input / output path 54 to a fixed potential. Thus, a technique for further improving tamper resistance is disclosed. On the other hand, in Patent Document 2, a diffusion layer extending from an in-chip region to a scribe region is formed below a seal ring for protecting a semiconductor integrated circuit from contamination by moisture or the like, and the in-chip region is formed using this diffusion layer. Is connected to the pads in the scribe region.

JP-A-2005-150514 JP 2010-153753 A

  However, in the technique disclosed in Patent Document 1, it is necessary to separately provide a dicing detector and a switching circuit, and there is a problem that the structure of the semiconductor wafer becomes complicated. On the other hand, according to the technique disclosed in Patent Document 2, such a problem does not occur, but there arises a problem that it cannot be used together with a structure in which the seal ring is a substrate potential. When the seal ring has a substrate potential, a diffusion layer having the same conductivity type as that of the substrate is generally provided around the chip region, and a seal ring is provided on the diffusion layer. However, the technique disclosed in Patent Document 2 This is because the seal ring is provided on the insulating layer formed on the surface of the semiconductor substrate.

  The present invention has been made in view of the above problems, and can be used in combination with a structure in which a seal ring is used as a substrate potential, and realizes a reduction in area of a semiconductor integrated circuit and an improvement in tamper resistance with a simple configuration. It aims at providing the technology to do.

  In order to solve the above-described problems, the present invention provides a semiconductor wafer in which a plurality of chip regions including a semiconductor integrated circuit and a scribe region that is a region between the chip regions are formed on a first conductivity type semiconductor substrate. The semiconductor substrate is formed with a second conductivity type deep well extending from the chip region into the scribe region across a dicing line that is a boundary between the chip region and the scribe region, and the plurality of chips. A seal ring is formed along the outer periphery of each of the regions, and the deep well is connected to the semiconductor integrated circuit via a diffusion layer and a wiring layer of a second conductivity type in the chip region, Provided is a semiconductor wafer which is connected to a pad through a diffusion layer of a second conductivity type in the scribe region. .

  According to such a semiconductor wafer, from the semiconductor integrated circuit in the chip region, the wiring layer, the second conductivity type diffusion layer in the chip region, the second conductivity type diffusion layer in the deep well and the scribe region. A signal input / output path reaching the pad in the scribe area via the. For this reason, in the inspection process, the semiconductor circuit can be inspected by applying various inspection signals to the pad. According to this semiconductor wafer, it is disclosed in Patent Document 1 and Patent Document 2 that pads used in the inspection process can be provided in the scribe region, the area of the semiconductor integrated circuit can be reduced, and the tamper resistance can be improved. This is similar to the disclosed technology. In addition, in the semiconductor wafer according to the present invention, it is not necessary to provide a detection circuit for detecting dicing or a switching circuit for setting the signal input / output path to a fixed potential. Therefore, the semiconductor wafer is configured in comparison with the semiconductor wafer disclosed in Patent Document 1. Becomes simple.

  Further, in the semiconductor wafer of the present invention, since the seal ring has a substrate potential, even if a diffusion layer having the same conductivity type as that of the semiconductor substrate is provided around the chip region and the seal ring is provided on the diffusion layer, the diffusion is performed. Since the signal input / output path is formed by using a deep well located deeper than the layer, no particular problem occurs. In other words, the semiconductor wafer of the present invention can be used in combination with a structure in which the seal ring has a substrate potential. For example, in the case of a P-type substrate, a deep N well extending from the chip region to the scribe region is provided below the P well provided under the seal ring, and the N well and the wiring layer in the chip region are interposed. The deep N well may be electrically connected to the semiconductor integrated circuit in the chip region, and the deep N well may be connected to the inspection pad in the scribe region via the N well in the scribe region. .

  As described above, according to the present invention, it is possible to use the seal ring with the structure in which the substrate potential is used, and it is possible to realize the reduction of the area of the semiconductor integrated circuit and the improvement of the tamper resistance with a simple configuration.

  As another aspect of the present invention, a semiconductor integrated circuit manufacturing method for manufacturing a semiconductor integrated circuit by cutting the semiconductor wafer along a dicing line can be considered. When the semiconductor wafer is cut along a dicing line, a semiconductor substrate of a first conductivity type surrounded by a scribe boundary is formed, and a semiconductor integrated circuit is formed, and a second that reaches the scribe boundary. A deep well of the conductive type is formed, and the deep well is connected to the semiconductor integrated circuit through the second conductive type diffusion layer and the wiring layer in the chip region. It is done.

1 is a diagram showing a structure of a semiconductor wafer 1 according to an embodiment of the present invention. 2 is a partially enlarged view of the semiconductor wafer 1 and a cross section thereof. FIG. It is a figure for demonstrating the prior art for implement | achieving the area reduction of a semiconductor integrated circuit, and tamper-proof improvement.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing the structure of a semiconductor wafer 1 according to an embodiment of the present invention. FIG. 1A is a plan view of the semiconductor wafer 1. In FIG. 1, the same components as those in FIG. 3 are denoted by the same reference numerals. As shown in FIG. 1A, a semiconductor wafer 1 has a plurality of chip regions 10 each formed with a semiconductor integrated circuit and a scribe region 20 that is a region between the chip regions 10 formed on a P-type semiconductor substrate. This is what happens. In the present embodiment, a MOSFET (Metal Oxide) is formed in the chip region 10.
A circuit component element such as a semiconductor field effect transistor (metal-oxide film-semiconductor field effect transistor) is formed, and after wiring between the elements is performed, a dicing line serving as a boundary between the chip region 10 and the scribe region 20 is formed. A semiconductor integrated circuit is manufactured by dicing along the DL.

  FIG. 1B is a diagram showing a part of a cross section taken along line XX ′ in FIG. 1A (that is, a line extending from one chip region 10 to an adjacent scribe region 20). The seal ring SR in FIG. 1B is for preventing moisture from entering the semiconductor integrated circuit formed in the chip region 10 and peeling due to stress of each layer stacked when forming the semiconductor integrated circuit. It is. The seal ring SR is formed of the same metal material as the wiring layer so as to surround the periphery of the semiconductor integrated circuit (that is, along the outer periphery of the chip region 10). As shown in FIG. 1B, the seal ring SR is provided on a diffusion layer (P well P1 in this embodiment) having the same conductivity type as the semiconductor substrate (P type substrate in this embodiment). This is to make the potential of the seal ring SR the same as the potential of the semiconductor substrate.

  As shown in FIG. 1B, the feature of the present embodiment is that the diffusion extends from the chip region 10 to the scribe region 20 across the dicing line DL at a deeper position than the P well P1 immediately below the seal ring SR. A diffusion layer of a conductivity type different from that of the semiconductor substrate (in this embodiment, a deep N well DN) is provided. 2A is an enlarged view of the vicinity of the YY 'line in FIG. 1, and FIG. 2B is a view of the chip side (N1 side) as viewed from the cross section along the YY' line. 2A and 2B, the same components as those in FIG. 1B are denoted by the same reference numerals. However, in FIG. 2A and FIG. 2B, the first metal layer (the metal wiring layer indicated by reference numeral M1 in FIG. 1B) and the subsequent portions are omitted as appropriate for easy viewing of the drawing. Yes. As shown in FIGS. 1B and 2B, the deep N well DN is in contact with an N well N1 which is a normal N well provided in the chip region 10 and an N well N2 provided in the scribe region 20. Is provided. In the present embodiment, when the lowermost metal wiring layer (first metal layer M1) of the wiring layers of the semiconductor integrated circuit is applied, the gate electrode of the transistor Tr formed in the chip region 10 → Gate wiring (first metal layer M1) → N well N1 → deep N well DN → N well N2 → pad in scribe region 20 (pad used for input / output of various signals in the inspection process: FIG. 1B) As shown, the pad is formed by a metal wiring layer and a via, and an opening for inputting a signal is provided).

  As described above, in the semiconductor wafer 1 of the present embodiment, the pads for inputting and outputting various signals are arranged in the scribe region 20 in the inspection process of the semiconductor integrated circuit formed in the chip region 10. The area of the semiconductor integrated circuit can be reduced as compared with the case where the semiconductor integrated circuit is arranged in the chip region 10. In addition, since the scribe region 20 in which the pads are arranged is cut out by dicing, it is possible to conceal what signal is input in the inspection process after product shipment (that is, tamper resistance is improved). This is the same as the technique disclosed in Patent Document 1 or Patent Document 2. Since the semiconductor wafer 1 of the present embodiment does not require a dicing detector or a switching circuit for detecting excision of the scribe region 20, the semiconductor integrated circuit has a simpler configuration than the technique disclosed in Patent Document 1. The area can be reduced and the tamper resistance can be improved.

  In the present embodiment, the chip region 10 is formed from the pad in the scribe region 20 using a deep N well that extends under the seal ring structure (the seal ring SR and the P well P1) and extends from the chip region 10 to the scribe region 20. Since a signal input / output path leading to the semiconductor integrated circuit is formed, it can be used in combination with a structure in which the seal ring is set to the substrate potential.

  As described above, according to the present embodiment, it is possible to use in combination with a structure in which the seal ring is a substrate potential, and it is possible to realize a reduction in area of the semiconductor integrated circuit and an improvement in tamper resistance with a simple configuration. become.

Although one embodiment of the present invention has been described above, this embodiment may of course be modified as follows.
(1) In the above embodiment, the deep N well DN is connected to the semiconductor integrated circuit via the lowermost metal wiring layer (first metal layer M1) and the N well N1 in the chip region 10, but the second metal layer M2 The deep N well DN may be connected to the semiconductor circuit via another wiring layer such as the third metal layer M3 and the N well N1.

(2) In the above embodiment, the case where the circuit constituent element of the semiconductor integrated circuit formed in the chip region 10 is a MOSFET has been described. However, a MEMS (Micro Electro Mechanical Systems) such as a magnetic element and a MOSFET are mixedly mounted. It may be a semiconductor integrated circuit or may be constituted by a bipolar transistor.

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor wafer, 10 ... Chip area | region, 20 ... Scribe area | region, N1, N2 ... N well, DN ... Deep N well, P1 ... P well, DL ... Dicing line, SR ... Seal ring, M1 ... 1st metal layer, M2 ... second metal layer, M3 ... third metal layer, C ... signal input / output path.

Claims (2)

A semiconductor wafer formed by forming a plurality of chip regions including a semiconductor integrated circuit on a semiconductor substrate of a first conductivity type and a scribe region that is a region between the chip regions,
The semiconductor substrate is formed with a second conductivity type deep well extending from the chip region into the scribe region across a dicing line serving as a boundary between the chip region and the scribe region. A seal ring is formed along each outer periphery,
The deep well is connected to the semiconductor integrated circuit via the second conductive type diffusion layer and the wiring layer in the chip region, and is connected to the semiconductor integrated circuit in the scribe region via the second conductive type diffusion layer. A semiconductor wafer characterized by being connected to a pad.   A semiconductor integrated circuit manufacturing method for manufacturing a semiconductor integrated circuit by cutting the semiconductor wafer according to claim 1 along the dicing line.

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