JP2013074113A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of detecting a crack generated in an inner area of a seal ring at low cost.SOLUTION: As shown in a drawing 2, a semiconductor device concerning this embodiment includes: a multilayer wiring layer; an internal circuit area 3; a seal ring 220 which is formed in the multilayer wiring layer, and covers the internal circuit area 3; and a TEG 200 which is provided in an area sandwiched by the internal circuit area 3 and the seal ring 220 in a plan view. The TEG 200 is constituted of: a conductor pattern 7; a P-type well 13; and an N-type well 14 which are provided in at least each of two layers of the multilayer wiring layer to be mutually connected. The P-type well 13 and the N-type well 14 are arranged at a state of being alternately and mutually connected in the plan view, and the conductor pattern 7 is connected to either of the P-type well 13 and the N-type well 14.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  In recent semiconductor devices, copper wiring having low resistance to wiring and high resistance to electromigration and stress migration is employed. In order to reduce the wiring capacitance, a low dielectric constant insulating film is employed as an interlayer insulating film or an inter-wiring insulating film. However, the low dielectric constant insulating film has poor water resistance. For this reason, moisture easily enters the semiconductor device. If moisture penetrates into the semiconductor device, it may cause a malfunction such as a change in dielectric constant of the low dielectric constant insulating film or corrosion of the copper wiring.

  Patent Documents 1-3 disclose a method for suppressing or detecting moisture intrusion into a semiconductor device. Patent Document 1 describes a seal ring disposed at a location where moisture absorption from a dicing portion where a low dielectric constant insulating film is exposed can be prevented. Patent Document 2 describes a structure between a dicing region and a seal ring that can suppress the propagation of moisture to the seal ring when a crack occurs. Patent Document 3 describes a method of detecting a crack by arranging a via outside a seal ring, measuring a leak current when a voltage is applied.

JP 2000-150429 A JP 2006-5288 A JP 2008-16573 A

  In order to suppress the occurrence of malfunction due to deterioration over time, it is preferable to detect a crack reaching the inner region of the seal ring of the semiconductor device and remove the defective product. Therefore, there is a need for a method for detecting cracks generated in the inner region of the seal ring in the semiconductor device at a low cost.

According to the present invention, a substrate;
A multilayer wiring layer laminated on the substrate;
Internal circuit area,
A seal ring formed in the multilayer wiring layer and surrounding the internal circuit region;
A TEG provided in a region sandwiched between the internal circuit region and the seal ring in plan view;
Including
The TEG is
A laminate of conductor patterns provided in at least two layers of the multilayer wiring layer;
A P-type well formed on the substrate;
An N-type well formed on the substrate,
The P-type well and the N-type well are arranged in a state of being alternately connected to each other in a plan view, and the P-type well and the N-type well are connected to the different stacked bodies. An apparatus is provided.

Further, according to the present invention, an impurity is implanted into the substrate and a multilayer wiring layer is formed on the substrate, so that the internal circuit region is located in the multilayer wiring layer and surrounds the internal circuit region. Forming a seal ring, and a TEG provided in a region sandwiched between the internal circuit region and the seal ring in a plan view;
A dicing step of cutting out the semiconductor device by dicing the substrate;
An evaluation process for evaluating cracks formed in the multilayer wiring layer in the TEG;
Have
The TEG has a laminate of conductor patterns provided in at least two layers of the multilayer wiring layer, a P-type well formed on the substrate, and an N-type well formed on the substrate. The P-type well and the N-type well are alternately connected to each other in a plan view, and the P-type well and the N-type well are connected to the different stacked bodies. ,
In the evaluation step, a semiconductor device manufacturing method for measuring a leakage current flowing in the TEG is provided.

  According to the present invention, by arranging the TEG in which the N-type well and the P-type well are alternately arranged in the region between the internal circuit region and the seal ring, cracks generated in the inner region of the seal ring can be prevented. The flowing leak current can be detected.

  According to the present invention, cracks can be detected at low cost by the TEG disposed in the inner region of the seal ring. For this reason, a defective semiconductor device can be removed at low cost.

It is a figure for demonstrating the usage type of the semiconductor device which concerns on this embodiment. It is a top view which shows the semiconductor device which concerns on this embodiment. It is sectional drawing which shows the semiconductor device which concerns on this embodiment. It is sectional drawing which shows the semiconductor device which concerns on this embodiment. It is a plane conceptual diagram for demonstrating the crack which arose in the semiconductor device which concerns on this embodiment. It is a section conceptual diagram for explaining the crack which arose in the semiconductor device concerning this embodiment. It is a section conceptual diagram for explaining the crack which arose in the semiconductor device concerning this embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

FIG. 1 is a diagram for explaining a usage pattern of the semiconductor device according to the present embodiment.
As shown in FIG. 1, the semiconductor wafer is provided with a chip 400 region. A dicing region 300 is provided between the chips 400 adjacent to each other. A region to be the chip 400 is connected through a dicing region 300. In FIG. 1, only one chip is shown in detail, but the internal circuit area 3 and the like are also provided for other chips that do not actually show the internal circuit area 3 and the like. The chip 400 has an internal circuit region 3 at the center. The internal circuit region 3 is surrounded by the seal ring 220. A TEG 200 is provided in a region between the internal circuit region 3 and the seal ring 220. The TEG 200 is preferably arranged over the entire circumference.

  The semiconductor wafer is cut along the dicing region 300 using a dicing blade. Thereby, the plurality of chips 400 are singulated. At this time, a crack 5 may occur in the chip 400 (see FIG. 5). When the crack 5 is generated in the wiring layer of the chip 400, the chip 400 is easily deteriorated. This is because moisture having conductivity easily enters the chip 400 through the crack 5.

  As will be described later, in the semiconductor device according to this embodiment, the TEG 200 is used to distinguish between the chip 400 in which the crack 5 is generated in the inner region of the seal ring 220 and the chip 400 in which the crack 5 is not generated. be able to.

FIG. 2 is a plan view showing the semiconductor device according to the present embodiment.
As shown in FIG. 2, the semiconductor device according to the present embodiment includes a multilayer wiring layer, an internal circuit region 3, a seal ring 220, and a TEG 200. The seal ring 220 is formed in a multilayer wiring layer and surrounds the internal circuit region 3. The TEG 200 is provided in a region sandwiched between the internal circuit region 3 and the seal ring 220 in plan view. Further, the TEG 200 is provided in each of at least two layers of the multilayer wiring layer, and includes a conductor pattern 7, a P-type well 13, and an N-type well 14 that are connected to each other. In the TEG 200 according to the present embodiment, a plurality of conductor patterns 7 form a laminated body (see FIGS. 3 and 4). The P-type well 13 and the N-type well 14 are arranged in a state of being connected to each other in plan view, and the laminate of the conductor pattern 7 is connected to one of the P-type well 13 and the N-type well 14. Yes.
Further, the dicing region 300 remains outside the seal ring 220 in the chip 400. This is because the semiconductor wafer is cut with a slight margin when it is cut by the dicing blade.

  As shown in FIG. 2, the TEG 200 includes a P-type well 13, an N-type well 14, and a conductor pattern 7 as one structural unit 210. The TEG 200 has a plurality of structural units 210. Note that the structural unit 210 of the TEG 200 includes a first electrode pad 32 connected to the stacked body connected to the P-type well and a second electrode pad 34 connected to the stacked body connected to the N-type well. .

  The direction in which the P-type well 13 and the N-type well 14 are arranged is either a parallel direction or a vertical direction with respect to the dicing region 300. However, when the TEG 200 is arranged in a direction perpendicular to the dicing region 300, there is a possibility that the distance between the two stacked bodies having the conductor pattern 7 becomes short. In this case, there is a possibility that the TEGs 200 cannot be kept at different potentials. This is because if the distance between the two adjacent conductor patterns 7 becomes too short, a leak current may flow even if the crack 5 does not occur in the inner region of the seal ring 220.

  In FIG. 2, a rectangular N-type well 14 is arranged in the P-type well 13 in a direction perpendicular to the dicing region 300. Further, in the semiconductor device according to the present embodiment, the width of the crack reaching the inside of the seal ring 4 in the dicing region 300 is several tens of μm or more. For this reason, if the widths of the P-type well 13 and the N-type well 14 are about 1 μm, many PN junctions are broken by cracks. Further, it is preferable that the interval between the conductor pattern 7 of the TEG 200 and the interval between the conductor pattern of the TEG 200 and the seal ring 220 be a minimum interval of about 0.12 to 0.14 μm.

  The TEG 200 is preferably provided over the entire circumference of the semiconductor chip 400. Thus, a defective product can be detected regardless of where the crack 5 generated by dicing occurs in the semiconductor chip 400.

  When the chip 400 is packaged, the thermal expansion coefficients of the sealing resin and the semiconductor device are different. As a result, the chip 400 receives heat stress from the outside. Since this thermal stress is more strongly applied to the outside of the chip 400, the internal circuit region 3 is preferably not provided outside. For this reason, a certain amount of space is provided between the internal circuit region 3 and the seal ring 220. In this embodiment, the TEG 200 can be disposed on the entire circumference in the space between the internal circuit region 3 and the seal ring 220.

3 is a cross-sectional view taken along the line AA ′ in FIG. 2, and FIG. 4 is a cross-sectional view taken along the line BB ′ in FIG.
As shown in FIGS. 3 and 4, the element isolation film 12 is partially formed on the substrate 11, and the contact interlayer insulating film 100 is formed thereon. In addition, a P-type well 13, an N-type well 14, a P + diffusion layer 15 and an N + type diffusion layer 16 are formed on the substrate 11. The substrate 11 is, for example, a Si substrate.

  A first wiring layer insulating film 110 is formed on the contact interlayer insulating film 100. In the first wiring layer insulating film 110, first conductor patterns 112 and 114 are embedded, and in the contact interlayer insulating film 100, contacts 102 and 104 are embedded. The contacts 102 and 104 electrically connect the substrate 11 and the first conductor patterns 112 and 114. A first via interlayer insulating film 120 is formed on the first wiring layer insulating film 110.

  A second wiring layer insulating film 130 is formed on the first via interlayer insulating film 120. Second conductor patterns 132 and 134 are embedded in the second wiring layer insulating film 130, and first vias 122 and 124 are embedded in the first via interlayer insulating film 120. The first vias 122 and 124 electrically connect the first conductor patterns 112 and 114 and the second conductor patterns 132 and 134. A second via interlayer insulating film 140 is formed on the second wiring layer insulating film 130.

  A third wiring layer insulating film 150 is formed on the second via interlayer insulating film 140. Third conductor patterns 152 and 154 are embedded in the third wiring layer insulating film 150, and second vias 142 and 144 are embedded in the second via interlayer insulating film 140. The second vias 142 and 144 electrically connect the second conductor patterns 132 and 134 and the third conductor patterns 152 and 154. A third via interlayer insulating film 160 and a passivation film 30 are formed on the third wiring layer insulating film 150, respectively.

  Note that electrode pads 32 and 34 are formed on the third via interlayer insulating film 160. A passivation film 30 is formed on the third via interlayer insulating film 160, the first electrode pad 32, and the second electrode pad 34. The first electrode pad 32 and the second electrode pad The passivation film 30 disposed on the upper portion of 34 is removed. Note that the first electrode pad 32 and the second electrode pad 34 are made of aluminum, for example.

  The seal ring 220 has a configuration in which the contact 104, the first via 124, the second via 144, the first conductor pattern 114, the second conductor pattern 134, and the third conductor pattern 154 are stacked. The first wiring layer insulating film 110, the second wiring layer insulating film 130, and the third wiring layer insulating film 150 are separated by a seal ring 220. Note that the seal ring 220 may be configured in a multiple manner.

  3 and 4, the laminated body is provided in an interlayer insulating film having contacts or vias and a layer above the interlayer insulating film, and a conductor pattern having the wiring layer insulating film having wiring as one constituent unit is laminated. Has been. Specifically, the contact interlayer insulating film 100 and the first wiring layer insulating film 110, the first via interlayer insulating film 120 and the second wiring layer insulating film 130, the second via interlayer insulating film 140 and the third The wiring layer insulating film 150 is a constituent unit of the conductor pattern. The semiconductor devices shown in FIGS. 3 and 4 are configured by laminating these conductor patterns.

  Contact interlayer insulating film 100, first via interlayer insulating film 120, second via interlayer insulating film 140, first wiring layer insulating film 110, second wiring layer insulating film 130, and third wiring layer As the insulating film 150, a low dielectric constant insulating film is preferably used. At this time, a laminated structure in which a part of the insulating film is a low dielectric constant insulating film may be employed. Note that a silicon oxide film is preferably used for the third via interlayer insulating film 160.

  The contacts 102 and 104, the first vias 122 and 124, the second vias 142 and 144, and the first conductor pattern 112, the second conductor pattern 132, and the third conductor pattern 152 include electromigration and A material having excellent resistance to stress migration and a small specific resistance is used. Specifically, when these are formed by a single damascene method, tungsten or copper is used, and when they are formed by a dual damascene method, copper is used.

  The passivation film 30 is a silicon oxide film, a silicon nitride film, or a laminated structure of polyimide. Furthermore, as the pad metal, a metal material mainly composed of aluminum is used.

  As shown in FIGS. 2 and 3, the internal circuit region 3 includes a transistor including a gate electrode 40, a gate insulating film 50, an element isolation region 60, a source / drain region 70, an extension region 90, and a sidewall 95. Has been. This transistor may be either a p-type transistor or an n-type transistor.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described.

  First, impurities are implanted into a substrate 11 provided on a semiconductor wafer, and a transistor and an element isolation insulating film 12 are formed on the substrate 11 as shown in FIGS. Simultaneously with the transistor, an N-type well 14, a P-type well 13, a P + diffusion layer 15, and an N + diffusion layer 16 are formed.

  Next, a multilayer wiring layer is formed on the transistor and the substrate 11. The multilayer wiring layer is formed by sequentially stacking each layer. At this time, the internal circuit region 3 of the TEG 200 is formed. A seal ring 220 surrounding the internal circuit region 3 is also formed. In this step, the TEG 200 is formed. Next, the dicing area 300 of the semiconductor wafer is cut by a dicing blade, and the semiconductor chip 400 is cut out.

  Next, the leakage current flowing through the crack 5 formed in the multilayer wiring layer is measured by the TEG 200. At this time, when a leak current is detected, the semiconductor device is removed as a defective product.

FIG. 5 is a conceptual plan view for explaining a crack generated in the semiconductor device according to the present embodiment. 6 is a diagram of a first example of the AA ′ cross section in FIG. 5, and FIG. 7 is a diagram of a second example of the AA ′ cross section of FIG. The crack 5 is generated when the dicing area 300 is cut into individual semiconductor chips 400 by a dicing blade.
As shown in FIG. 5, the crack 5 is generated so as to overlap the TEG 200 disposed in the inner region of the seal ring 220 from the dicing region 300. Further, the crack extends from the outside of the chip 400 toward the inside. For this reason, the crack 5 may enter the interlayer film or the substrate.

  FIG. 6 is a cross-sectional view when the crack 5 enters the interlayer film. As shown in FIG. 6, the crack 5 starting from the insulating film in the multilayer wiring layer divides the conductor pattern 7 composed of the wiring of the TEG 200 and the connection layer. When moisture enters the crack 5, the insulating film exposed as the crack 5 is generated absorbs moisture. At this time, each conductor pattern 7 is connected to the electrode pad 36. For this reason, when a voltage is applied, the insulating film which absorbed moisture cannot maintain insulation. For this reason, a leak current flows between the conductor pattern 7 and the seal ring 220. On the other hand, no leak current flows through the chip 400 in which the crack 5 has not occurred.

FIG. 7 is a cross-sectional view when the crack 5 generated from the substrate 11 enters the interlayer film.
The N-type well 14 and the P-type well 13 are connected to the first electrode pad 32 and the second electrode pad 34, respectively. In the case where the junction between the N-type well 14 and the P-type well 13 in the TEG 200 is broken, when a voltage is applied, a leak current flows in a location where the crack 5 occurs. On the other hand, as in the case where the crack 5 shown in FIG. 6 occurs, no leak current flows through the semiconductor device in which the crack 5 does not occur.
Therefore, when the insulating film is the starting point and when the substrate 11 is the starting point, the crack 5 can be detected in any case.

  When the generated crack 5 reaches the internal circuit region 3 inside the region where the TEG 200 is formed, the P-type well 13, the N-type well 14, the P + diffusion layer 15, and the N + diffusion layer 16 constituting the internal circuit region 3 are used. The PN junction constituted by any of the above is destroyed. As a result, a leakage current is generated, so that it is determined as defective by an electrical inspection by the TEG 200 after the assembly of the package.

  Next, effects of the semiconductor device according to the present embodiment will be described.

  The TEG 200 in which the N-type well 14 and the P-type well 13 are alternately arranged is arranged between the seal ring 220 and the internal circuit region 3. As a result, either of the cases where the crack 5 starting from the substrate 11 reaches the inside of the seal ring 220 or the crack 5 starting from the insulating film in the multilayer wiring layer reaches the inside of the seal ring 220. The crack 5 can also be detected. Therefore, when this semiconductor device is used, defective products can be removed at low cost.

  Further, since the TEG 200 is disposed between the seal ring 220 and the internal circuit region 3, only the crack 5 extending inward from the seal ring 220 is set as a detection target. For this reason, the crack 5 generated outside the seal ring 220 is detected, and the semiconductor device is not removed as a defective product.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

3 Internal circuit region 5 Crack 7 Conductor pattern 11 Substrate 12 Element isolation insulating film 13 P-type well 14 N-type well 15 P + diffusion layer 16 N + diffusion layer 30 Passivation film 32 First electrode pad 34 Second electrode pad 40 Gate electrode 50 Gate insulating film 70 Source / drain region 90 Extension region 95 Side wall 100 Contact interlayer insulating film 102 Contact 104 Contact 110 First wiring layer insulating film 112 First conductor pattern 114 First conductor pattern 120 First via layer Insulating film 122 First via 124 First via 130 Second wiring layer insulating film 132 Second conductor pattern 134 Second conductor pattern 140 Second via interlayer insulating film 142 Second via 144 Second via 150 Third wiring layer insulating film 152 Third conductor pattern 154 Third conductor pattern 160 Third via interlayer insulating film 200 TEG
210 TEG constituent unit 220 Seal ring 300 Dicing region 400 Semiconductor chip

Claims (8)

A substrate,
A multilayer wiring layer laminated on the substrate;
Internal circuit area,
A seal ring formed in the multilayer wiring layer and surrounding the internal circuit region;
A TEG provided in a region sandwiched between the internal circuit region and the seal ring in plan view;
Including
The TEG is
A laminate of conductor patterns provided in at least two layers of the multilayer wiring layer;
A P-type well formed on the substrate;
An N-type well formed on the substrate,
The P-type well and the N-type well are arranged in a state of being alternately connected to each other in a plan view, and the P-type well and the N-type well are connected to the different stacked bodies. apparatus.   2. The semiconductor device according to claim 1, wherein the direction in which the P-type well and the N-type well are aligned is either a parallel direction or a vertical direction with respect to the dicing region.   A first electrode pad connected to the stacked body connected to the P-type well and connected to the stacked body connected to the N-type well; and a second electrode pad connected to the stacked body connected to the N-type well. The semiconductor device according to claim 1 or 2.   The semiconductor device according to claim 1, wherein the TEG is provided over the entire circumference of the semiconductor chip. Impurities are implanted into the substrate, and a multilayer wiring layer is formed on the substrate, whereby an internal circuit region, a seal ring located in the multilayer wiring layer and surrounding the internal circuit region, and the planar view A forming step of forming a TEG provided in a region sandwiched between an internal circuit region and the seal ring;
A dicing step of cutting out the semiconductor device by dicing the substrate;
An evaluation step for evaluating cracks formed in the multilayer wiring layer in the TEG;
Have
The TEG has a laminate of conductor patterns provided in at least two layers of the multilayer wiring layer, a P-type well formed in the substrate, and an N-type well formed in the substrate. The P-type well and the N-type well are alternately connected to each other in plan view, and the P-type well and the N-type well are connected to the different stacked bodies. ,
The evaluation step is a method of manufacturing a semiconductor device that measures a leakage current flowing through the TEG.   6. The method of manufacturing a semiconductor device according to claim 5, wherein a direction in which the P-type well and the N-type well are aligned is either a parallel direction or a vertical direction with respect to the dicing region.   A first electrode pad connected to the stacked body connected to the P-type well and connected to the stacked body connected to the N-type well; and a second electrode pad connected to the stacked body connected to the N-type well. A method for manufacturing a semiconductor device according to claim 5 or 6.   The method for manufacturing a semiconductor device according to claim 5, wherein the TEG is provided over the entire circumference of the semiconductor chip.

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