JP2012033760A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a simple method to detect the existence of interlayer peeling in a multilayer wiring layer.SOLUTION: A first electrode 412 is formed in a multilayer wiring layer 20. A second electrode 422 faces a first electrode 412 through a part of an insulating film 22. A first electrode pad 430 is connected to the first electrode 412. A second electrode pad 432 is connected to the second electrode 422. Each of at least more than two insulating layers 22 is sandwiched between the first electrode 412 and the second electrode 422. At least a part of a sensor 40 is constituted by the first electrode 412 and the second electrode 422. The sensor 40 is used for detecting the existence of interlayer peeling in the multilayer wiring layer 20.

Description

  The present invention relates to a semiconductor device having a multilayer wiring layer and a method for manufacturing the semiconductor device.

  The semiconductor chip manufacturing process includes a process of dicing a wafer into individual semiconductor chips. At the stage of dicing, a multilayer wiring layer is formed on the wafer. For this reason, when dicing the wafer, there is a possibility that peeling occurs between the layers of the multilayer wiring layer on the side surface of the semiconductor chip.

  Patent Document 1 describes that a test MIM capacitor for determining the quality of a decap ring capacitor is provided. This MIM capacitor is formed by using two wiring layers.

JP 2008-192707 A

  As described above, when dicing the wafer, there is a possibility that separation occurs between the layers of the multilayer wiring layer on the side surface of the semiconductor chip. When peeling occurs between the layers of the multilayer wiring layer, the peeled portion becomes a starting point of deterioration of the semiconductor chip. For this reason, in order to detect a defective semiconductor chip, it is necessary to be able to detect the presence or absence of delamination between layers of the multilayer wiring layer by a simple method.

According to the present invention, a substrate;
A multilayer wiring layer formed on the substrate and having three or more wiring layers;
An insulating layer constituting the wiring layer;
A first electrode formed on any of the wiring layers;
A second electrode facing the first electrode through a part of the insulating layer;
A first electrode pad connected to the first electrode;
A second electrode pad connected to the second electrode;
With
There is provided a semiconductor device in which at least two or more insulating layers are sandwiched between the first electrode and the second electrode.

  When peeling occurs between the layers of the multilayer wiring layer on the side surface of the semiconductor device, moisture enters the inside of the semiconductor device from the peeled portion. This moisture is absorbed by the insulating film. As a result, the dielectric constant of the interlayer insulating film increases, and as a result, the capacitance generated between the first electrode and the second electrode increases. Therefore, the capacitance generated between the first electrode pad and the second electrode pad is measured before and after the process of dicing the wafer into a plurality of semiconductor devices, and grasping the difference between the two capacitances. Thus, it is possible to detect the presence or absence of peeling between the multilayer wiring layers.

According to the present invention, a first step of forming a multilayer wiring layer having three or more wiring layers on a wafer;
A second step of dicing the wafer into pieces into a plurality of semiconductor devices;
With
The wiring layer has an insulating layer;
In the first step,
A first electrode located in any of the wiring layers;
A second electrode facing the first electrode across a part of the insulating layer;
A first electrode pad connected to the first electrode;
A second electrode pad connected to the second electrode;
Are formed for each of the plurality of semiconductor devices, and the first electrode and the second electrode are arranged so that each of the at least two insulating layers is sandwiched between the first electrode and the second electrode. Forming,
By measuring the capacitance between the first electrode pad and the second electrode pad at respective timings before and after the second step, and comparing the obtained two measured values, A method of manufacturing a semiconductor device is provided that detects whether there is an abnormality in the semiconductor device.

  According to the present invention, the presence / absence of delamination between layers of a multilayer wiring layer can be detected by a simple technique.

It is sectional drawing of the principal part of the semiconductor device which concerns on 1st Embodiment. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. It is a perspective view which shows the structure of the sensor which the semiconductor device shown in FIG. 1 has. It is the figure which expanded a part of sensor. It is sectional drawing which shows the structure of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 4th Embodiment. It is a top view which shows the shape of the 1st electrode and 2nd electrode in the semiconductor device shown in FIG. FIG. 8 is an enlarged cross-sectional view of a main part of the semiconductor device shown in FIG. 7. It is a top view which shows the structure of the semiconductor device which concerns on 5th Embodiment. It is sectional drawing of the semiconductor device shown in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a cross-sectional view of a main part of the semiconductor device according to the first embodiment. FIG. 2 is a plan view of the semiconductor device shown in FIG. FIG. 1 corresponds to the AA ′ cross section in FIG. 2. FIG. 3 is a perspective view showing a configuration of the sensor 40 included in the semiconductor device shown in FIG. A cross section in the left-right direction in FIG. 3 corresponds to the cross-sectional view in FIG. This semiconductor device includes a substrate 10, a multilayer wiring layer 20, a first electrode 412, a second electrode 422, a first electrode pad 430 (see FIG. 3), and a second electrode pad 432 (see FIG. 3). Yes. The multilayer wiring layer 20 is formed on the substrate 10 and has three or more wiring layers. Each wiring layer has an insulating film 22. The first electrode 412 is formed on the multilayer wiring layer 20. The second electrode 422 is opposed to the first electrode 412 through a part of the insulating film 22. The first electrode pad 430 is connected to the first electrode 412. The second electrode pad 432 is connected to the second electrode 422. Each of the insulating films 22 having at least two layers is sandwiched between the first electrode 412 and the second electrode 422. The first electrode 412 and the second electrode 422 form at least a part of the sensor 40. The sensor 40 is used to detect the presence or absence of peeling between the multilayer wiring layers 20. Details will be described below.

  As shown in FIG. 2, the semiconductor device according to this embodiment includes an internal circuit region 100. The internal circuit region 100 has an internal circuit of the semiconductor device. This circuit has a transistor. The circuit formed in the internal circuit region 100 includes, for example, at least one of a logic circuit, an analog circuit, and a memory circuit. The internal circuit region 100 is surrounded by guard rings 30 and 32. As shown in FIG. 1, the guard rings 30 and 32 form conductive patterns 302 in each wiring layer of the multilayer wiring layer 20, connect these conductive patterns 302 to each other using the conductive pattern 301 in the same layer as the vias, Further, the conductive pattern 303 is formed on the insulating layer 12 where the contact is formed. In the region 104 outside the guard ring 32, peeling may occur in the multilayer wiring layer 20 during dicing. In this embodiment, the presence or absence of this peeling is detected by using the sensor 40. In the present embodiment, the sensor 40 is disposed in the region 102 between the guard rings 30 and 32.

  As shown in FIGS. 1 and 3, the first electrode 412 and the second electrode 422 are arranged in different wiring layers. In plan view, the first electrode 412 and the second electrode 422 overlap.

  Specifically, the first electrode 412 is formed on all odd-numbered wiring layers of the multilayer wiring layer 20, and the second electrode 422 is formed on all even-numbered wiring layers. The plurality of first electrodes 412 are connected to each other through vias 411 embedded in the insulating film 22 and conductor patterns 413 formed in even-numbered wiring layers. The plurality of second electrodes 422 are connected to each other through vias 421 embedded in the insulating film 22 and conductor patterns 423 formed in odd-numbered wiring layers. All the first electrodes 412 are connected to the same first electrode pad 430, and all the second electrodes 422 are connected to the same second electrode pad 432. The first electrode 412 is connected only to the first electrode pad 430 through the via and wiring in the multilayer wiring layer 20, and the second electrode 422 is connected to the first electrode 412 through the via and wiring in the multilayer wiring layer 20. Only the two-electrode pad 432 is connected. The insulating film 22 is, for example, SiOC or SiCOH.

  Further, when the first electrode 412 and the second electrode 422 that overlap each other in plan view are viewed as one capacitive element, a plurality of capacitive elements are formed. The plurality of capacitive elements are connected in parallel by conductor patterns 414 and 424 formed in any one of the wiring layers. The conductor pattern 414 connects the first electrodes 412, and the conductor pattern 424 connects the second electrodes 422.

  FIG. 4 is an enlarged view of a part of the sensor 40. In each wiring layer constituting the multilayer wiring layer 20, the wiring is embedded in the insulating film 22. Since the first electrode 412 and the second electrode 422 are formed in the same process as the wiring, they are embedded in the insulating film 22.

  In order to embed the first electrode 412 and the second electrode 422 in the insulating film 22, it is necessary to form a groove in the insulating film 22 using a resist pattern. In the step of forming the groove and the step of ashing the resist pattern, the altered layer 24 that has been subjected to plasma damage is formed on the surface of the insulating film 22 (including the side and bottom surfaces of the groove). That is, the cap film 23, the etching stopper film 21, the insulating film 22, and the altered layer 24 are laminated in this order between the first electrode 412 and the second electrode 422. The altered layer 24 is easier to absorb moisture than a portion of the insulating film 22 that is not altered. The altered layer 24 and the insulating film 22 increase in dielectric constant when absorbed.

  On the other hand, when peeling occurs between the layers of the multilayer wiring layer 20, moisture enters the inside of the semiconductor device from the peeled portion. This moisture is absorbed by, for example, the altered layer 24 and the insulating film 22. As a result, the capacitance generated between the first electrode 412 and the second electrode 422 increases. Therefore, before and after the process of dicing the wafer into a plurality of semiconductor devices, the capacitance generated between the first electrode pad 430 and the second electrode pad 432 is measured to grasp the difference between the two capacitances. By doing so, it is possible to detect the presence or absence of delamination between the multilayer wiring layers 20.

  Next, a method for manufacturing the semiconductor device shown in FIGS. 1 to 4 will be described. First, an element such as a transistor is formed on the substrate 10 in a wafer state. Next, the multilayer wiring layer 20 is formed on the substrate 10. At this time, the sensor 40 and the guard rings 30 and 32 are also formed. Next, in a state before separation, the capacitance between the first electrode pad 430 and the second electrode pad 432 of the sensor 40 is measured for each semiconductor device.

  Thereafter, the substrate 10 and the multilayer wiring layer 20 are diced to singulate a plurality of semiconductor devices. Then, the capacitance between the first electrode pad 430 and the second electrode pad 432 of the sensor 40 is measured for each semiconductor device after separation. Then, the change in capacitance before and after dicing is measured, and a semiconductor device whose change amount exceeds the reference is determined as a defective product.

  As described above, according to the present embodiment, whether or not the multi-layer wiring layer 20 of the semiconductor device is peeled is determined only by measuring the resistance of the sensor 40 before and after the semiconductor device is separated. can do. In the present embodiment, since one of the first electrode 412 and the second electrode 422 is formed in each wiring layer of the multilayer wiring layer 20, this separation is detected even if any separation occurs. Can do.

  The plurality of first electrodes 412 are connected to the same first electrode pad 430, and the plurality of second electrodes 422 are connected to the same second electrode pad 432. For this reason, the measurement may be performed once before and after the semiconductor device is separated. For this reason, the number of processes required for the measurement of the sensor 40 can be reduced.

(Second Embodiment)
FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment, and corresponds to FIG. 1 in the first embodiment. The semiconductor device according to the present embodiment has the same configuration as that of the semiconductor device according to the first embodiment, except that the sensor 40 is included in the internal circuit region 100.

Specifically, the sensor 40 is located between the inner guard ring 30 and an internal circuit (not shown).
Also according to this embodiment, the same effect as that of the first embodiment can be obtained.

(Third embodiment)
FIG. 6 is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment, and corresponds to FIG. 1 in the first embodiment. The semiconductor device according to the present embodiment has the same configuration as that of the semiconductor device according to the first embodiment, except that the sensor 40 is provided in the region 104 outside the outer guard ring 32.
Also according to this embodiment, the same effect as that of the semiconductor device according to the first embodiment can be obtained.

(Fourth embodiment)
FIG. 7 is a cross-sectional view showing the configuration of the semiconductor device according to the fourth embodiment, and corresponds to FIG. 1 in the first embodiment. FIG. 8 is a plan view showing the shapes of the first electrode 412 and the second electrode 422 in the semiconductor device shown in FIG. FIG. 9 is an enlarged cross-sectional view of a main part of the semiconductor device shown in FIG. 7, and corresponds to FIG. 4 in the first embodiment. 7 corresponds to the AA ′ cross section of FIG. 8, and FIG. 9 corresponds to the BB ′ cross section of FIG. The semiconductor device according to this embodiment has the same configuration as that of the semiconductor device according to any one of the first to third embodiments, except for the layout of the first electrode 412 and the second electrode 422. Each figure shows the same case as in the first embodiment.

  In the present embodiment, the first electrode 412 and the second electrode 422 are embedded in all the wiring layers, and face each other in the same wiring layer. Specifically, each of the first electrode 412 and the second electrode 422 has a comb-shaped planar shape, and the tooth portions are arranged so as to enter each other's gap. The first electrodes 412 formed in each layer are connected to each other through vias, and the second electrodes 422 formed in each layer are also connected to each other through vias.

  As shown in FIG. 9, the insulating film 22 and the altered layer 24 are located between the first electrode 412 and the second electrode 422. For this reason, according to this embodiment, the same effect as that of the first embodiment can be obtained.

(Fifth embodiment)
FIG. 10 is a plan view showing the configuration of the semiconductor device according to the fifth embodiment, and corresponds to FIG. 8 in the fourth embodiment. FIG. 11 is a cross-sectional view of the semiconductor device shown in FIG. 10 and corresponds to FIG. 7 in the fourth embodiment. The semiconductor device according to the present embodiment is the same as the semiconductor device according to the fourth embodiment except that the first electrode 412 and the second electrode 422 do not have a comb-teeth shape and are linear in a plan view. It is the same composition as.
According to this embodiment, the same effect as that of the fourth embodiment can be obtained.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

DESCRIPTION OF SYMBOLS 10 Board | substrate 12 Insulating layer 20 Multilayer wiring layer 21 Etching stopper film 22 Insulating film 23 Cap film 24 Alteration layer 30 Guard ring 32 Guard ring 40 Sensor 100 Internal circuit area 102 Area 104 Area 301 Conductive pattern 302 Conductive pattern 303 Conductive pattern 411 Via 412 First electrode 413 Conductor pattern 414 Conductor pattern 421 Via 422 Second electrode 423 Conductor pattern 424 Conductor pattern 430 First electrode pad 432 Second electrode pad

Claims (12)

A substrate,
A multilayer wiring layer formed on the substrate and having three or more wiring layers;
An insulating layer constituting the wiring layer;
A first electrode formed on any of the wiring layers;
A second electrode facing the first electrode through a part of the insulating layer;
A first electrode pad connected to the first electrode;
A second electrode pad connected to the second electrode;
With
A semiconductor device in which each of at least two or more insulating layers is sandwiched between the first electrode and the second electrode. The semiconductor device according to claim 1,
The semiconductor device, wherein the second electrode is formed in a wiring layer one layer above the wiring layer in which the first electrode is formed. The semiconductor device according to claim 2,
The first electrode is formed on all of the odd-numbered wiring layers of the multilayer wiring layer,
A semiconductor device in which the second electrode is formed in all even-numbered wiring layers of the multilayer wiring layer. The semiconductor device according to claim 1,
The semiconductor device in which the first electrode and the second electrode are embedded in the same insulating layer. The semiconductor device according to claim 4,
The semiconductor device in which the first electrode and the second electrode are formed in all layers of the multilayer wiring layer. In the semiconductor device according to any one of claims 1 to 5,
All the first electrodes are connected to the same first electrode pad,
A semiconductor device in which all the second electrodes are connected to the same second electrode pad. In the semiconductor device according to any one of claims 1 to 6,
The semiconductor device in which the surface layer of the insulating layer is a deteriorated layer that absorbs moisture more easily than an unmodified portion of the insulating layer. In the semiconductor device according to any one of claims 1 to 7,
The first electrode is connected only to the first electrode pad through wiring and vias in the multilayer wiring layer,
The semiconductor device, wherein the second electrode is connected only to the second electrode pad via a wiring and a via in the multilayer wiring layer. In the semiconductor device according to any one of claims 1 to 8,
Internal circuitry,
A guard ring surrounding the internal circuit;
With
The semiconductor device in which the first electrode and the second electrode are located between the internal circuit and the guard ring in plan view. In the semiconductor device according to any one of claims 1 to 8,
Internal circuitry,
A guard ring surrounding the internal circuit;
With
The semiconductor device, wherein the first electrode and the second electrode are located outside the guard ring in plan view. In the semiconductor device according to any one of claims 1 to 8,
Internal circuitry,
A first guard ring surrounding the inner circuit;
A second guard ring surrounding the first guard ring;
With
The semiconductor device, wherein the first electrode and the second electrode are located between the first guard ring and the second guard ring in plan view. A first step of forming a multilayer wiring layer having three or more wiring layers on the wafer;
A second step of dicing the wafer into pieces into a plurality of semiconductor devices;
With
The wiring layer has an insulating layer;
In the first step,
A first electrode located in any of the wiring layers;
A second electrode facing the first electrode across a part of the insulating layer;
A first electrode pad connected to the first electrode;
A second electrode pad connected to the second electrode;
Are formed for each of the plurality of semiconductor devices, and the first electrode and the second electrode are formed such that at least two or more insulating layers are sandwiched between the first electrode and the second electrode. And
By measuring the capacitance between the first electrode pad and the second electrode pad at respective timings before and after the second step, and comparing the obtained two measured values, A method of manufacturing a semiconductor device, wherein the presence or absence of abnormality of the semiconductor device is detected.

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