TWI550749B - Semiconductor wafer, semiconductor chip and semiconductor device and the fabricating method thereof - Google Patents

Description

Semiconductor wafer, semiconductor wafer, and semiconductor device and method of fabricating the same

The present invention relates to a semiconductor wafer of a dynamic random access memory (DRAM), a NAND flash memory, a method of manufacturing the same, a semiconductor wafer having a plurality of semiconductor wafers, a method of manufacturing the same, and a layer A semiconductor device in which a plurality of semiconductor wafers are stacked and a method of manufacturing the same.

At present, through-silicon vias (hereinafter referred to as "TSV" (through silicon via) technology are being developed and put into practical use by many semiconductor manufacturing companies, and large-capacity DRAM or NAND type with TSV connection pads are being used. A technique in which a plurality of semiconductor wafers of a flash memory are stacked in the thickness direction to produce a memory device having a larger capacity is put to practical use. For example, in the Hybrid Memory Cube Consortium (HMCC), research and development of high-performance, high-capacity DRAMs using TSV technology is being researched and developed.

Patent Document 1] JP 2013-105996

Patent Document 2] JP 2013-065393

Patent Document 3] JP2005-072457

[Patent Document 4] JP2004-342725

Patent Document 5] JP 2013-098535

[Patent Document 6] JP2005-026582

Fig. 1 is a plan view showing the configuration of a semiconductor wafer 1 having a plurality of NAND-type flash memory wafers according to a conventional example. As shown in Fig. 1, a plurality of semiconductor memory chips 2 on the semiconductor wafer 1 are arranged side by side for the large connection pads 3 for detecting and bonding. These large connection pads 3 also occupy a large area. Further, an electrostatic discharge circuit (hereinafter referred to as an "ESD circuit") is formed in the large connection pad 3, and similarly occupies a large area. Therefore, if these connection pads and the ESD circuit can be placed in the semiconductor memory chip 2, the wafer size can be reduced and the cost can be reduced. In the first drawing, SA is a scribe region for displaying the semiconductor memory chips 2, and SL is a scribe line for displaying each of the semiconductor memory chips 2.

For example, Patent Document 1 laminates a plurality of DRAM wafers by TSV on a semiconductor wafer having an interface circuit. Since this DRAM wafer is dedicated for lamination, it does not require a bonding pad, an ESD circuit, etc., but has a connection pad for probe testing. Further, Patent Document 2 discloses a semiconductor device in which a semiconductor memory wafer is further connected to a semiconductor wafer having a via circuit by bonding or TSV-connecting a plurality of semiconductor memory chips, but has a Bonding pads for bonding and probe testing.

Further, in Patent Documents 3 and 4, a plurality of probe test pads are formed in the cutting region, and the probe test can be easily performed. Also, in the patent literature In 5 and 6, a plurality of TSV connection pads are formed in the cutting zone.

However, as in, for example, Patent Documents 3 and 4, when a plurality of probe test pads are formed in the dicing zone, the large width of the probe test pad or the like may cause a problem of deterioration of reliability as follows.

(1) when the dicing line cuts the semiconductor wafer, the residual metal causes a short circuit between the connection pads; and (2) the local damage caused by dicing the semiconductor wafer, the moisture extending along the connection pad from the inside of the wafer The connecting metal wires invade and corrode.

An object of the present invention is to provide a semiconductor wafer, a method of fabricating the same, a semiconductor wafer having a plurality of semiconductor wafers, a method of fabricating the same, and a semiconductor device for stacking a plurality of semiconductor wafers, and a method of fabricating the same, which are formed by TSV lamination on a dicing line In the case of the probe test pad of the connected semiconductor memory chip, it is possible to solve the problem that the reliability of the semiconductor wafer caused by the pad metal, the damage, and the like remaining in the probe test pad when the wire is cut by the dicing line is deteriorated.

In view of this, an embodiment of the present invention provides a semiconductor wafer, comprising: a plurality of semiconductor wafers; a plurality of probe test pads formed in a dicing area of the semiconductor wafer; and a plurality of through-pass twinned holes Forming on the semiconductor wafer; and a circuit layer, each of the probe test pads is respectively connected to each of the through-silicon vias; wherein the semiconductor wafer is configured to remove the above by etching after the wafer test a plurality of probe test pads or a part of the above circuit layer, or a plurality of the above The probe test pad and a portion of the above wiring layer are removed by etching.

Preferably, in the semiconductor wafer, the plurality of through-silicon vias are formed in advance, and after the wafer is tested, the plurality of probe test pads or a part of the circuit layer is removed by etching, or The plurality of probe test pads and a portion of the wiring layer are removed by etching.

Further, the semiconductor wafer further includes a protective film formed to cover an exposed surface of the remaining wiring layer when a part of the wiring layer is removed.

Furthermore, in the above semiconductor wafer, the wiring layer connected to the plurality of probe test pads is not the uppermost layer.

Further, in the semiconductor wafer, a wiring layer connected to each of the probe test pads and a wiring layer connected to each of the through-silicon vias are different layers.

Further, in the above semiconductor wafer, the plurality of probe test pads are formed along one side or both sides of the semiconductor wafer.

Furthermore, in the above semiconductor wafer, the plurality of probe test pads are commonly used to be connected to the plurality of semiconductor wafers via the wiring layer.

Further, in the above semiconductor wafer, a test circuit is further included.

Further, in the above semiconductor wafer, the probe test pad is made of copper.

Another embodiment of the present invention provides a semiconductor wafer characterized in that, in the semiconductor wafer, a plurality of semiconductor wafers are separated by cutting along a predetermined scribe line of the dicing area.

In the above semiconductor wafer, the semiconductor wafer is preferably a semiconductor memory wafer.

Still another embodiment of the present invention provides a semiconductor device characterized in that a plurality of semiconductor wafers are laminated by connecting through straight through-holes of semiconductor wafers adjacent to each other in a thickness direction, thereby constituting a semiconductor device. .

Still another embodiment of the present invention provides a method of fabricating a semiconductor wafer, comprising: forming a plurality of probe test pads in a dicing region of a semiconductor wafer having a plurality of semiconductor wafers; forming on the semiconductor wafer a plurality of circuit layers; forming a plurality of through-silicon vias connected to the respective circuit layers on the semiconductor wafer; and removing the plurality of probe test pads or a portion of the circuit layers by etching after wafer testing Or a plurality of probe test pads and a portion of the above wiring layer are removed by etching.

In the method for fabricating a semiconductor wafer, after the plurality of through-silicon vias are formed in advance, a wafer test is performed, and the plurality of probe test pads or a part of the circuit layer is removed by etching, or A plurality of probe test pads and a portion of the above wiring layers are removed by etching.

Further, in the method of manufacturing a semiconductor wafer, the method further includes forming a protective film by covering an exposed surface of the remaining wiring layer when a part of the wiring layer is removed.

Yet another embodiment of the present invention is to provide a semiconductor wafer A manufacturing method characterized in that in the method of manufacturing a semiconductor wafer, a plurality of semiconductor wafers are separated by cutting along a predetermined scribe line of the dicing area.

Still another embodiment of the present invention provides a method of fabricating a semiconductor device, characterized in that in the method for fabricating a semiconductor wafer, each of the plurality of semiconductor wafers is connected to each other through a semiconductor wafer adjacent to each other in a thickness direction. The crystal vias are laminated to form a semiconductor device.

According to the invention, at least one of the plurality of probe test pads and a portion of the circuit layer is removed by etching after the wafer is tested. Therefore, it is possible to solve the problem that the reliability of the semiconductor wafer caused by the pad metal remaining in the probe test pad when the semiconductor wafer is cut by the scribe line is deteriorated.

1‧‧‧Semiconductor wafer

2‧‧‧NAND flash memory chip

3‧‧‧ Large connection pad

4‧‧‧ probe test pad

5‧‧‧TSV connection pad

6‧‧‧TSV connection pad

7‧‧‧Test circuit

10‧‧‧Line layer

10a‧‧‧ exposed surface

11‧‧‧Protective film

12‧‧‧Protective film

13‧‧‧through holes

14‧‧‧TSV conductor

15‧‧‧ spacer film

16‧‧‧ openings

21‧‧‧MOS memory transistor

22‧‧‧Interlayer conductor

23‧‧‧Interlayer conductor

SA‧‧ cutting area

SL‧‧‧ cutting road

SP‧‧ ‧ interval

Fig. 1 is a plan view showing the configuration of a semiconductor wafer 1 having a plurality of NAND-type flash memory chips 2 according to a conventional example.

Fig. 2 is a plan view showing the configuration of a semiconductor wafer 1 having a plurality of NAND-type flash memory chips 2 according to the first embodiment.

Fig. 3A is a longitudinal sectional view showing the first step of the method of manufacturing the NAND type flash memory chip 2 of Fig. 2.

Fig. 3B is a longitudinal sectional view showing the second step of the method of manufacturing the NAND type flash memory chip 2 of Fig. 2.

Fig. 3C is a longitudinal sectional view showing the third step of the method of manufacturing the NAND type flash memory chip 2 of Fig. 2.

Figure 3D is a longitudinal sectional view showing the NAND type flash memory crystal of Figure 2 The fourth step of the manufacturing method of the sheet 2.

Fig. 3E is a longitudinal sectional view showing the fifth step of the method of manufacturing the NAND type flash memory chip 2 of Fig. 2.

Fig. 4 is a plan view showing the configuration of a semiconductor wafer 1 having a plurality of NAND-type flash memory chips 2 according to the second embodiment.

Fig. 5 is a plan view showing the configuration of a semiconductor wafer 1 having a plurality of NAND type flash memory chips 2 according to the third embodiment.

Fig. 6 is a plan view showing the configuration of a semiconductor wafer 1 having a plurality of NAND-type flash memory chips 2 according to the fourth embodiment.

Fig. 7A is a longitudinal sectional view showing the first step of the method of manufacturing the NAND type flash memory chip 2 according to the fifth embodiment.

Fig. 7B is a longitudinal sectional view showing the second step of the method of manufacturing the NAND type flash memory chip 2 according to the fifth embodiment.

Fig. 7C is a longitudinal sectional view showing the third step of the method of manufacturing the NAND type flash memory chip 2 according to the fifth embodiment.

Fig. 7D is a longitudinal sectional view showing the fourth step of the method of manufacturing the NAND type flash memory chip 2 according to the fifth embodiment.

Fig. 7E is a longitudinal sectional view showing the fifth step of the method of manufacturing the NAND type flash memory chip 2 according to the fifth embodiment.

Fig. 7F is a longitudinal sectional view showing the sixth step of the method of manufacturing the NAND flash memory chip 2 according to the fifth embodiment.

Fig. 7G is a longitudinal sectional view showing the seventh step of the method of manufacturing the NAND flash memory chip 2 according to the fifth embodiment.

The above and other objects, features, and advantages of the present invention will become more apparent and understood, Many different embodiments or examples are provided to implement different features of the invention. Embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein the same or similar elements will be denoted by the same reference numerals. The shapes and thicknesses of the embodiments may be exaggerated in the drawings in order to clarify the features of the invention. The disclosure of the present specification is a specific example of the various components and their arrangement in order to simplify the description of the invention. Of course, these specific examples are not intended to limit the invention. For example, if the disclosure of the present specification describes forming a first feature on or above a first feature, that is, it includes an embodiment in which the formed first feature is in direct contact with the second feature. Also included is an embodiment in which additional features are formed between the first feature and the second feature described above, such that the first feature and the second feature may not be in direct contact. In addition, the disclosure of the present disclosure may be repeated in the various examples to make the description more simplified and clear, but the repeated element symbols themselves do not indicate the relationship between different embodiments and/or structures.

In addition, in the case of the numerical description, the words "above" and "below" are used to describe the numerical range. Unless otherwise noted, the relevant numerical range includes the above "above" and "below". The value preceded by the word.

If a plurality of semiconductor memory chips are connected to have an interface The semiconductor wafer of the circuit uses TSV conductors to interconnect the necessary electrodes in a semiconductor process. We believe that the above large ESD circuits, large connection pads 3, etc. can be substantially removed from the semiconductor memory wafer. If a TSV connection pad having a size that is very small relative to the TSV conductor is formed in the semiconductor memory chip, and a large-sized probe test pad for wafer testing is formed on the scribe line, the probe test should also be solved. Problems with the homework. The inventors of the present invention have completed the following embodiments related to the present invention based on the above concept.

[First Embodiment]

Fig. 2 is a plan view showing the configuration of a semiconductor wafer 1 having a plurality of NAND-type flash memory chips 2 according to the first embodiment. The connection pad region according to the conventional example of Fig. 1 is a length in which the horizontal direction (the lateral direction when the wafer is placed on the plane) is required to be an area of about 150 to 200 μm × 100 μm per connection pad. On the other hand, the length of one side of the connection pad for TSV may be 30 μm, and the width of the dicing area SA may be about 80 to 100 μm. Therefore, we believe that if the probe test pad is formed in the dicing area SA, the wafer size can be shortened to a length of 100 to 150 μm.

However, as described above, when a large-width metal such as a probe test pad or the like is formed in the dicing area SA, the dicing SL is diced when the semiconductor wafer 1 is diced: the residual metal is short-circuited between the connection pads. Or a situation in which moisture invades from a partially damaged part of the cut.

In the present embodiment, in order to solve the above problems, it is characterized in that after the wafer test, the probe test pad 4 made of, for example, copper is removed by etching. In the second diagram of the embodiment, a plurality of sides are formed along one side of the edge portion of the NAND flash memory chip 2 formed on the semiconductor wafer 1. The TSV is connected to the pad 5, and on the other hand, a plurality of probe test pads 4 are formed in the dicing area SA located in the vicinity of the opposite side. Here, each of the TSV connection pads 5 is connected to each of the corresponding probe test pads 4 via a wiring layer 10 made of, for example, copper. Further, when the width of the dicing area SA is set to 100 μm, the probe test pad 4 having a width of 80 μm is formed to have an interval SP of about 10 μm on both sides as shown in Fig. 2 . Further, in the NAND-type flash memory chip 2, an electrostatic discharge circuit (ESD circuit) is not formed, and it is preferable to form an ESD circuit on a semiconductor wafer having the above-described interface circuit.

3A to 3E are a series of longitudinal cross-sectional views showing the steps of the method of manufacturing the NAND-type flash memory chip 2 of Fig. 2. Hereinafter, a method of manufacturing the NAND-type flash memory chip 2 will be described with reference to FIGS. 3A to 3E.

In FIG. 3A, a plurality of NAND-type flash memory chips 2 are formed on a semiconductor wafer 1 such as a germanium wafer. In each of the NAND-type flash memory chips 2, a metal-oxide-semiconductor (hereinafter referred to as "MOS") memory transistor 21, a via conductor 22 for a connection line, and the like are formed. In the dicing area SA of the NAND type flash memory chip 2, a probe test pad 4 is formed; in addition, on the NAND type flash memory chip 2, a probe test pad 4 is continuously connected. Circuit layer 10, circuit layer 10 is also referred to as the so-called "pad metal layer". Here, the wiring layer 10 does not require aluminum but copper, and is electrically connected to, for example, the via conductor 22 and the probe test pad 4.

Next, in FIG. 3B, on the NAND type flash memory chip 2 and the wafer region of the wiring layer 10 formed thereon, a protective film 11 is formed, and the protective film 11 is insulating such as SiO ₂ /SiN. membrane. Then, on the probe test pad 4, the protective film 11 is removed by a patterning process using a photolithography etching method of a photoresist. Then, the wafer test is performed in the state of FIG. 3B, and the defective products of the NAND-type flash memory chip 2 are found based on the results of the wafer test. The defective products of these NAND-type flash memory chips 2 are not in the subsequent Used in package stacking processes. Up to this point, the manufacturing method of the conventional semiconductor wafer of FIG. 1 is substantially the same except for the position of the connection pad.

Next, in FIG. 3C, the probe test pad 4 is removed by etching, and on the other hand, other members are not removed. Here, a portion of the wiring layer 10 connected to the dicing area SA of the probe test pad 4 may also be etched. Further, at least one of the probe test pad 4 and a part of the wiring layer 10 in which the above problem occurs may be used as an object of etching.

As shown in FIG. 3C, the exposed surface 10a is exposed on the wiring layer 10 by etching. If the exposed surface 10a of the wiring layer 10 is placed as it is, the possibility of occurrence of a short circuit as described above is greatly reduced, but the possibility of moisture intrusion from this portion is left. In order to prevent such a possibility, the steps of the 3D drawing are performed.

In the 3D view, a protective film 12 is formed on the upper side of the protective film 11 and to protect the exposed surface 10a of the wiring layer 10, and the protective film 12 is made of, for example, epoxy resin. Thereby, the exposed surface 10a is covered by the protective film 12. Thereafter, the through holes 13 penetrating the semiconductor wafer 1 and the NAND flash memory chip 2 in the thickness direction are formed, and then the TSV conductor 14 is filled in the through holes 13. Then, the TSV connection pad 5 is formed on the upper side of the TSV conductor 14, and the TSV connection pad 6 is formed on the lower side of the TSV conductor 14. An example of a specific method of forming this TSV is to use the following sequence of steps.

(1) A through hole 13 for TSV is formed which has a predetermined diameter and a depth that is not penetrated.

(2) A thin insulating film is formed in the through hole 13.

(3) The TSV conductor 14 is formed on the insulating film in the through hole 13 and in the through hole 13, and the TSV conductor 14 is a conductive material.

(4) Polishing the lower surface of the semiconductor wafer 1 of the NAND flash memory chip 2, etching the TSV conductor 14 protruding from the semiconductor wafer 1, and flattening the upper and lower surfaces of the TSV connection pad 5 and the TSV connection pad 6. Chemical.

Further, a dicing die SL located at the center in the width direction of the dicing area SA is cut by a wafer dicing machine (not shown), and a plurality of NAND type flash memory chips are sliced from the semiconductor wafer 1. 2. At this time, since the probe test pad 4 has been etched, the above problem does not occur.

Further, in the 3D drawing, the protective film 12 is removed by etching in the central portion of the dicing area SA in the patterning process by the lithography method, but may be directly cut without being removed. In addition, the above etching may be performed before forming the TSV or after forming the TSV.

In the 3E drawing, a plurality of NAND type flash memory chips 2 which have been judged to be good in the wafer test are stacked in the vertical direction to obtain a large-capacity semiconductor memory device (semiconductor device). Here, the TSV connection pad 5 on the lower side of the NAND flash memory chip 2 is aligned with the TSV connection pad 6 on the lower side of the upper NAND flash memory chip 2, and one is placed. The pair of NAND-type flash memory chips 2 are aligned so that the TSV connection pads 5 and the TSV connection pads 6 are opposed to each other, and the pair of the spacers 15 are bonded to each other via a predetermined spacer film 15 such as a polyimide resin. a NAND type flash memory chip 2, and a connection pad for the TSV 5, Wiring of the connection pad 6 for TSV.

Further, in FIG. 3E, the stacking of the two NAND type flash memory chips 2 is performed. However, the present invention is not limited thereto, and three or more NAND type flash memory chips 2 may be stacked.

As described above, according to the present embodiment, as shown in FIG. 3C, the probe test pad 4 formed in the dicing area SA is removed by etching, and a metal having a large width such as a probe test pad is formed in the dicing area SA. At this time, it is possible to prevent a short circuit between the connection pads caused by the residual metal when the dicing street SL cuts the semiconductor wafer 1.

Further, as shown in FIG. 3D, since the exposed surface 10a of the wiring layer 10 is covered by the protective film 12, the above-mentioned short-circuit problem can be solved, and at the same time, moisture can be prevented from invading from the partial damage at the time of cutting. And cause corrosion.

Further, since the wiring layer 10 and the probe test pad 4 do not need to be joined as in the conventional example, it is not necessary to deposit aluminum on the copper pad, but may be formed of a metal line such as copper.

Further, the gist of the first embodiment can be applied to the following second to fourth embodiments.

[Second embodiment]

Fig. 4 is a plan view showing the configuration of a semiconductor wafer 1 having a plurality of NAND-type flash memory chips 2 according to the second embodiment. The semiconductor wafer 1 according to the second embodiment is compared with the first embodiment of the second embodiment, and is characterized in that, in the dicing area SA, in addition to the probe test pad 4, for example, a NAND type is formed. At least one of the flash memory chips 2 for wafer testing Test circuit 7. Here, since the test circuit 7 is internally connected to the probe test pad 4 or the NAND type flash memory chip 2 by the circuit layer 10, in the step of FIG. 3C, the test circuit 7 is probed by etching. The needle test pad 4 is removed from at least a portion of the circuit layer 10.

According to the second embodiment constructed as above, since the test circuit 7 including the probe test pad 4 formed in the dicing area SA is removed by etching, a large-width metal of the probe test pad or the like is formed in the dicing area SA. It is possible to prevent a short circuit between the connection pads caused by residual metal when the dicing street SL cuts the semiconductor wafer 1. Therefore, the second embodiment has the same functions and effects as those of the first embodiment.

Further, the above-described test circuit 7 is also preferably formed in accordance with a small ESD circuit for a probe test operation. This is because although the test is conducted in an environment that has been statically managed, a minimum ESD countermeasure is required.

[Third embodiment]

Fig. 5 is a plan view showing the configuration of a semiconductor wafer 1 having a plurality of NAND type flash memory chips 2 according to the third embodiment. The semiconductor wafer 1 according to the third embodiment is compared with the first embodiment in FIG. 2 in which a plurality of TSV connection pads 5 are provided along one side of the NAND flash memory chip 2, and is formed in the dicing area. The probe test pads 4 of the SA are connected to the TSVs of the pair of NAND-type flash memory chips 2 having adjacent sides facing the probe test pads 4 via the respective circuit layers 10 and 10, respectively. Connect the pads 5, 5. Here, the probe test pad 4 and a portion of its connected circuit layer 10 are removed at the step of Figure 3C by etching.

That is, in the third embodiment, a plurality of probe test pads 4, A pair of adjacent NAND flash memory chips 2 are used in common, and are connected to the respective TSV connection pads 5 via the respective wiring layers 10. In addition, in FIG. 5, a diagram showing that all of the probe test pads 4 are shared is used. Of course, in the test, a plurality of probe test pads 4 corresponding to the wafer selection signals and the like in the plurality of probe test pads 4 are used. It is better to set each independently.

According to the third embodiment constructed as above, since the probe test pad 4 formed in the dicing area SA is removed by etching, and a large-width metal such as a probe test pad or the like is formed in the dicing area SA, the cutting can be prevented. When the gate SL cuts the semiconductor wafer 1, a short circuit between the connection pads is caused by the residual metal. Therefore, the third embodiment has the same functions and effects as those of the first embodiment.

[Fourth embodiment]

Fig. 6 is a plan view showing the configuration of a semiconductor wafer 1 having a plurality of NAND-type flash memory chips 2 according to the fourth embodiment. The semiconductor wafer 1 according to the fourth embodiment is compared with the first embodiment of FIG. 2 in which a plurality of TSV connection pads 5 are provided along one side of the NAND flash memory chip 2, and is characterized by a NAND type. Each of the two sides of the flash memory chip 2 has a plurality of connection pads 5 for TSV. Here, the two sides of the NAND type flash memory chip 2 are opposite to the other NAND type flash memory chip 2 adjacent to the NAND type flash memory chip 2 in the thickness direction, and the TSV is not formed. Use the side of the connection pad 5. Thereby, the dicing area SA between the pair of NAND-type flash memory chips 2 adjacent to each other in the thickness direction can efficiently and efficiently form the NAND type flash memory chip 2 for any one of them. The needle test pad 4 (connected to the connection pad of the TSV connection pad 5 via the wiring layer 10). In addition, the probe test pad 4 and a portion of the circuit layer 10 connected thereto are in the step of FIG. 3C by etching They were removed together.

According to the fourth embodiment configured as above, since the probe test pad 4 formed in the dicing area SA is removed by etching, and a large-width metal such as a probe test pad or the like is formed in the dicing area SA, the cutting can be prevented. When the gate SL cuts the semiconductor wafer 1, a short circuit between the connection pads is caused by the residual metal. Therefore, the fourth embodiment has the same functions and effects as those of the first embodiment.

[Fifth Embodiment]

7A to 7G are a series of longitudinal cross-sectional views showing the respective steps of the method of manufacturing the NAND-type flash memory chip 2 according to the fifth embodiment. In the seventh to seventh embodiments, the same components as those in the third to third embodiments are given the same reference numerals. The NAND-type flash memory chip 2 according to the fifth embodiment differs from the above-described embodiment in the following points.

(1) After the TSV conductor 14 and the TSV connection pad 5 are formed in advance, the probe test is performed and the probe test pad 4 is removed.

(2) The wiring layer including the probe test pad 4 is not the uppermost layer (the intermediate layer or the lowermost layer).

(3) The metal layer containing the probe test pad 4 is a different layer from the wiring layer 10 connecting the TSV conductor 14 and the TSV connection pad 5.

Hereinafter, a method of manufacturing the NAND-type flash memory chip 2 according to the fifth embodiment will be described with reference to FIGS. 7A to 7G.

Fig. 7A is a cross-sectional view corresponding to Fig. 3A showing the end time of the usual process before the opening of the probe test pad 4. In Fig. 7, the wiring layer 10 and the wiring layer including the probe test pad 4 are different layers, and are connected by the via conductor 23. In the example of FIG. 7A, the wiring layer 10 is larger than the probe-containing test pad 4. The circuit layer also has the structure of the upper layer.

In Fig. 7B, after the back surface of the semiconductor wafer 1 is polished to have a reduced thickness, a through hole 13 is formed from the back surface to the wiring layer 10, and the TSV conductor 14 is filled therein. Next, in FIG. 7C, the TSV connection pad 5 is formed directly above the TSV conductor 14 and on the upper side of the wiring layer 10. On the other hand, a TSV connection pad 6 is formed on the back surface of the semiconductor wafer 1 and directly under the TSV conductor 14. Then, in the seventh drawing, the portion of the cutting portion SA in the horizontal direction and the portion directly above the probe test pad 4 are anisotropically etched to a predetermined width to form the opening portion 16, and then used. The probe test pad 4 is subjected to a probe test.

Further, in FIG. 7E, the central portion of the probe test pad 4 is further etched to form an opening portion 17 larger than the opening portion 16. At this time, a part of the probe test pad 4 remains. Next, in FIG. 7F, a protective film 18 is formed on the upper surface of the semiconductor wafer 1 and inside the opening 17, and the protective film 18 is an insulating film. Then, in the 7Gth diagram, the protective film 18 is etched to expose the connection pad 5 for TSV. At this time, the surface 4a of a portion of the portion of the residual probe test pad 4 is protected by the protective film 18. Then, the semiconductor wafer 1 is cut along the dicing street SL, and is divided into a plurality of NAND-type flash memory chips 2. The plurality of NAND type flash memory chips 2 formed as described above can be laminated in the same manner as shown in FIG. 3E.

As described above, according to the present embodiment, by performing the probe test on the semiconductor wafer 1 after forming the TSV conductor 14, not only the defects in the usual process can be removed, but also the TSV conductor 14 and the TSV can be removed. Defects that occur with the formation of the connection pads 5, 6. For example, it is possible to mask the functional defects caused by the short circuit of the TSV connection pads 5, 6 and the substrate, and the occurrence of defects.

[variation]

In the above embodiment, each of the NAND-type flash memory chips 2 is cut out by cutting a plurality of NAND-type flash memory chips 2 formed on the semiconductor wafer 1. The present invention is not limited thereto, and the NAND type flash memory chip 2 may be replaced by a DRAM or other memory chip, another type of semiconductor wafer or the like.

In FIGS. 3C and 7E, the probe test pad 4 and its connected circuit layer 10 are removed by etching, but the present invention is not limited thereto, and the probe test pad 4 may be removed. The probe test strip 4 is in the form of at least one of a portion of the wiring layer 10.

Further, the test circuit 7 according to the second embodiment can also be applied to the first embodiment and the third to fifth embodiments.

Although the present invention has been disclosed in the above preferred embodiments, the present invention is not intended to limit the invention, and it is possible to make a few changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.

[Industrial availability]

As described in detail above, according to the present invention, after the wafer is tested, the plurality of probe test pads or a portion of the circuit layer or the plurality of probe test pads and the above are removed by etching. A portion of the wiring layer is removed by etching. Therefore, the problem of the deterioration of the reliability of the semiconductor wafer caused by the residual pad metal when the dicing die cuts the semiconductor wafer can be solved.

1‧‧‧Semiconductor wafer

2‧‧‧NAND flash memory chip

5‧‧‧TSV connection pad

6‧‧‧TSV connection pad

10‧‧‧Line layer

10a‧‧‧ exposed surface

11‧‧‧Protective film

12‧‧‧Protective film

13‧‧‧through holes

14‧‧‧TSV conductor

21‧‧‧MOS memory transistor

22‧‧‧Interlayer conductor

SA‧‧ cutting area

SL‧‧‧ cutting road

Claims (14)

A semiconductor wafer, comprising: a plurality of semiconductor wafers; a plurality of probe test pads formed on a dicing region of the semiconductor wafer; a plurality of through-silicon vias formed on the semiconductor wafer; and a circuit layer Each of the probe test pads is respectively connected to each of the through-twisted vias, wherein the circuit layer includes a first portion connected to each of the probe test pads and a second portion connected to each of the through-twisted vias. The first portion and the second portion are different layers and are connected by a via conductor; wherein the semiconductor wafer is configured to remove a portion of the plurality of probe test pads by etching after the wafer is tested, An exposed surface of the removed probe test pad is located in the wafer cutting area; and a protective film covering the exposed surface. The semiconductor wafer according to claim 1, wherein the plurality of through-silicon vias are formed in advance, and a part of the plurality of probe test pads is removed by etching after the wafer is tested. The semiconductor wafer of claim 1, wherein the circuit layer connected to the plurality of probe test pads is not the uppermost layer. The semiconductor wafer of claim 1, wherein the plurality of probe test pads are formed along one or both sides of the semiconductor wafer. The semiconductor wafer of claim 1, wherein the plurality of probe test pads are commonly used to connect to the plurality of semiconductor wafers via the wiring layer. The semiconductor wafer according to claim 1, further comprising a test circuit. The semiconductor wafer according to claim 1, wherein the probe test pad is made of copper. A semiconductor wafer, characterized in that, in the semiconductor wafer according to any one of claims 1 to 7, the plurality of semiconductor wafers are separated by cutting along a predetermined scribe line of the dicing area. . The semiconductor wafer according to claim 8, wherein the semiconductor wafer is a semiconductor memory wafer. A semiconductor device characterized in that a plurality of semiconductor wafers according to claim 8 or 9 are laminated by connecting through straight through-holes of semiconductor wafers adjacent to each other in a thickness direction, thereby constituting a semiconductor device . A method of fabricating a semiconductor wafer, comprising: forming a plurality of probe test pads in a dicing region of a semiconductor wafer having a plurality of semiconductor wafers; forming a plurality of wiring layers on said semiconductor wafer; and forming said plurality of wiring layers on said semiconductor wafer Forming a plurality of through-twisted vias connected to the respective circuit layers; wherein each of the circuit layers includes a first portion connected to one of the probe test pads and a second portion connected to each of the through-twisted vias a portion and the second portion are different layers and connected by a via conductor; and after the wafer is tested, a portion of the plurality of probe test pads are removed by etching, wherein the probe test pad is not removed An exposed surface is located on the wafer In the cutting zone; and forming a protective film covering the exposed surface. The method for fabricating a semiconductor wafer according to claim 11, wherein after the plurality of through-silicon vias are formed in advance, a wafer test is performed, and a part of the plurality of probe test pads is removed by etching. . A method of manufacturing a semiconductor wafer according to any one of claims 11 to 12, wherein the plurality of the semiconductor wafers are cut by a predetermined scribe line along the cutting zone. Semiconductor wafer. A method of manufacturing a semiconductor device according to the invention of claim 13, wherein the plurality of semiconductor wafers are connected to each of the through-crystal twinned semiconductor wafers adjacent to each other in the thickness direction In this way, a layer is formed, thereby constituting a semiconductor device.