JP2014071932A - Multi-chip memory module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a laminated multi-chip memory module capable of high speed operation without reducing yield even if wafers are laminated with each other and without increase in a mounting area in a multi-chip memory module formed by laminating a plurality of memory chips having a through-silicon via.SOLUTION: A multi-chip memory module is characterized in that a redundant memory chip having a redundant memory cell provided therein is included in a plurality of memory chips, a memory circuit storing information on a defective place is assembled in the other memory chip, a function in which an access destination is switched to the redundant memory chip is provided when the defective place is accessed, and normal operation is maintained by the redundant memory cell corresponding to the defective place.

Description

  The present invention relates to a semiconductor memory device, and more particularly to a defect relief function of a chip stack type large capacity semiconductor memory device using a through silicon via.

  The storage capacity required for semiconductor memories such as DRAMs has been increasing year by year, and in recent years, a multi-chip memory module in which a plurality of memory chips as shown in FIG. 1 are stacked has been proposed. In FIG. 1, symbol 1 indicates a memory chip, and here, an example in which four memory chips are stacked is shown. Each memory chip 1 is connected to the package substrate 2 by wires 3. With this multi-layer multichip memory module 14, it is possible to simultaneously realize a larger capacity and a smaller size than conventional products. However, since it is necessary to connect each chip to be stacked and the package substrate by wire bonding, as the number of chips to be stacked increases, the number of wires also increases, ensuring space for wire loops and wire bonding pads on the package substrate. As a result, it is difficult to secure a large number of chips.

  On the other hand, recently, a chip stacking technique using a through silicon via (TSV; Through Silicon Via) as shown in FIG. 2 has been developed. TSV is a through electrode provided on the silicon substrate, and electrical connection between the stacked chips and between the chip and the package substrate can be performed via the TSV. In FIG. 2, symbol 1 indicates a memory chip, and here, an example in which eight memory chips are stacked is shown. Each memory chip and between the memory chip and the package substrate 2 are connected via TSV4. This eliminates the need for bonding wires that have been used in the past, so it is possible to increase the number of chips to be stacked, further reducing the distance between chips and between the chip and the package substrate, which is advantageous for high-speed signal transmission, It is attracting attention as a technology that can simultaneously realize large capacity, small size, and high speed.

  Here, a manufacturing process of a multi-chip memory module by a chip stacking technique using TSV will be described with reference to FIG. FIG. 3A shows a memory wafer 6 with TSV before being stacked. FIG. 3B is a view in which two memory wafers 6 with TSV are stacked. Wafers are joined to each other by micro solder bumps 8 through TSVs 4 as shown in FIG. The joining of the wafers is repeated for the number of wafers to be stacked. In this example, eight wafers are stacked. FIG. 3C shows a state where the lamination is completed. Next, as shown in FIG. 3D, dicing is performed by the dicer blade 5 to cut out into chip-sized modules. FIG. 3E shows the chip size module 7 cut out. Thereafter, as shown in FIG. 3F, the chip size module 7 is mounted on the package substrate 2 to obtain a multichip memory module.

In this way, chip stacking using TSV is an effective technique for increasing the capacity as compared with chip stacking by conventional wire bonding, but the defect rate as a module increases as the number of chips stacked increases. There is. For example, assuming that the yield of chips in a wafer is 80%, when two wafers are stacked, the module yield decreases to 64% as a square of 80%, 51% for three, and 17% for eight. End up. Usually, a redundancy circuit is mounted on a memory chip for defect relief. The redundant circuit stores the information of the defective address when there is a defect in the memory cell, and switches the access destination to the normal memory cell for redundancy formed in the same chip when the defective address is accessed. It has a function to rescue the chip. As a method for storing information on defective addresses, a method is generally used in which a defective address is acquired when a wafer is subjected to a probing test, and wiring of a defective address storage circuit is cut by a laser. In addition, a method of mounting a small-capacity nonvolatile memory and storing a defective address in the nonvolatile memory is also conceivable. However, the number of memory cells that can be relieved by such a method is limited. This is because a large number of redundant memory cells are required to relieve a large number of defective memory cells, and the chip size increases accordingly. Therefore, when a failure occurs in a large number of memory cells, the repair is impossible, and such a chip is determined as a defective chip.

  Therefore, when performing chip stacking using TSV, instead of stacking wafers, dicing is performed in advance except for the base wafer, and only the chips determined to be non-defective are sequentially stacked on the base wafer. The method of doing is often adopted. At this time, the wafer as a base is also tested prior to stacking, and the position of the non-defective chips is known, whereby a multichip memory module in which only non-defective chips are stacked can be obtained.

  However, in such a method, dicing needs to be repeated for the number of wafers, and further, alignment and bonding processes need to be repeated for the number of chips at the time of stacking, which is disadvantageous in terms of cost. . Therefore, a technique as disclosed in Patent Document 1 is disclosed. In Patent Document 1, in order to relieve a defect of a memory chip, defect information of each memory chip is stored in a separately stacked controller chip, and if a defective cell of the memory chip is accessed, it is mounted in another package. A method of accessing the redundant memory chip is employed.

JP 2010-45166 A

  However, in the method disclosed in Patent Document 1, it is necessary to mount a redundant memory in a separate package in addition to the multichip memory module, which is disadvantageous in terms of mounting area. Further, since the redundancy memory is a separate package, there is a disadvantage that a delay occurs in the access time when redundancy is selected, and it cannot be applied to a high-speed system.

  Therefore, in the present invention, in a multi-chip memory module in which chips are connected between TSs and between a chip and a package substrate through TSV, the yield is not lowered even if the wafers are stacked, and the mounting area is not increased. Another object of the present invention is to provide a stacked multichip memory module that can operate at higher speed.

In order to solve the above problems, the present invention is a multichip memory module in which a plurality of memory chips having through silicon vias are stacked,
The plurality of memory chips include a redundancy memory chip provided with redundancy memory cells,
Other memory chips have built-in memory circuits that store information on defective parts,
When a defective portion is accessed, the access destination is switched to a redundant memory chip, and normal operation is maintained by a redundant memory cell corresponding to the defective portion.

  In the present invention, the memory circuit is a nonvolatile memory.

  Furthermore, the present invention is characterized in that no redundant memory cell is mounted on the memory chip except for the redundant memory chip.

In the multichip memory module according to the present invention, a memory circuit for storing information on a defective portion is incorporated in the memory chip, and a redundant memory chip is stacked on the same multichip memory module. Can be secured. For this reason, even when the lamination of wafers is adopted as a method of laminating memory chips, it is possible to manufacture at a low cost without reducing the yield.
Further, by connecting the memory chips with a short distance via the TSV, even when accessing the redundant cell, a high-speed operation is possible with little delay.

  Further, in the present invention, since the memory circuit for storing the information on the defective portion is a nonvolatile memory, it is possible to store information on many defective portions with a smaller area than the method of cutting the fuse with a laser.

  Furthermore, in the present invention, since no redundant memory cell is mounted on the memory chip, the chip area can be reduced.

It is explanatory drawing which showed the example of the conventional multilayer multichip memory module using wire bonding in the cross section. It is explanatory drawing which showed the example of the lamination | stacking multichip memory module using TSV in the cross section. It is explanatory drawing of the example of a manufacturing process of the lamination | stacking multichip memory module using TSV. It is explanatory drawing which showed an example of embodiment of the multichip memory module of this invention in the cross section. It is explanatory drawing of an example of the circuit block of the multichip memory module of this invention. It is explanatory drawing of the example of a manufacturing process of the multichip memory module of this invention.

  An example of an embodiment of the present invention will be described with reference to FIGS. FIG. 4 is an example of a multi-chip memory module 14 according to the present invention. A plurality of memory chips 1 on which TSVs 4 are formed and a redundant memory chip 11 are stacked on the package substrate 2. In this example, a total of eight memory chips are stacked. Each memory chip and the redundant memory chip are connected through a TSV. The chips and between the chip and the package substrate are joined by micro solder bumps (not shown).

FIG. 5 is an example of a circuit block of a multichip memory module according to the present invention. In FIG. 5, eight memory chips 1 to 8 are mounted, and one redundant memory chip is mounted. The memory chip will be described in detail only for the memory chip 1 as a representative, but the memory chips 2 to 8 have the same circuit configuration. A defect information storage circuit is incorporated in the memory chip, and when an attempt is made to access a defective address in the memory chip, the address is converted into a redundancy address. The converted redundancy address is transmitted to the redundancy memory chip to access the address in the redundancy memory chip. Further, when a defective address is accessed, a switching control signal is output from the defect information storage circuit and transmitted to the switching circuit. When the normal address is accessed, the switching circuit inputs / outputs data to / from the memory cells in the memory chip, and when trying to access a defective address, the switching circuit transfers data to / from the memory cells of the redundant memory chip. Switch the data input / output destination to perform input / output. By switching the data input / output with respect to the defective address to the input / output with respect to the normal address of the redundant memory cell in this way, even if there is a defective address in the memory chip, the module does not become defective and is used in the same way as a normal product. it can. As for the relief function by transferring the defective address to the redundant memory chip, it is desirable to provide all the memory chips to be mounted as shown in FIG.

In a conventional memory chip, redundant memory cells are mounted in the same chip. In that case, the redundant memory capacity that can be secured is small, and when there are many defective cells in the same chip, the redundancy function is used. In some cases, it was impossible to remedy a defect.
However, according to the present invention, since one whole memory chip can be used for redundancy, a much larger capacity can be relieved than before, so that the stacking of wafers can be performed without reducing the yield. The multi-chip memory module can be manufactured.

  In addition, since the memory chip and the redundant memory chip are connected via the TSV, the operation can be performed at a higher speed than the conventional connection by wire bonding.

  Furthermore, since it is not necessary to mount redundant memory cells in the memory chip, the chip area can be reduced.

  On the other hand, in addition to the redundant memory cell (memory cell in FIG. 5) corresponding to the defective portion, the redundant memory chip further includes a redundant memory cell (see FIG. 5) in order to relieve the defective cell of the redundant memory chip itself. Then, it is desirable to mount redundant memory cells. With respect to these redundant memory cells, a larger capacity than before can be allocated for redundancy, so that an improvement in yield can be expected.

Next, an example of a method for manufacturing a multichip memory module of the present invention will be described with reference to FIG.
First, as shown in FIG. 6A, a probing test is performed on a wafer on which a wafer process is completed and chips having a memory chip circuit as shown in FIG. Although FIG. 6A shows one each of the memory wafer 6 and the redundant memory wafer 13, the probing test is actually performed on all the wafers to be stacked. The probing test is performed by bringing the tip of the prober 12 connected to an inspection apparatus such as an LSI tester into contact with an electrode for probing test provided in advance on each chip. Here, for a chip in which a defect is found, the defect address information is stored in the defect information storage circuit of each chip. As a mechanism for storing defective addresses, a method of cutting a conductor wiring for storing defective information with a laser is generally widely used. However, in order to store a large number of addresses, a large wiring area is required. Therefore, it is desirable to write to a non-volatile memory that can store many addresses in a smaller area. As the nonvolatile memory, PROM (Programmable Read Only Memory), EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory, etc.) can be used.

  Next, as shown in FIG. 6B, the respective wafers are stacked. Here, a case where eight memory chip wafers and one redundant memory chip wafer are stacked is shown, but in the present invention, the number of these wafers is not particularly limited. Further, in this figure, the redundant memory chip wafer is arranged on the top, but there is no particular limitation on this arrangement. As an example of a method for connecting the wafers, FIG.

  Next, as shown in FIG. 6C, the laminated wafer is diced into each chip. Dicing can be performed by a general dicer.

  Next, the stacked and diced chip size module 7 is mounted on the package substrate 2 as shown in FIG. The chip size module 7 and the package substrate 2 can be connected to each other by a small solder bump or the like (not shown).

  The present invention relates to a semiconductor memory device, and can be used particularly for a chip stack type large capacity semiconductor memory device using TSV.

DESCRIPTION OF SYMBOLS 1 ... Memory chip 2 ... Package board 3 ... Bonding wire 4 ... TSV (through silicon via)
5 ... Dicer blade 6 ... Memory wafer 7 ... Chip size module 11 ... Redundant memory chip 12 ... Prober 13 ... Redundant memory wafer 14 ... Multi-chip memory module

Claims (3)

A multi-chip memory module in which a plurality of memory chips having through silicon vias are stacked,
The plurality of memory chips include a redundancy memory chip provided with redundancy memory cells,
Other memory chips have built-in memory circuits that store information on defective parts,
A multi-chip memory module having a function of switching an access destination to a redundant memory chip when a defective part is accessed, and maintaining normal operation by a redundant memory cell corresponding to the defective part.   The multi-chip memory module according to claim 1, wherein the storage circuit is a nonvolatile memory.   3. The multi-chip memory module according to claim 1, wherein no redundant memory cell is mounted on the memory chip except for the redundant memory chip.