JP5976055B2 - Semiconductor wafer, semiconductor chip, semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor chip such as a DRAM (Dynamic Random Access Memory) and a NAND flash memory and a manufacturing method thereof, a semiconductor wafer including a plurality of semiconductor chips, a manufacturing method thereof, and a semiconductor in which a plurality of semiconductor chips are stacked. The present invention relates to an apparatus and a manufacturing method thereof.

  Currently, a through silicon via (hereinafter referred to as TSV (Through Silicon Via)) technology has been developed and put into practical use by many semiconductor manufacturing companies, and is a large capacity DRAM or NAND flash memory having a TSV pad. It has been put to practical use to manufacture a larger capacity memory device by stacking the semiconductor memory chips in the thickness direction. For example, the Hybrid Memory Cube Consortium is researching and developing high-performance and large-capacity DRAMs manufactured using TSV technology.

JP2013-105996A JP 2013-0665393 A JP 2005-072457 A JP 2004-342725 A JP 2013-098535 A JP 2005-026582 A

  FIG. 1 is a plan view showing a configuration of a semiconductor wafer 1 including a plurality of NAND flash memory chips 2 according to a conventional example. As is clear from FIG. 1, in the plurality of semiconductor memory chips 2 on the semiconductor wafer 1, similarly, large pads 3 for probing test and bonding are juxtaposed and occupy a large area. Further, an electrostatic charge discharge circuit (hereinafter referred to as an ESD circuit) is formed on the pad 3 and similarly occupies a large area. Therefore, if these pads and ESD circuits can be eliminated from the semiconductor memory chip 2, the chip size can be reduced and the cost can be reduced. In FIG. 1, SA is a scribe area between the semiconductor memory chips 2, and SL indicates a scribe line when cutting each semiconductor memory chip 2.

  For example, in Patent Document 1, a plurality of DRAM chips are stacked by TSV on a semiconductor chip having an interface circuit. Since this DRAM chip is dedicated to stacking, no bonding pad or ESD circuit is required, but a pad for probing test is provided. Similarly, Patent Document 2 discloses a semiconductor device in which a plurality of semiconductor memory chips are connected and stacked by bonding or TSV, and further connected to a semiconductor chip having an interface circuit. However, bonding and probing are disclosed. A pad for testing is provided.

  In Patent Documents 3 and 4, a plurality of probing pads are formed in the scribe region, and probing can be easily performed. Further, in Patent Documents 5 and 6, a plurality of TSV pads are formed in the scribe region.

However, as described in Patent Documents 3 and 4, for example, when a plurality of probing pads are formed in the scribe region, a large wide metal such as the probing pads may cause the following problem of reliability deterioration. It was.
(1) A short circuit between the pads due to the metal remaining when the semiconductor wafer is diced by a scribe line, and (2) a connection metal in which moisture extends from the pad into the chip due to partial damage when the semiconductor wafer is diced. Invasion along the line and corrosion.

  An object of the present invention is to form a semiconductor memory chip probing pad stacked and connected by TSV on a scribe line, and to ensure the reliability of the semiconductor chip based on the pad metal remaining and the damage when the semiconductor wafer is diced by the scribe line. A semiconductor chip and a manufacturing method thereof, a semiconductor wafer including a plurality of semiconductor chips, a manufacturing method thereof, a semiconductor device in which a plurality of semiconductor chips are stacked, and a manufacturing method thereof are provided. There is to do.

The semiconductor wafer according to the present invention is a semiconductor wafer comprising a plurality of semiconductor chips,
A plurality of probing pads formed in the scribe region of the semiconductor wafer;
A plurality of through silicon vias formed on the semiconductor chip;
A wiring layer for connecting each probing pad to each silicon through electrode,
After the wafer test, at least one of the plurality of probing pads and part of the wiring layer is removed by etching.

  In the semiconductor wafer, the plurality of through silicon vias are first formed, and after the wafer test, at least one of the plurality of probing pads and the wiring layer is removed by etching. To do.

  The semiconductor wafer may further include a protective film formed to cover an exposed surface of the wiring layer remaining when a part of the wiring layer is removed.

  Furthermore, in the semiconductor wafer, a wiring layer connected to the plurality of probing pads is not the uppermost layer.

  Furthermore, in the semiconductor wafer, the wiring layer connected to each probing pad is different from the wiring layer connected to each silicon through electrode.

  In the semiconductor wafer, the plurality of probing pads are formed along one side or two sides of the semiconductor chip.

  Further, in the semiconductor wafer, the plurality of probing pads are commonly used by being connected to the plurality of semiconductor chips via the wiring layer.

  The semiconductor wafer further includes the plurality of probing pads and a test circuit in place of the plurality of probing pads.

  In the semiconductor wafer, the probing pad is made of Cu.

  The semiconductor chip according to the present invention is characterized in that a plurality of semiconductor chips are separated from each other by dicing along a predetermined scribe line in the scribe region in the semiconductor wafer.

  In the semiconductor chip, the semiconductor chip is a semiconductor memory chip.

  The semiconductor device according to the present invention is characterized in that the semiconductor device is configured by stacking the plurality of semiconductor chips so as to connect the through silicon vias of the semiconductor chips adjacent to each other in the thickness direction.

A method for producing a semiconductor wafer according to the present invention comprises:
Forming a plurality of probing pads in a scribe region of a semiconductor wafer having a plurality of semiconductor chips;
Forming a plurality of wiring layers on the semiconductor chip;
Forming a plurality of through silicon vias connected to each wiring layer on the semiconductor chip;
After the wafer test, at least one of the plurality of probing pads and the wiring layer is removed by etching.

  In the method for manufacturing a semiconductor wafer, a wafer test is performed after the plurality of through silicon vias are first formed, and at least one of the plurality of probing pads and the wiring layer is removed by etching. To do.

  The semiconductor wafer manufacturing method further includes forming a protective film so as to cover an exposed surface of the wiring layer remaining when a part of the wiring layer is removed.

A method for manufacturing a semiconductor chip according to the present invention is the above-described method for manufacturing a semiconductor wafer,
The method further includes separating the plurality of semiconductor chips by dicing along a predetermined scribe line in the scribe region.

A method for manufacturing a semiconductor device according to the present invention is the above-described method for manufacturing a semiconductor chip.
The semiconductor device is further configured by stacking the plurality of semiconductor chips so as to connect the through silicon vias of the semiconductor chips adjacent to each other in the thickness direction.

  According to the present invention, after the wafer test, at least one of the plurality of probing pads and the wiring layer is removed by etching. Therefore, it is possible to solve the problem of deterioration of the reliability of the semiconductor chip based on the pad metal remaining when the semiconductor wafer is diced by the scribe line.

It is a top view which shows the structure of the semiconductor wafer 1 provided with the several NAND type flash memory chip 2 which concerns on a prior art example. 1 is a plan view showing a configuration of a semiconductor wafer 1 including a plurality of NAND flash memory chips 2 according to a first embodiment. FIG. 4 is a longitudinal sectional view showing a first step showing a method for manufacturing the NAND flash memory chip 2 in FIG. 2. FIG. 10 is a longitudinal sectional view showing a second step in the method for manufacturing the NAND flash memory chip 2 in FIG. 2. FIG. 11 is a longitudinal sectional view showing a third step showing the method for manufacturing the NAND flash memory chip 2 in FIG. 2. FIG. 11 is a longitudinal sectional view showing a fourth step, which shows a method for manufacturing the NAND flash memory chip 2 in FIG. 2. FIG. 10 is a longitudinal sectional view showing a fifth step showing the method for manufacturing the NAND flash memory chip 2 in FIG. 2. FIG. 6 is a plan view showing a configuration of a semiconductor wafer 1 including a plurality of NAND flash memory chips 2 according to a second embodiment. It is a top view which shows the structure of the semiconductor wafer 1 provided with the several NAND type flash memory chip 2 which concerns on 3rd Embodiment. It is a top view which shows the structure of the semiconductor wafer 1 provided with the several NAND type flash memory chip 2 which concerns on 4th Embodiment. It is a longitudinal cross-sectional view which shows the 1st process which shows the manufacturing method of the NAND type flash memory chip 2 concerning 5th Embodiment. It is a longitudinal cross-sectional view which shows the 2nd process which shows the manufacturing method of the NAND type flash memory chip 2 concerning 5th Embodiment. It is a longitudinal cross-sectional view which shows the 3rd process which shows the manufacturing method of the NAND type flash memory chip 2 concerning 5th Embodiment. It is a longitudinal cross-sectional view which shows the 4th process which shows the manufacturing method of the NAND type flash memory chip 2 concerning 5th Embodiment. It is a longitudinal cross-sectional view which shows the 5th process which shows the manufacturing method of the NAND type flash memory chip 2 concerning 5th Embodiment. It is a longitudinal cross-sectional view which shows the 6th process which shows the manufacturing method of the NAND type flash memory chip 2 concerning 5th Embodiment. It is a longitudinal cross-sectional view which shows the 7th process which shows the manufacturing method of the NAND type flash memory chip 2 concerning 5th Embodiment.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

  If a plurality of semiconductor memory chips are connected to a semiconductor chip having an interface circuit, if the necessary electrodes are connected to each other using a TSV conductor in a semiconductor process, the large ESD circuit and the large pad 3 described above are basically used. Can be removed from the semiconductor memory chip. A probing pad for TSV connection of a small size that is sufficiently large with respect to the TSV conductor is formed in the semiconductor memory chip, and a probing work of a large size for wafer test can be solved by forming the probing pad on the scribe. Will. Based on these findings, the present inventors have devised the following embodiments according to the present invention.

First embodiment.
FIG. 2 is a plan view showing a configuration of a semiconductor wafer 1 including a plurality of NAND flash memory chips 2 according to the first embodiment. The pad region according to the conventional example of FIG. 1 requires a length in the horizontal direction (referred to as a lateral direction when a chip is mounted on a plane) having an area of about 150 to 200 μm × 100 μm per pad. On the other hand, the length of one side of the TSV pad may be 30 μm or less, and the width of the scribe area SA may be about 80 to 100 μm. Therefore, if the probing pad is formed in the scribe area SA, it is considered that the chip size can be shortened by a length of 100 to 150 μm.

  However, as described above, when a large and wide metal such as a probing pad is formed in the scribe area SA, the semiconductor wafer 1 is short-circuited between the pads by the metal remaining when the semiconductor wafer 1 is diced by the scribe line SL, or There was a problem that moisture may invade from the part of the partial damage when dicing and corrode.

  In the present embodiment, in order to solve the problem, the probing pad 4 made of Cu, for example, is removed by etching after the wafer test. In FIG. 2 of the present embodiment, a plurality of TSV pads 5 are formed along one side of the edge portion of the semiconductor memory chip 2 formed on the semiconductor wafer 1, and are located in the vicinity facing the one side. A plurality of probing pads 4 are formed in the scribe area SA. Here, each TSV pad 5 is connected to each corresponding probing pad 4 via a wiring layer 10 made of, for example, Cu. When the width of the scribe region SA is 100 μm, the probing pad 4 having a width of 80 μm is formed with a space SP of about 10 μm on both sides as shown in FIG. Further, it is preferable that the electrostatic charge discharge circuit (ESD circuit) is not formed on the semiconductor memory chip 2 and is formed on the semiconductor chip having the interface circuit, for example.

  3A to 3E are longitudinal sectional views showing respective steps showing a method of manufacturing the NAND flash memory chip 2 of FIG. Hereinafter, a method of manufacturing the NAND flash memory chip 2 will be described with reference to FIGS. 3A to 3E.

  In FIG. 3A, a plurality of NAND flash memory chips 2 are formed on a semiconductor wafer 1 which is a silicon wafer, for example. Each NAND flash memory chip 2 is formed with a MOS memory transistor 21 and a via conductor 22 for connection wiring. A probing pad 4 is formed in the scribe area SA of the memory chip 2, and a wiring layer 10 called a “pad metal layer” that is continuously connected to the probing pad 4 is formed on the memory chip 2. Has been. Here, the wiring layer 10 does not need to be Al but may be Cu. For example, the via conductor 22 and the probing pad 4 are electrically connected.

Next, in FIG. 3B, a protective film 11 which is an insulating film such as SiO ₂ / SiN is formed on the chip area of the semiconductor memory chip 2 and the wiring layer 10 formed thereon. Then, the protective film 11 is removed on the probing pad 4 by patterning by a photolithography method using a resist. Then, a wafer test is performed in the state of FIG. 3B, and a defective semiconductor memory chip 2 is found based on the result of the wafer test, and the defective semiconductor memory chip 2 is not used in the subsequent assembly stack. The process so far can be said to be the same as the conventional method of manufacturing the semiconductor memory chip of FIG.

  Next, in FIG. 3C, the probing pad 4 is removed by etching while the other components are not removed. Here, a part of the wiring layer 10 in the scribe area SA connected to the probing pad 4 may also be etched. The object to be etched may be at least one of the probing pad 4 and a part of the wiring layer 10 where the above-described problems occur.

  By the etching, the exposed surface 10a is exposed on the wiring layer 10 as shown in FIG. 3C. If the exposed surface 10a of the wiring layer 10 is left as it is, the possibility of occurrence of a short circuit as described above is greatly reduced, but the possibility of moisture intrusion from this portion remains. In order to prevent this, the process of FIG. 3D is performed.

In FIG. 3D, a protective film 12 made of, for example, an epoxy resin is formed on the upper side of the protective film 11 and so as to protect the exposed surface 10a of the wiring layer 10. As a result, the exposed surface 10 a is covered with the protective film 12. After that, a through hole 13 that penetrates the semiconductor wafer 1 and the semiconductor memory chip 2 in the thickness direction is formed, and then the TSV conductor 14 is filled into the through hole 13. The pad 5 is formed on the upper side of the TSV conductor 14 and the pad 6 is formed on the lower side thereof. The following procedure is used as an example of a specific method for forming the TSV.
(1) The TSV through hole 13 having a predetermined diameter and a depth not penetrating is formed.
(2) A thin insulating film is formed in the through hole 13.
(3) The TSV conductor 14 which is a conductive material is filled in the through hole 13 on the insulating film in the through hole 13.
(4) The lower surface of the semiconductor wafer 1 of the semiconductor memory chip 2 is polished, and the TSV conductor 14 protruding from the semiconductor wafer 1 is etched to flatten the upper and lower surfaces that become the pads 5 and 6.

  Further, a plurality of semiconductor memory chips 2 are diced and cut out from the semiconductor wafer 1 using a chip cutter (not shown) along the scribe line SL located at the center in the width direction of the scribe area SA. At this time, since the probing pad 4 has already been etched, the above-mentioned problem does not occur.

  In FIG. 3D, the protective film 12 is etched away at the central portion of the scribe region SA by patterning by photolithography, but may be diced without being removed in this way. Further, this etching may be performed before or after the formation of TSV.

  In FIG. 3E, a plurality of semiconductor memory chips 2 determined as non-defective semiconductor memory chips 2 in the wafer test are stacked in the vertical direction to obtain a large-capacity semiconductor memory device (semiconductor device). Here, the upper pad 5 of the lower semiconductor memory chip 2 is aligned with the lower pad 6 of the upper semiconductor memory chip 2 so that the pads 5 and 6 face each other in the pair of semiconductor memory chips 2. The pads 5 and 6 are connected to each other by bonding them through a predetermined spacer film 15 such as polyimide resin.

  In FIG. 3E, two semiconductor memory chips 2 are stacked. However, the present invention is not limited to this, and three or more semiconductor memory chips 2 may be stacked.

  As described above, according to the present embodiment, as shown in FIG. 3C, the probing pad 4 formed in the scribe area SA is removed by etching, so that a large wide metal such as a probing pad is formed in the scribe area SA. In this case, it is possible to prevent a short circuit between the pads due to the metal remaining when the semiconductor wafer 1 is diced by the scribe line SL.

  Further, as shown in FIG. 3D, the exposed surface 10a of the wiring layer 10 is covered with the protective film 12, so that the above-mentioned short-circuit problem can be solved and moisture enters from the part of the partial damage when dicing. To prevent corrosion.

  Further, since there is no need to bond the wiring layer 10 and the probing pad 4 as in the conventional example, it is not necessary to deposit Al on the Cu pad, and a metal wiring such as Cu may be used.

  In addition, about the summary of 1st Embodiment, it is applicable also to the following 2nd-4th embodiment.

Second embodiment.
FIG. 4 is a plan view showing a configuration of a semiconductor wafer 1 including a plurality of NAND flash memory chips 2 according to the second embodiment. Compared to the first embodiment of FIG. 2, the semiconductor wafer 1 according to the second embodiment has at least one for wafer testing, for example, a semiconductor memory chip 2 in addition to the probing pad 4 in the scribe area SA. One test circuit 7 is formed. Here, since the test circuit 7 is connected to the probing pad or the inside of the semiconductor memory chip 2 by the wiring layer 10, at least the wiring layer 10 of the test circuit 7 together with the probing pad 4 is removed by etching in the process of FIG. 3C.

  According to the second embodiment configured as described above, since the wiring layer 10 including the probing pad 4 formed in the scribe area SA is removed by etching, a large wide metal such as the probing pad is formed in the scribe area SA. When formed, it is possible to prevent a short circuit between the pads due to the metal remaining when the semiconductor wafer 1 is diced by the scribe line SL. Therefore, the second embodiment has the same operational effects as the first embodiment.

The test circuit is preferably formed with a small ESD circuit for a probing operation. This is because a minimum ESD countermeasure is required although it is a test in a controlled environment.

Third embodiment.
FIG. 5 is a plan view showing a configuration of a semiconductor wafer 1 including a plurality of NAND flash memory chips 2 according to the third embodiment. The semiconductor wafer 1 according to the third embodiment has a probing formed in the scribe area SA as compared to the first embodiment of FIG. 2 having a plurality of TSV pads 5 along one side of the semiconductor memory chip 2. The pad 4 is characterized in that it is connected to the TSV pads 5 and 5 of the pair of semiconductor memory chips 2 each having one side facing each other through the wiring layers 10 and 10, respectively. Here, the probing pad 4 and a part of the wiring layer 10 connected to the probing pad 4 are removed by etching together with the probing pad 4 in the step of FIG. 3C.

  That is, in the third embodiment, the plurality of probing pads 4 are connected to the plurality of semiconductor memory chips 2 via the wiring layer 10 and used in common. In FIG. 5, all the probing pads 4 are shared. However, it is naturally preferable in the test that some probing pads such as a chip select signal are provided independently for each chip.

  According to the third embodiment configured as described above, since the probing pad 4 formed in the scribe area SA is removed by etching, a large wide metal such as a probing pad is formed in the scribe area SA. In addition, it is possible to prevent a short circuit between the pads due to the metal remaining when the semiconductor wafer 1 is diced by the scribe line SL. Therefore, the third embodiment has the same operational effects as the first embodiment.

Fourth embodiment.
FIG. 6 is a plan view showing a configuration of a semiconductor wafer 1 including a plurality of NAND flash memory chips 2 according to the fourth embodiment. The semiconductor wafer 1 according to the third embodiment has two sides of the semiconductor memory chip 2 as compared to the first embodiment of FIG. 2 having a plurality of TSV pads 5 along one side of the semiconductor memory chip 2. Along with this, a plurality of TSV pads 5 are provided. Here, each of the two sides of the semiconductor memory chip 2 is opposed to a side where the TSV pad 5 of another semiconductor memory chip 2 adjacent thereto in the thickness direction is not formed. As a result, the scribe area SA between each pair of semiconductor memory chips 2 adjacent to each other in the thickness direction becomes the probing pad 4 for either one of the semiconductor memory chips 2 (the TSV pad 5 via the wiring layer 10). Can be formed effectively and efficiently. The plurality of probing pads 4 and a part of the wiring layer 10 connected thereto are removed together with the probing pads 4 by etching in the process of FIG. 3C.

  According to the fourth embodiment configured as described above, since the probing pad 4 formed in the scribe area SA is removed by etching, a large wide metal such as a probing pad is formed in the scribe area SA. In addition, it is possible to prevent a short circuit between the pads due to the metal remaining when the semiconductor wafer 1 is diced by the scribe line SL. Accordingly, the fourth embodiment has the same function and effect as the first embodiment.

Fifth embodiment.
7A to 7G are longitudinal sectional views showing respective steps showing a method for manufacturing the NAND flash memory chip 2 according to the fifth embodiment. 7A to 7G, the same symbols are assigned to the same components as those in FIGS. 3A to 3E. The NAND flash memory chip 2 according to the fifth embodiment is different from the above-described embodiment in the following points.
(1) After the TSV conductor 14 and the TSV pad 5 are formed first, a probing test is performed to remove the probing pad 4.
(2) The wiring layer including the probing pad 4 is not the uppermost layer (middle layer or lower layer).
(3) The metal layer including the probing pad 4 is different from the wiring layer 10 to which the TSV conductor 14 and the TSV pad 5 are connected.

  A method for manufacturing the NAND flash memory chip 2 according to the fifth embodiment will be described below with reference to FIGS. 7A to 7G.

  FIG. 7A shows a cross-sectional view corresponding to FIG. 3A and shows the end point of the normal process before opening the probing pad 4. In FIG. 7A, the wiring layer 10 and the wiring layer including the probing pad 4 are different layers and are connected by via conductors 23. In the example of FIG. 7A, the wiring layer 10 is an upper layer than the wiring layer including the probing pad 4.

  In FIG. 7B, after the thickness of the semiconductor wafer 1 is reduced by polishing, a through hole 13 from the back surface to the wiring layer 10 is formed, and a TSV conductor 14 is filled therein. Next, in FIG. 7C, the TSV pad 5 is formed immediately above the TSV conductor 14 and above the wiring layer 10. On the other hand, a TSV pad 6 is formed on the back side of the semiconductor wafer 1 and immediately below the TSV conductor 14. In FIG. 7D, an opening 16 is formed by anisotropically etching the scribe area SA in the horizontal direction and directly above the probing pad 4 by a predetermined width, and the probing pad 4 is used for probing. Do the test.

  Further, in FIG. 7E, the central portion of the probing pad 4 is further etched to form an opening 17 larger than the opening 16. At this time, a part of the probing pad 4 remains. Next, in FIG. 7F, a protective film 18 that is an insulating film including the inside of the opening 17 is formed on the upper surface of the semiconductor wafer 1. In FIG. 7G, the protective film 18 is etched back to expose the TSV pad 5. At this time, the surface 4 a of the portion where the part of the probing pad 4 remains is protected by the protective film 18. Then, the semiconductor wafer 1 is scribed along the scribe line SL to be separated into a plurality of semiconductor memory chips 2. A plurality of semiconductor memory chips 2 formed as described above can be stacked as in FIG. 3E.

  As described above, according to the present embodiment, by performing a probing test on the semiconductor wafer 1 after the TSV conductor 14 is formed, not only a defect in a normal process but also the TSV conductor 14 and the TSV pad 5, Defects associated with the formation of 6 can also be removed. For example, it is possible to screen for defective functions due to short circuits between the TSV pads 5 and 6 and the substrate or the occurrence of defects.

Modified example.
In the above embodiment, each of the NAND-type flash memory chips 2 formed on the semiconductor wafer 1 is cut by dicing to cut out each memory chip 2. The present invention is not limited to this, and the memory chip 2 may be a DRAM, another memory chip, or a semiconductor chip.

  3C and 7E, the probing pad 4 and a part of the wiring layer 10 connected thereto are removed by etching. However, the present invention is not limited to this, and the probing pad 4 and the wiring layer 10 connected thereto are used. Of these, at least one of them may be removed.

  Note that the test circuit 7 according to the second embodiment may be applied to the first embodiment and the third to fifth embodiments.

  As described above in detail, according to the present invention, after the wafer test, at least one of the plurality of probing pads and the wiring layer is removed by etching. Therefore, it is possible to solve the problem of deterioration of the reliability of the semiconductor chip based on the pad metal remaining when the semiconductor wafer is diced by the scribe line.

1 ... Semiconductor wafer,
2 ... Semiconductor memory chip,
3 ... Pad,
4 ... Probing pad,
5, 6, 5A ... TSV pad,
7 ... Test circuit,
10 ... wiring layer,
10a: exposed cross section of the wiring layer,
11, 12 ... Protective film,
13 ... Through hole,
14 ... TSV conductor,
15 ... spacer film,
16, 17 ... opening,
18 ... Protective film, 21 ... MOS memory transistor,
22, 23 ... via conductor,
SA ... Scribe area,
SL ... Scribe line.

Claims (6)

Forming a plurality of probing pads and a test circuit in a scribe region of a semiconductor wafer having a plurality of semiconductor chips;
Forming a plurality of wiring layers on the semiconductor chip;
Forming a plurality of through silicon vias connected to each wiring layer on a layer different from the wiring layer connected to each probing pad and the test circuit on the semiconductor chip;
After the wafer test, the a plurality of probing pads, the method for manufacturing a semiconductor wafer, which comprises and removing by etching a part of the wiring layer including the test circuit. 2. The method of manufacturing a semiconductor wafer according to claim 1 , wherein the wiring layers connected to the plurality of probing pads and the test circuit are not uppermost layers. After previously formed a plurality of through silicon via performs wafer testing, claim 1, wherein said plurality of probing pads, removing by etching a part of the wiring layer including the test circuit Or the manufacturing method of the semiconductor wafer of 2 . 4. The method according to claim 1, further comprising forming a protective film so as to cover an exposed surface of the wiring layer remaining when a part of the wiring layer is removed. The manufacturing method of the semiconductor wafer of description. In the manufacturing method of the semiconductor wafer as described in any one of Claims 1-4 ,
A method of manufacturing a semiconductor chip, further comprising separating a plurality of semiconductor chips by dicing along a predetermined scribe line in the scribe region. In the manufacturing method of the semiconductor chip according to claim 5 ,
A method for manufacturing a semiconductor device, further comprising: stacking the plurality of semiconductor chips so as to connect through silicon vias of semiconductor chips adjacent to each other in the thickness direction.

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