TWI329895B - Method for fabricating a semiconductor wafer - Google Patents

Description

IX. Description of the Invention: [Technical Field] The present invention relates to a wafer packaging process, and more particularly, to remove a test pad on a scribe line after a bump process to avoid a dicing process. The defects caused by the residue' affect the total effective number of crystal grains of a single wafer. [Prior Art] In order to test the electrical properties of each layer of wiring (laying), most of the fabs will design the test circuit (the test point _ heart) as the electrical test. The use of 'other' has a small portion of the test die. Generally speaking, the material of the test pad is mostly metal, such as aluminum. However, during the process of cutting the wafer, the metal on the test pad is easily coated with the diamond particles on the cutting tool, thereby reducing the digging ability of the cutting tool, so that the cutting is performed. The quality of the knife marks is unstable or extends other problems such as chipping and micro-cracking. In addition, the choice of cutting tool must be selected based on the width design of the wafer-related test points. Therefore, it is difficult to control the product development time. Moreover, it is necessary to adjust the cutting parameters and the optional tool multiple times to verify the cutting stability and the longer time required. W ^ In the general wafer packaging process, if the test pad is cut, the metal is splashed back to the die, and there is a risk of short or current leakage in the subsequent package process. In the process of cutting the wafer, metal residue and chipping are apt to occur, which may cause problems such as damage to the protective layer and electrical anomalies.

4CHIPBOND/06002TW b In order to avoid the metal layer in the process of crystal 81 cutting, the above-mentioned related 2' system must be proposed - a kind of solution, the problems that occur when the metal layer of the bribe cuts the wafer. Thin [Invention] In the above-mentioned background of the invention, the conventional wafer packaging process +, in the cutting =: many disadvantages produced by the present invention, therefore, the present invention proposes to cut the wafer crystal ": PCT removal in the cutting The metal layer of the test point on the track to avoid the defect caused by the metal layer when cutting the circle. The purpose of x Ming is to remove the metal layer before the wafer is cut, to avoid the occurrence of cracking, and to shrink the wafer (4) Crack safety value, _ small scribe line, increase the total effective number of grains of a single wafer (wafergrGssdie). According to the above, the present invention provides a method of killing after wafer encapsulation; A method for total number of effective crystal grains of a sheet of g, which comprises a crystal grain of a number of 22 crystals, wherein the grain between the grain and the grain can be defined as a dicing street and disposed on the dicing street - Most of the bumps are on the wafer, the test pads on the majority of the scribe lines are removed, the electrical properties of all the dies in the crystal, the dicing of the wafer to form a plurality of dies, and the difficulty of the process Borrowing the domain and doing the tricks on the circumcision Yield passage, and visibility can be reduced because the scribe 'when the material to _ Xiao small track width design, the total number of crystal grains effective circle. [Embodiment is the earlier

4CHJPBOND/06002TW, some embodiments of the present invention will be described in detail below. However, the present invention may be widely practiced in other embodiments, and the scope of the present invention is not limited, and the scope of the following patents will prevail. . For example, please refer to the first figure to show the flow of the wafer for manufacturing the invention. The first S' reference figure--, step 1G is a well-known wafer system, 'where there are many grains on the wafer, the area of each two grains can be, the meaning, the cutting path' It is possible to cut wafers according to the scribe line to form a plurality of single-grains. Correctively set up some tests on the _ road, these tests = to test the electrical properties of the layout on the wafer; step 12 is the bump fabrication, which is to form a plurality of bumps in each die In the above, the bumps can provide the contacts of the integrated components and the connectors, and the wipes can be made of a wrapable carrier such as TCP/COF, glass, lead frame flead fr_) or a general printed circuit. The board also provides electrical, mechanical, and signal transmission through these bumps, etc., so that the packaged wafer can be directly contacted with the component to achieve effective conduction. Then, step 14 is a butterfly side process, and the step 142 = the step M6 is a feature of the present invention, wherein the step 142 is that the photoresist has a bump and is not covered by the photoresist. The second surface is the portion of the butterfly track; the surface 144 is a method for indicating __, the test pad placed on the scribe line is completely removed; and the step 146 is for removing the photoresist. Next, step 16 is a crystal test, which is used to test the circuit layout and electrical properties of the die; step 18 is a wafer cutting process, and the step towel is a paste tool and is based on the wafer. The scribe line semiconductor die; and the step 20 ' indicates the back segment

4CHIPBOND/06002TW In addition, please refer to the second figure, which is also a flow chart showing the fabrication of the wafer disclosed in the present invention. First, step 30 is also a conventional wafer fabrication. Similarly, there are a plurality of crystal grains on the wafer, and are arranged in an array manner, and the distance between each two crystal grains can be defined as a butterfly track, and the purpose thereof can be generated according to the precise paste crystals of these cutting channels. Most of the grains. In addition, some of the residuals are set on the scribe line, and the test pads are used to test the electrical properties of the circuit layout of the wafer; the step % is made of bumps, as described above, a plurality of bumps are formed in each of the crystals. On the granule, the bumps can be used to provide a connection between the component and the connector, wherein the connector can be a flexible carrier such as a TCP/COF glass, a lead frame (iea), or a general printed circuit board. And through these bumps to provide electrical, mechanical and job transmission and correction unit connection, the package (9) and the meta-signal can directly depend on, to achieve an effective signal transmission, step 34 is also the same as the hair _, the cutting road The test 塾 on the scribe line is dry or wet _ _ _ f f s 36, is the wafer test; step 38 is the wafer dicing process is based on the dicing on the two circles to cut the wafer into a plurality of The grain is next; in step 40, the bottom step 50 is followed by the round step 50, and the money is referenced to the third figure, which is a mask of a plurality of crystal grains. The particles 52 are arranged in an array, so that the space between the two mother grains 52 Can be defined as scribe M. Next, the fourth A chill McCaw FIGS C to fourth respective image transmission (iv) Stripping Process butterfly recording track of the recording u

4CHIPB〇nd/〇6〇〇2TW 1329895 shows that there is a track % between the die 52 and the die 52, and the symbol W in the figure indicates the width of the single-die 52 on the wafer 4G, symbol L The force width of the scribe line 54 is shown, and the spacing 54 between the two dies 52 is the area where the test pad 56 is placed. These tests are used to test the electrical properties of the various layers of the circuit layout on the wafer. In general design, the test pads are shame, mostly made of metal. The commonly used materials are mainly aluminum and then mixed with other substances. In addition, in the mother die ... ... _ 叩 open, eve a number of bumps 522, these convex

Block 522 is formed by a bump process of a general package technique, by which the bumps 522 can provide a contact between the circuit component and the connector, and the towel connector 疋 flexible carrier such as TOVCOF, glass, lead frame _ For example, a piece 522 provides electrical, mechanical, and internal connection of the contact, so that the packaged wafer and the tree can be in direct contact, and an effective signal transmission is achieved. The fourth material is shown in Figure 4, in this embodiment, due to the test pad. %

= because of the easy diamond cutter head, so that the cutter = force judgment of the eclipse system, such as in the example before cutting the wafer 50, first perform step 14 of the first figure and step 34 of the second figure) Γ ^522 — - engrave, complete the shaft or _, refer to the fourth C diagram' to remove the removal process of the test pad 56 on the die 52 I =: pad = lower scribe 54. First (four) 0, and the yuan became

4CHJPBOND/06002TW

9 Referring to FIGS. 5A and 5, in another embodiment, on a wafer 50 having a plurality of dies 52, the selective side (10) is used to remove The test pad on the cutting track 54 is allowed. Here, the selective etching method has a high _ selectivity between the test pad 56 and the bump 522, that is, the side of the wafer 5 is used for this moment. The test crucible 56 on the dicing street 54 is removed without laterally to the bumps 522 located on the die 52. Thus, as shown in Figure 5b, after the residual acid is passed through, the test pad 56 on the scribe line 54 has been completely removed. Hey. Next, all of the dies 52 on the wafer 50 are tested and a dicing process 50 is performed to cut a wafer % according to the scribe line 54 to produce a plurality of dies 52. In this step, since the scale has been completely removed, it is possible to avoid the occurrence of cracking when cutting, and there is no metal residual, and there is a problem with the diamond knife that covers the butterfly cutter. 'So' reduces the leakage current or short circuit in the later stage of making money.

The invention can obtain the technology of the present invention, and the advantage is that the scribe line on the round is maintained—reducing the width to avoid the unevenness of the eight-knife marks when the wafer is diced, and the wafer is cracked. Therefore, the crack is broken into the grain, so the width of the scribe line designed in the crystal must be greater than the measured width plus a positive value of the queen (the two sides are the minimum, so that the shadow will be safe in the day. The value, therefore, has a smaller σ 'so that the total effective number of grains on a single wafer can be increased.

4CHIPBOND/06002TW 5 1329895 In addition, since the metal layer has been removed, it is easy to cut the tool and accelerate the time course of product development. [Simple description of the map]

The first diagram is a flow chart for fabricating a wafer according to the technology disclosed in the present invention; the second diagram is a flow chart for another example of fabricating a wafer according to the technology disclosed by the present invention; The disclosed technology is not intended to have a wafer of a plurality of dies; the fourth to fourth C diagrams are based on the technique disclosed in the present invention, and are removed in a light-engraving process in an embodiment. The steps of the job of the Tao are not intended, and

The selection of the fifth A ® to the fifth B is based on the technique disclosed in the present invention. In another embodiment, the steps of the test pads on the scribe line are selectively etched. ;-· φ*%

4CHIPBOND/06002TW

II 1329895 [Key component symbol description] 50 Wafer 52 Die 54 Cutting path 56 Test pad 60 Photoresist 522 Bump 4CHIPBOND/06002TW 12

Claims (1)

1329895 V. X. Patent Application Range: 1. A method for processing wafers, including: Bamboo Year?修修(更)正95145924月22曰修正-replacement page k for one of the wafers with a plurality of dies, wherein the dies are arranged in an array] so that the spacing between each of the two dies is a cutting track having a plurality of test pads thereon; forming a plurality of bumps on the plurality of dies; removing the test pads on the scribe lines; and After removing the test pads, the crystals are cut according to the scribe lines to form a plurality of single crystal grains. The method of the invention is as follows: wherein the test pad is a metal layer. Wherein the metal layer is aluminum or other 3. The method described in claim 2, applied to the material on the wafer. 4. The test pads of the method of claim 1, comprising an etching method. 'Removed on the scribe lines, wherein the surname includes the use of dry ‘ which is removed on the scribe lines. 5. The method or wet money engraving as described in claim 4 of the patent application. 6. The test pads of the method of claim 2, comprising: a photoresist to cover the plurality of crystal grains having the bumps; and removing the (four) test potential on the (four) tracks; And removing the photoresist. 4CHIPBOND/06002TVV 13 I3?9895 Case No.: 95945924 Modified on March 22, 1999. Replacement Page 7 • A method of forming a wafer, comprising: (a) providing a wafer having a plurality of dies, and The grain system is arranged in an array, and a distance between each of the two crystal grains is defined as a scribe line, and a plurality of test ridges are formed on the scribe lines, wherein the test 塾 is a metal layer; (b) After step (8), a plurality of bumps are formed on the plurality of dies; (c) after step (b), removing the test pads on the scribe lines; (9) after step (c), according to The dicing lines cut the wafer to obtain the single dies; and Λ (e) after the step (d), respectively packaging the dies. 8. The method of claim 7, wherein in the step, there is no metal on the channel. The method of claim 7, wherein the metal layer is a metal or a material applied to the wafer. Or 10. ===: the method described in which the 11 stem 1 (four) Wei branch on the cutting lane is removed, wherein the fiber system utilizes the method described in the seventh item of the patent scope, wherein the removal is performed at the same time. Some test pads utilize a dry or wet meal method. —上 4CHIPB〇ND/06002T\V 14 1329895 mt VII. Designated representative map: (1) The representative representative of the case is: Figure 5B. (2) A brief description of the symbol of the representative figure: 52 Grain 54 Cutting path 522 Bump 8 If there is a chemical formula in this case, the outline is most dependent on the chemical formula of the invention: None None 4CHIPBOND/06002TW