JP4443092B2 - Semiconductor device and manufacturing method - Google Patents

Semiconductor device and manufacturing method Download PDF

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Publication number
JP4443092B2
JP4443092B2 JP2002084016A JP2002084016A JP4443092B2 JP 4443092 B2 JP4443092 B2 JP 4443092B2 JP 2002084016 A JP2002084016 A JP 2002084016A JP 2002084016 A JP2002084016 A JP 2002084016A JP 4443092 B2 JP4443092 B2 JP 4443092B2
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Japan
Prior art keywords
mark
dicing
protective film
chip
polyimide film
Prior art date
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Expired - Fee Related
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JP2002084016A
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Japanese (ja)
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JP2003282484A (en
Inventor
隆雄 秋葉
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Seiko Instruments Inc
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Seiko Instruments Inc
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Description

【0001】
【発明の属する技術分野】
本発明は、半導体ウエハのICチップを分離するダイシング工程の製造方法に関する。
【0002】
【従来の技術】
半導体ウエハに複数形成されたICチップを分離するダイシング工程では、スクライブライン部分を切断して行う。但し、前記スクライブラインの中には、フォトリソ工程に必要なアライメントマーク、線幅、合わせずれ、エッチング状態などを測定する工程モニターマークなど、ウエハ表面に回路を形成する製造工程で必要な様々なマークが、設置されている。複数のマークが設置されている、すなわち単一の層で形成されていない、スクライブラインにて(ダイシング)ブレードを当てて、切断する。そして、それぞれのICチップに分離している。これは、いわゆる研削加工により行われるものである。
【0003】
【発明が解決しようとする課題】
このように、従来の半導体装置のICチップを分離するダイシング工程では、複数のICは、複数マークが設置されているスクライブラインにてブレードを使って研削/切断される。すなはちマークも同時に切断される事になる。そして複数のICを分離するウエハ切断後、それぞれのマークの大半部分は研削/切断によって削除される。また、研削されないスクラブラインには、マークの一部が残ることになる。そして、ダイシング後はマークの下地とマーク残留部分の密着面積が小さくなるため、密着力が低下した状態になる。そのためダイシング時にかかる外部応力、例えば切削水の圧力などによって密着力が低下したマークが剥がれたり、捲れあがったりしてしまい、その後の実装工程で不良を引き起こす問題があった。また実装工程で問題がでなくとも、ICチップ表面に異物があるため信頼性上の弊害をもたらすことがあつた。
【0004】
【課題を解決するための手段】
本発明は上記課題を解決するため、マークを形成する各層膜とIC側のマークで使用している同一層膜を分離しないパターン構造を用いたマークを設置する。
【0005】
更に、ICを分離するダイシング工程において、ダイシング後のスクライブラインに設置しているマーク幅の残りが10μm以上残る様に、ダイシングブレードの幅を選択してダイシングを行う。
【0006】
以上のようにダイシング後にマークの設置面積を確保することにより、ダイシング時に必要とする洗浄水の圧力等でマークが捲れたり、剥がれたりする事がなくなり、その後の実装工程に及ぼす不良因子を無くす事ができた。
【0007】
【発明の実施の形態】
以下に、この本発明の実施の形態について詳細に説明する。図1(a)、(b)は本発明の第一の実施例における半導体装置の上面図と断面図である。
【0008】
1は、例えばSiからなる半導体基板(ウエハ基板)である。2は、スクライブラインである。スクラブライン2にダイシングソーの歯を当て、ウエハを切断するものである。5は、スクライブライン上に設置されたウエハ状で半導体装置を製造する工程に必要なマークである。3は、半導体基板1上に形成される例えば窒化膜からなる保護膜である。4は、保護膜3上に形成されるポリイミド膜である。
【0009】
6は、マーク5とICチップのスリット部に形成されている保護膜である。7は、マーク5とICチップのスリット部に形成されているポリイミド膜である。8は、ICチップとマーク5のスリット部である。スクライブライン2を設計する場合ウエハ製造工程でモニター等に使用するマーク5を設置する。この時マーク5を形成している上部の層、本実施例では保護膜3とポリイミド膜4をICチップ側と分離せずにスリット部8の保護膜6とスリット部8のポリイミド膜7も形成される様にパターン設計を行う。
【0010】
以上のように構成されたスクライブライン2をダイシング工程でICチップを分離すると、マーク5の半導体基板1との設置面積はスリット部8にポリイミド4、保護膜3が形成されているため大きくなっており、ダイシング時にかかる洗浄水などの応力によって、切断後のマーク5が捲れたり、剥がれたりしなくなる。
【0011】
図2は本発明の第二の実施例における半導体装置の断面図である。マーク5を2種類以上の膜で形成する場合、マーク5とICチップのスリット部8をマーク5を形成する全層で埋めるのでなく、最上層の膜、本実施例ではポリイミド膜4のみでスリット部ポリイミド膜7を形成する。以上のように構成されたスクライブライン2をダイシングし、ICチップを分離した場合でも最上層のポリイミド膜4がマーク5の下層を押さえつけているため、切断後のマーク5が捲れたり、剥がれたりしなくなる。
【0012】
図3(A)、(B)は本発明の第三の実施例における半導体装置の上面図と断面図である。9はマーク5のマーク幅で記号Wで表す、10はダイシング後のスクライブに残ったマーク幅で記号Δwで表す、11はカーフ幅で記号Dで表す。ダイシング後にスクライブラインに残るダイシング後マーク幅10が10μm以上残るように、ダイシングに使用するブレードの幅すなはち、カーフ幅11とマーク幅9を決めて、スクライブライン2にマーク5を設置する。マーク幅9、ダイシング後マーク幅10とカーフ幅11の関係は次の様になる。
【0013】
10μm≧Δw
Δw=W/2-D
例えばカーフ幅Dが25μmになるブレードを使う場合、10μm以上のダイシング後マーク幅10が必要のため、マーク幅は上記式より45μm以上のマーク幅9のマーク5をスクライブライン2に設置する。以上の様に構成されたマーク5はやはり設置面積が剥がれない
【0014】
【発明の効果】
以上、詳細に説明したように、本発明によれば、次のような効果がある。スクライブラインに設置したマークをダイシングによって切断しても、保護膜やポリイミド膜など上層面の膜を分離しない事、もしくは分離した場合でも十分な接触面積を確保できるサイズのマーク幅を持たす事によって、切断後に外部からの応力でマークが捲れたり、剥がれたりする事がない。そのためICチップを分離した後パッケージ等の実装時に剥がれた物がパッドにつく事がなく、実装不良の発生を低減する効果がある。以上のように本発明はダイシング工程において不良発生率を低減する効果がある。
【図面の簡単な説明】
【図1】本発明の実施例における半導体装置の上面図と断面図である。
【図2】本発明の実施例における半導体装置の断面図である。
【図3】本発明の実施例における半導体装置の上面図と断面図である。
【符号の説明】
1 半導体基板
2 スクライブライン
3 保護膜
4 ポリイミド膜
5 マーク
6 スリット部保護膜
7 スリット部ポリイミド膜
8 スリット部
9 マーク幅
10 ダイシング後マーク幅
11 カーフ幅
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a manufacturing method of a dicing process for separating an IC chip of a semiconductor wafer.
[0002]
[Prior art]
In the dicing process of separating a plurality of IC chips formed on the semiconductor wafer, the scribe line portion is cut. However, in the scribe line, various marks necessary for the manufacturing process for forming a circuit on the wafer surface, such as an alignment mark necessary for the photolithography process, a process monitor mark for measuring the line width, misalignment, etching state, etc. Is installed. Cut by applying a (dicing) blade on a scribe line where a plurality of marks are installed, i.e. not formed in a single layer. It is separated into each IC chip. This is performed by so-called grinding.
[0003]
[Problems to be solved by the invention]
As described above, in the dicing process for separating the IC chips of the conventional semiconductor device, the plurality of ICs are ground / cut using a blade on a scribe line in which a plurality of marks are installed. The Sunahachi mark will be cut at the same time. After the wafer cutting for separating the plurality of ICs, most of the marks are deleted by grinding / cutting. Further, a part of the mark remains on the scrub line that is not ground. Then, after dicing, the contact area between the mark base and the mark remaining portion is reduced, and the contact force is reduced. For this reason, there is a problem that a mark whose adhesion is lowered due to an external stress applied during dicing, for example, a pressure of cutting water, is peeled off or curled up and causes a defect in the subsequent mounting process. Even if there is no problem in the mounting process, there is a problem in reliability due to the presence of foreign matter on the surface of the IC chip.
[0004]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present invention is provided with a mark using a pattern structure that does not separate each layer film forming the mark and the same layer film used in the IC side mark.
[0005]
Further, in the dicing process for separating the IC, dicing is performed by selecting the width of the dicing blade so that the remainder of the mark width set on the scribe line after dicing remains 10 μm or more.
[0006]
By securing the mark installation area after dicing as described above, the mark will not be swollen or peeled off due to the pressure of the cleaning water required for dicing, etc., and there will be no defective factors affecting the subsequent mounting process. I was able to.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail. 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
[0008]
Reference numeral 1 denotes a semiconductor substrate (wafer substrate) made of, for example, Si. 2 is a scribe line. Dicing saw teeth are applied to the scrub line 2 to cut the wafer. Reference numeral 5 denotes a mark necessary for a process of manufacturing a semiconductor device in the form of a wafer placed on a scribe line. Reference numeral 3 denotes a protective film made of, for example, a nitride film formed on the semiconductor substrate 1. Reference numeral 4 denotes a polyimide film formed on the protective film 3.
[0009]
Reference numeral 6 denotes a protective film formed on the mark 5 and the slit portion of the IC chip. 7 is a polyimide film formed on the mark 5 and the slit portion of the IC chip. Reference numeral 8 denotes a slit portion between the IC chip and the mark 5. When designing the scribe line 2, a mark 5 used for a monitor or the like in the wafer manufacturing process is installed. At this time, the upper layer forming the mark 5, in this embodiment, the protective film 3 and the polyimide film 4 are not separated from the IC chip side, and the protective film 6 of the slit portion 8 and the polyimide film 7 of the slit portion 8 are also formed. Design the pattern as expected.
[0010]
When the IC chip is separated from the scribe line 2 configured as described above in the dicing process, the installation area of the mark 5 with the semiconductor substrate 1 becomes large because the polyimide 4 and the protective film 3 are formed in the slit portion 8. Therefore, the marks 5 after cutting are not frayed or peeled off due to stress such as washing water applied during dicing.
[0011]
FIG. 2 is a sectional view of a semiconductor device according to the second embodiment of the present invention. When forming the mark 5 with two or more types of films, the mark 5 and the slit portion 8 of the IC chip are not filled with all the layers forming the mark 5, but are slit only with the uppermost film, which is the polyimide film 4 in this embodiment. A partial polyimide film 7 is formed. Even when the scribe line 2 configured as described above is diced and the IC chip is separated, the uppermost polyimide film 4 presses the lower layer of the mark 5, so that the mark 5 after cutting may be broken or peeled off. Disappear.
[0012]
3A and 3B are a top view and a cross-sectional view of a semiconductor device according to the third embodiment of the present invention. 9 is the mark width of the mark 5 and is represented by the symbol W, 10 is the mark width remaining in the scribe after dicing, is represented by the symbol Δw, and 11 is the kerf width and is represented by the symbol D. The width of the blade used for dicing, that is, the kerf width 11 and the mark width 9 is determined so that the mark width 10 after dicing remaining on the scribe line after dicing is 10 μm or more, and the mark 5 is set on the scribe line 2. The relationship between the mark width 9, the post-dicing mark width 10 and the kerf width 11 is as follows.
[0013]
10μm ≧ Δw
Δw = W / 2-D
For example, when a blade having a kerf width D of 25 μm is used, a mark width 10 after dicing of 10 μm or more is required. Therefore, a mark 5 having a mark width 9 of 45 μm or more is set on the scribe line 2 from the above formula. The mark 5 configured as above does not peel off the installation area.
【The invention's effect】
As described above in detail, the present invention has the following effects. Even if the mark placed on the scribe line is cut by dicing, the film on the upper layer such as the protective film or polyimide film is not separated, or by having a mark width of a size that can secure a sufficient contact area even when separated, After cutting, the marks will not be damaged or peeled off by external stress. Therefore, after the IC chip is separated, an object peeled off during mounting such as a package does not stick to the pad, and there is an effect of reducing the occurrence of mounting defects. As described above, the present invention has an effect of reducing the defect occurrence rate in the dicing process.
[Brief description of the drawings]
1A and 1B are a top view and a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a semiconductor device in an embodiment of the present invention.
FIGS. 3A and 3B are a top view and a cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIGS.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Scribe line 3 Protective film 4 Polyimide film 5 Mark 6 Slit part protective film 7 Slit part polyimide film 8 Slit part 9 Mark width 10 Dicing mark width 11 Calf width

Claims (2)

保護膜とポリイミド膜との二層からなる、ICチップ間のスクライブライン上に配置された、ウェハ製造工程でモニター等に使用するマークであって、前記マークを構成する前記保護膜と前記ポリイミド膜とは同じ形状を有するとともに、前記保護膜と前記ポリイミド膜の両端前記ICチップ上に配置された保護膜とポリイミド膜とそれぞれ分離されずに繋がっている部分を有するマークを具備する半導体装置。 Consisting of two layers of the protective film and the polyimide film was placed on the scribe lines between IC chip, a mark used to monitor or the like in the wafer fabrication process, the polyimide film and the protective film of the mark which has the same shape as the semiconductor device in which both ends of the protective film and the polyimide film comprises a mark having a portion which is connected without being separated from each protective film and the polyimide film disposed on the IC chip . 保護膜とポリイミド膜との二層からなる、ICチップ間のスクライブライン上に配置された、ウェハ製造工程でモニター等に使用するマークであって、前記マークを構成する前記保護膜と前記ポリイミド膜とは同じ形状を有するとともに、前記保護膜と前記ポリイミド膜の両端前記ICチップ上に配置された保護膜とポリイミド膜とそれぞれ分離されずに繋がっている部分を有するマークを具備する半導体ウェハを前記スクライブラインでダイシングする半導体装置の製造方法。 Consisting of two layers of the protective film and the polyimide film was placed on the scribe lines between IC chip, a mark used to monitor or the like in the wafer fabrication process, the polyimide film and the protective film of the mark which has the same shape as the semiconductor wafer in which both ends of the protective film and the polyimide film comprises a mark having a portion which is connected without being separated from each protective film and the polyimide film disposed on the IC chip For manufacturing a semiconductor device.
JP2002084016A 2002-03-25 2002-03-25 Semiconductor device and manufacturing method Expired - Fee Related JP4443092B2 (en)

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