JPH03129855A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH03129855A JPH03129855A JP1268483A JP26848389A JPH03129855A JP H03129855 A JPH03129855 A JP H03129855A JP 1268483 A JP1268483 A JP 1268483A JP 26848389 A JP26848389 A JP 26848389A JP H03129855 A JPH03129855 A JP H03129855A
- Authority
- JP
- Japan
- Prior art keywords
- scribe
- area
- region
- protective film
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000001681 protective effect Effects 0.000 claims description 24
- 229920001721 polyimide Polymers 0.000 claims description 12
- 239000009719 polyimide resin Substances 0.000 claims description 11
- 238000012544 monitoring process Methods 0.000 claims description 4
- 238000009795 derivation Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 3
- 102100027340 Slit homolog 2 protein Human genes 0.000 abstract 1
- 101710133576 Slit homolog 2 protein Proteins 0.000 abstract 1
- 238000002161 passivation Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 239000000498 cooling water Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明はダイシングによる表面保護膜の損傷を防ぎつつ
工程を簡略化できる半導体装置とその製造方法に関する
。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor device and a manufacturing method thereof that can simplify the process while preventing damage to a surface protective film caused by dicing.
（ロ）従来の技術
ＭＯＳ−ＬＳＩ等の半導体装置は、外部環境（水分、イ
オン等）から素子を保護するためにＰＳＧ膜やＳｉＮ膜
で表面を覆う（パッシベーション）必要がある。また、
素子に加わるストレスが少ないことから、ファイナル（
最終）パッシベーションとしてポリイミド系樹脂を用い
る技術が多用されている（例えば、特開昭６１−１５０
２３８号公報）。(B) Conventional Technology Semiconductor devices such as MOS-LSI require covering (passivation) the surface with a PSG film or SiN film in order to protect the device from the external environment (moisture, ions, etc.). Also,
Final (
(Final) Technology using polyimide resin as passivation is often used (for example, JP-A-61-150
Publication No. 238).
しかしながら、ポリイミド系樹脂はその他の材料との密
着性に劣るので、ウェハーからチップを切出すダイシン
グ工程において、ダイシングブレードでポリイミド系樹
脂が引張られ剥がれてしまう難点がある。そのためダイ
シング領域上にポリイミド系樹脂を残すことは出来なか
った。However, since polyimide resin has poor adhesion to other materials, there is a problem in that the polyimide resin is pulled and peeled off by a dicing blade during the dicing process for cutting chips from a wafer. Therefore, it was not possible to leave the polyimide resin on the dicing area.
一方、ウェハーのスクライブライン上にはウェハー面積
の効率利用という点で素子モニタ用のテストパターンが
設けられることが多く、チップ内素子と同一の電気特性
が得られるようスクライブライン上にもパッシベーショ
ンが必要となる他、テストパターン用電極パッド上の開
孔も必要となる。On the other hand, test patterns for device monitoring are often provided on the wafer's scribe line in order to efficiently utilize the wafer area, and passivation is also required on the scribe line to obtain the same electrical characteristics as the elements on the chip. In addition, openings on the test pattern electrode pads are also required.
そこで従来は、先ず第２図Ａに示す如＜ ＳｉＮ膜等の
パッシベーション被膜（１）上に第１のホトレジスト層
（２）を形成し、
第３図Ｂに示す如くスクライブ領域上のテストパターン
用電極パッド（３）上を開孔し、第３図Ｃに示す如くポ
リイミド系樹脂から成る表面保護膜（４）を形成し、さ
らに表面保護膜（４）上に第２のホトレジスト層（５）
を形成し、第３図りに示す如くスクライブ領域上の表面
保護膜（４）を除去することにより、スクライブ領域上
にパッシベーション被膜（１）を残し且つポリイミド系
樹脂は除去して、ダイシングによる表面保護膜（４）の
剥離損傷を防止していた。尚、（６）は基板、（７〉は
フィールド酸化膜である。Conventionally, a first photoresist layer (2) is first formed on a passivation film (1) such as a SiN film as shown in FIG. A hole is formed on the electrode pad (3), a surface protection film (4) made of polyimide resin is formed as shown in FIG. 3C, and a second photoresist layer (5) is formed on the surface protection film (4).
As shown in the third diagram, the surface protection film (4) on the scribe area is removed to leave the passivation film (1) on the scribe area and the polyimide resin is removed, and the surface is protected by dicing. Peeling damage to the film (4) was prevented. Note that (6) is a substrate, and (7> is a field oxide film).
（ハ）発明が解決しようとする課題
しかしながら、上記従来技術はパッシベーション被膜（
１）の開孔と表面保護膜（４）の開孔とで２回のホトレ
ジスト工程を用いるので、工程が煩雑になる欠点があっ
た。(c) Problems to be Solved by the Invention However, the above-mentioned prior art does not require a passivation film (
Since two photoresist processes are used for forming the holes in 1) and for forming the surface protective film (4), there is a drawback that the process becomes complicated.
（＝）課題を解決するための手段
本発明は上記従来の欠点に鑑みて成され、基板（１１）
上に表面保護膜（１３）を被覆する工程と、表面保護膜
（１３）をエツチングして電極パッド（１４）の表面を
開孔すると共に、チップ領域を覆う表面保護膜（１３ａ
）とスクライプ領域を覆う表面保護膜（１３ｂ＞とを完
全に分断するスリット（２０）を形成する工程と、スク
ライブライン（２１）に沿ってダイシングを行う工程と
を具備することを特徴とする（ネ）作用
本発明によれば、スリット（２０）を設けることでポリ
イミド系表面保護膜（１３）が完全に分断されているの
で、ダイシング工程においてチップ領域を覆う表面保護
膜（１３ａ）が引張られることが無く、従って表面保護
膜（１３ｇ）の剥離損傷も防止できる。また、電極パッ
ド（１４）上を開孔するエッチング工程で同時的にスリ
ット（２０）を形成することができるので、ホトエツチ
ングは１回で済み工程を簡略化できる。(=) Means for Solving the Problems The present invention has been made in view of the above-mentioned conventional drawbacks.
A step of coating the surface protective film (13) on the top, etching the surface protective film (13) to open the surface of the electrode pad (14), and forming a surface protective film (13a) covering the chip area.
) and the surface protection film (13b>) covering the scribe area, and a process of dicing along the scribe line (21). f) Function According to the present invention, the polyimide surface protective film (13) is completely separated by providing the slits (20), so that the surface protective film (13a) covering the chip area is stretched during the dicing process. Therefore, peeling damage to the surface protective film (13g) can be prevented.Furthermore, the slit (20) can be formed at the same time as the etching process for opening the hole on the electrode pad (14), so photo-etching is not necessary. It only needs to be done once, which simplifies the process.
（へ）実施例
以下に本発明の一実施例を図面を参照しながら詳細に説
明する。(F) Example An example of the present invention will be described below in detail with reference to the drawings.
第１図は本発明の製造方法を工程順に示す断面図である
。先ず第１図Ａに示す通り、素子形成が終了したＰ型又
はＮ型シリコン半導体基板（１１）の全面に膜厚０．５
〜１．０μのシリコン窒化膜（ＳｉＮ）から成るパッシ
ベーション被膜（１２）をプラズマＣＶＤ法により堆積
し、続いてその上に膜厚１゜０〜３．０μのポリイミド
系樹脂から成る表面保護膜（１３）を、スピンオン塗布
法により形成する。FIG. 1 is a sectional view showing the manufacturing method of the present invention in order of steps. First, as shown in FIG. 1A, a film with a thickness of 0.5 cm is applied to the entire surface of a P-type or N-type silicon semiconductor substrate (11) on which element formation has been completed.
A passivation film (12) made of silicon nitride (SiN) with a thickness of ~1.0μ is deposited by plasma CVD, and then a surface protection film (12) made of polyimide resin with a film thickness of 1°0~3.0μ is deposited thereon. 13) is formed by a spin-on coating method.
基板（１１）はまだ半導体ウェハーの状態であり、その
表面には半導体チップとなるべき領域が多数個縦横に同
一パターンで描画きれ、個々のパターンの間は網状に延
在するウェハーを分割するためのスクライブ領域によっ
て分離されている。前記チップ領域にはＭＯＳ型等の半
導体素子が多数個形成されており、それらはポリシリコ
ン層、Ａｊ！−Ｓｉ層、Ａ１層等の電極層で結線され所
定の回路機能を達成する。前記スクライブ領域には前記
チップ領域内の素子の加工形状（線幅、材料残り等）や
電気的特性（断線、コンタクト抵抗等）をモニタするた
めのチエツクパターンが前記素子形成と同時に形成され
ている。また、前記チップ領域には素子と外部との電気
接続をとるための電極パッドが形成きれ、前記スクライ
ブ領域上にも前記チエツクパターンを測定する時の電気
的導出のために電極パッド（１４）が配設されている。The substrate (11) is still in the state of a semiconductor wafer, and on its surface, many regions that will become semiconductor chips can be drawn in the same pattern vertically and horizontally. are separated by a scribe area. A large number of semiconductor elements such as MOS type semiconductor elements are formed in the chip area, and they are formed by a polysilicon layer, Aj! - Connected through electrode layers such as the Si layer and the A1 layer to achieve a predetermined circuit function. A check pattern is formed in the scribe area at the same time as the element is formed to monitor the processed shape (line width, remaining material, etc.) and electrical characteristics (wire breakage, contact resistance, etc.) of the element in the chip area. . Further, electrode pads are formed in the chip area for electrically connecting the element to the outside, and electrode pads (14) are also formed on the scribe area for electrical conduction when measuring the check pattern. It is arranged.
（１５）は基板（１１）表面に設けたフィールド絶縁膜
（ＳｉＯｔ）である。(15) is a field insulating film (SiOt) provided on the surface of the substrate (11).
次に第１図Ｂに示す通り、表面保護膜（１３）上に例え
ばＡＺ１３５０等のポジ型レジスト（１６）をスピンオ
ン塗布し、これを露光、現像することでスクライブ領域
の電極パッド（１４）上の開孔（１７）と、スクライブ
領□域とチップ領域との境界線上の開孔（１８）を形成
する。もちろん、チップ領域内の電極パッド上にも図示
せぬ開孔を形成する。Next, as shown in FIG. 1B, a positive resist (16) such as AZ1350 is spin-on coated on the surface protection film (13), exposed and developed to form a pattern on the electrode pad (14) in the scribe area. An opening (17) and an opening (18) on the boundary line between the scribe area and the chip area are formed. Of course, openings (not shown) are also formed on the electrode pads in the chip area.
次に第１図Ｃに示す通り、ホトレジスト層（１６）をマ
スクとして表面保護膜（１３）をＯｔ雰囲気中のプラズ
マエッチによって異方性エツチングを行い、続いてパッ
シベーション被［（１２）をＣＦａ＋Ｏｔ雰［気中のプ
ラズマエツチングを行うことにより、電極パッド（１４
）上の開孔（１９）、および境界線上のスリット（２０
）を形成する。結果、表面保護膜（１３）はチップ領域
表面を覆う部分（１３ａ）とスクライブ領域表面を覆う
部分（１３ｂ）とに分断される。Next, as shown in FIG. 1C, using the photoresist layer (16) as a mask, the surface protective film (13) is anisotropically etched by plasma etching in an Ot atmosphere, and then the passivated film (12) is etched in a CFa+Ot atmosphere. [By performing plasma etching in the air, the electrode pads (14
) and the slit (20) on the border line.
) to form. As a result, the surface protection film (13) is divided into a portion (13a) covering the surface of the chip region and a portion (13b) covering the surface of the scribe region.
尚、ポジ型レジスト層（１６）の現像液として例えばＮ
ＭＤ３（東京応化）を用いることにより、この現像液は
表面保護膜（１３）のポリイミド系樹脂をエツチングす
ることが可能なので、ホトレジスト層（１６）の現像工
程で同時に表面保護膜（１３）を開孔することができ、
工程を簡素化できる。In addition, as a developer for the positive resist layer (16), for example, N
By using MD3 (Tokyo Ohka), this developer can etch the polyimide resin of the surface protective film (13), so the surface protective film (13) is opened at the same time as the photoresist layer (16) is developed. Can be holed,
The process can be simplified.
こうしてスリット（２０）を設けたウェハーの拡大平面
図を第２図に示す。（２１）は、ダイシング工程におい
てダイシングブレードが実際に切込みを行う領域を示す
スクライブライン、（２２）はチップ領域内の電極パッ
ド、（２３）はその上に設けられた開孔である。スリッ
ト（２０）はスクライブライン（２１）の両側に沿って
、スクライブ領域表面のチエツクパターンが存在しない
領域にチップ領域を囲むように延在°する。スクライブ
領域を覆う表面保護膜（１３ｂ）は、電極パッド（１４
）上の開孔（１９）を除いて、前記チエツクパターンの
表面を覆いこれをパッシベーションする。また、スクラ
イブ領域上の表面保護膜（１３ｂ）には、前記チエツク
パターンが存在しない部分に適宜第２のスリット（２４
）を複数個、前記スリット（２０）の形成と同時に形成
する。An enlarged plan view of the wafer provided with slits (20) in this manner is shown in FIG. (21) is a scribe line indicating the area where the dicing blade actually cuts in the dicing process, (22) is an electrode pad in the chip area, and (23) is an opening provided thereon. The slits (20) extend along both sides of the scribe line (21) so as to surround the chip area in an area where no check pattern exists on the surface of the scribe area. The surface protection film (13b) covering the scribe area covers the electrode pad (14).
) The surface of the check pattern is covered and passivated, except for the apertures (19) above. Further, in the surface protection film (13b) on the scribe area, second slits (24
) are formed simultaneously with the formation of the slits (20).
上記工程を経たウェハーは、最後にダイシング工程へと
移行する。ダイシング工程では、先ずウェハーの裏面側
にフィルムを貼付け、続いてダイシングブレードが前記
スクライブライン（２１）に沿って基板（１１）をハー
フカット又はフルカットすることにより、チップ領域を
個々の半導体チップに分割する。この時、スクライブラ
イン（２１）上の表面保護膜（１３ｂ）が除去されるこ
とはもちろんのこと、接着面積が少ないことから、ダイ
シング領城下のダイシングブレードに当接しない部分の
表面保護膜（１３ｂ）も前記ブレードに引張られて簡単
に剥がされる。剥がされたポリイミド系樹脂材料は、ダ
イシング装置の洗浄水および冷却水によってウェハー上
から除去される。また、前記第２のスリット（２４）を
設けることにより、接着面積を更に小さくして剥がれ易
さを助長する他、剥がされた材料が更に細分化されるの
で、ウェハー上からの除去を助ける。The wafer that has undergone the above steps is finally subjected to a dicing step. In the dicing process, a film is first attached to the back side of the wafer, and then a dicing blade half-cuts or fully cuts the substrate (11) along the scribe lines (21), thereby converting the chip area into individual semiconductor chips. To divide. At this time, not only the surface protective film (13b) on the scribe line (21) is removed, but also the surface protective film (13b) on the part that does not contact the dicing blade under the dicing area because the adhesive area is small. ) is also pulled by the blade and easily peeled off. The peeled polyimide resin material is removed from the wafer by cleaning water and cooling water of the dicing device. In addition, by providing the second slit (24), the bonding area is further reduced to facilitate peeling, and the peeled material is further divided into smaller pieces, which aids in removal from the wafer.
一方、チップ領域表面を覆う表面保護膜（１３ａ）は、
ダイシング領域上のもの（１３ｂ）とはスリット（２０
）によって完全に分断きれているので、前記ダイシング
ブレードの回転に伴う機械的応力が及ぶはずもなく、従
って剥がれ損傷は完全に防止できる。On the other hand, the surface protection film (13a) covering the chip area surface is
The one on the dicing area (13b) is the slit (20
), there is no need for mechanical stress due to the rotation of the dicing blade, and therefore, peeling damage can be completely prevented.
（ト〉発明の効果
以上に説明した通り、本発明はチップ領域とダイシング
領域とをスリット（２０）で分断することにより、表面
保護膜（１３）の剥がれ損傷を防止できる利点を有する
。一方、ダイシング領域のチエツクパターン上には、チ
ップ内素子と同一構造の保護膜を残せるので、素子特性
を正確にモニタできる利点を有する。さらに、ホトレジ
スト工程が１回で済むので、工程を簡略化できる利点を
も有する。(G) Effects of the Invention As explained above, the present invention has the advantage that peeling and damage to the surface protective film (13) can be prevented by separating the chip area and the dicing area with the slit (20).On the other hand, A protective film with the same structure as the internal chip elements can be left on the check pattern in the dicing area, which has the advantage of allowing accurate monitoring of element characteristics.Furthermore, the photoresist process can be performed only once, simplifying the process. It also has
第１図Ａ乃至第１図Ｃは本発明の製造方法を説明するた
めの断面図、第２図は本発明を説明するための平面図、
第３図Ａ乃至第３図りは従来例を説明するための断面図
である。1A to 1C are cross-sectional views for explaining the manufacturing method of the present invention, and FIG. 2 is a plan view for explaining the present invention.
FIGS. 3A to 3D are cross-sectional views for explaining a conventional example.
Claims (6)
と前記半導体基板を個々の半導体チップに分割するため
のスクライブ領域とを有し、 前記半導体基板上に表面保護膜を形成する工程と、 前記スクライブ領域上の表面保護膜の一部を選択的に除
去すると共に、前記スクライブ領域と前記チップ領域と
の間に、前記チップ領域を覆う表面保護膜と前記スクラ
イブ領域上に残る表面保護膜とを分断するスリットを形
成する工程と、前記スクライブ領域に沿ってダイシング
を行い、前記半導体基板を個々の半導体チップに分割す
る工程とを具備することを特徴とする半導体装置の製造
方法。(1) having a chip region for forming elements on a semiconductor substrate and a scribe region for dividing the semiconductor substrate into individual semiconductor chips, and forming a surface protection film on the semiconductor substrate; A part of the surface protection film on the scribe area is selectively removed, and a surface protection film covering the chip area and a surface protection film remaining on the scribe area are provided between the scribe area and the chip area. A method for manufacturing a semiconductor device, comprising: forming a slit to divide the semiconductor substrate; and performing dicing along the scribe region to divide the semiconductor substrate into individual semiconductor chips.
特徴とする請求項第１項に記載の半導体装置の製造方法
。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the surface protective film is made of polyimide resin.
と前記半導体基板を個々の半導体チップに分割するため
のスクライブ領域とを有し、 前記スクライブ領域表面に素子をモニタするためのテス
トパターンおよびテストパターンの電気的導出のための
電極パッドを形成する工程と、前記半導体基板上に表面
保護膜を形成する工程と、 前記スクライブ領域の電極パッド上の表面保護膜を除去
すると共に、前記スクライブ領域と前記チップ領域との
間に、前記チップ領域を覆う表面保護膜と前記スクライ
ブ領域上に残る表面保護膜とを分断するスリットを形成
する工程と、 前記スクライブ領域に沿ってダイシングを行い、前記半
導体基板を個々の半導体チップに分割する工程とを具備
することを特徴とする半導体装置の製造方法。(3) having a chip area for forming elements on a semiconductor substrate and a scribe area for dividing the semiconductor substrate into individual semiconductor chips; a test pattern for monitoring the element on the surface of the scribe area; and forming an electrode pad for electrical derivation of a test pattern; forming a surface protective film on the semiconductor substrate; removing the surface protective film on the electrode pad in the scribe area; and the chip region, forming a slit that separates a surface protective film covering the chip region and a surface protective film remaining on the scribe region, and dicing along the scribe region to remove the semiconductor. 1. A method for manufacturing a semiconductor device, comprising the step of dividing a substrate into individual semiconductor chips.
特徴とする請求項第３項に記載の半導体装置の製造方法
。(4) The method for manufacturing a semiconductor device according to claim 3, wherein the surface protective film is made of polyimide resin.
を更に細分化する第２のスリットを設けたことを特徴と
する請求項第３項に記載の半導体装置の製造方法。(5) The method for manufacturing a semiconductor device according to claim 3, characterized in that the surface protection film remaining on the scribe region is provided with second slits to further subdivide the surface protection film.
と、 前記スクライブ領域に形成された素子モニタ用のテスト
パターンおよびテストパターンを電気的に接続するため
の電極パッドと、 前記チップ領域の表面を覆う表面保護膜と、前記スクラ
イブ領域の表面を少なくとも前記電極パッド上を除いて
覆う表面保護膜と、 前記チップ領域上の表面保護膜と前記スクライブ領域上
の表面保護膜とを分断するスリットとを具備することを
特徴とする半導体装置。(6) A large number of chip areas for forming elements, a scribe area for dividing the chip area into individual parts, and a test pattern for monitoring the element formed in the scribe area and a test pattern electrically connected to each other. an electrode pad for connection; a surface protective film that covers the surface of the chip region; a surface protective film that covers the surface of the scribe region except at least over the electrode pad; a surface protective film on the chip region; A semiconductor device comprising a slit separating a surface protection film on a scribe region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26848389A JP2777426B2 (en) | 1989-10-16 | 1989-10-16 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26848389A JP2777426B2 (en) | 1989-10-16 | 1989-10-16 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03129855A true JPH03129855A (en) | 1991-06-03 |
| JP2777426B2 JP2777426B2 (en) | 1998-07-16 |
Family
ID=17459123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26848389A Expired - Lifetime JP2777426B2 (en) | 1989-10-16 | 1989-10-16 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2777426B2 (en) |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06177240A (en) * | 1992-12-03 | 1994-06-24 | Seiko Epson Corp | Semiconductor device |
| US5665655A (en) * | 1992-12-29 | 1997-09-09 | International Business Machines Corporation | Process for producing crackstops on semiconductor devices and devices containing the crackstops |
| JP2002094008A (en) * | 2000-09-20 | 2002-03-29 | Sanyo Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| JPWO2004097917A1 (en) * | 2003-04-30 | 2006-07-13 | 富士通株式会社 | Semiconductor device manufacturing method, semiconductor wafer, and semiconductor device |
| JP2006203215A (en) * | 2006-01-23 | 2006-08-03 | Renesas Technology Corp | Semiconductor integrated circuit device and method of manufacturing the same |
| JP2008060606A (en) * | 2007-11-14 | 2008-03-13 | Renesas Technology Corp | Manufacturing method of semiconductor device |
| US7459768B2 (en) | 2003-12-24 | 2008-12-02 | Elpida Memory, Inc. | Semiconductor wafer and dicing method |
| JP2009239149A (en) * | 2008-03-28 | 2009-10-15 | Nec Electronics Corp | Semiconductor wafer, semiconductor chip, semiconductor device, and method of manufacturing semiconductor device |
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| JPS6226839A (en) * | 1985-07-29 | 1987-02-04 | Oki Electric Ind Co Ltd | Semiconductor substrate |
| JPS62112348A (en) * | 1985-11-12 | 1987-05-23 | Toshiba Corp | Manufacture of semiconductor device |
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|---|---|---|---|---|
| JPH06177240A (en) * | 1992-12-03 | 1994-06-24 | Seiko Epson Corp | Semiconductor device |
| US5665655A (en) * | 1992-12-29 | 1997-09-09 | International Business Machines Corporation | Process for producing crackstops on semiconductor devices and devices containing the crackstops |
| JP2002094008A (en) * | 2000-09-20 | 2002-03-29 | Sanyo Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| JP4580867B2 (en) * | 2003-04-30 | 2010-11-17 | 富士通セミコンダクター株式会社 | Semiconductor device manufacturing method, semiconductor wafer, and semiconductor device |
| US8513776B2 (en) | 2003-04-30 | 2013-08-20 | Fujitsu Semiconductor Limited | Semiconductor device and method capable of scribing chips with high yield |
| US9105706B2 (en) | 2003-04-30 | 2015-08-11 | Fujitsu Semiconductor Limited | Semiconductor device fabrication method capable of scribing chips with high yield |
| JPWO2004097917A1 (en) * | 2003-04-30 | 2006-07-13 | 富士通株式会社 | Semiconductor device manufacturing method, semiconductor wafer, and semiconductor device |
| US7459768B2 (en) | 2003-12-24 | 2008-12-02 | Elpida Memory, Inc. | Semiconductor wafer and dicing method |
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| JP2008060606A (en) * | 2007-11-14 | 2008-03-13 | Renesas Technology Corp | Manufacturing method of semiconductor device |
| JP2009239149A (en) * | 2008-03-28 | 2009-10-15 | Nec Electronics Corp | Semiconductor wafer, semiconductor chip, semiconductor device, and method of manufacturing semiconductor device |
| JP2011014605A (en) * | 2009-06-30 | 2011-01-20 | Sanyo Electric Co Ltd | Semiconductor apparatus and method of manufacturing the same |
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| WO2011074155A1 (en) * | 2009-12-15 | 2011-06-23 | パナソニック株式会社 | Semiconductor device and manufacturing method for same |
| JP2012069705A (en) * | 2010-09-22 | 2012-04-05 | Toshiba Corp | Semiconductor device and manufacturing method therefor |
| JP2011071547A (en) * | 2010-12-14 | 2011-04-07 | Renesas Electronics Corp | Method for manufacturing semiconductor integrated circuit device |
| WO2012095907A1 (en) * | 2011-01-14 | 2012-07-19 | パナソニック株式会社 | Semiconductor device and product employing flip-chip mounting |
| US9343365B2 (en) | 2011-03-14 | 2016-05-17 | Plasma-Therm Llc | Method and apparatus for plasma dicing a semi-conductor wafer |
| JP2012070004A (en) * | 2011-12-21 | 2012-04-05 | Mitsumi Electric Co Ltd | Manufacturing method of semiconductor device |
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|---|---|
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