JP2006203215A - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent erosion of pad portions on TEGs, and to enhance solderability of pad portions of a real device and shear strength, after the formation of solder bumps. <P>SOLUTION: A third layer wiring M3 in a chip region CA and the third layer wiring M3 in a scribe region SA of a semiconductor wafer are formed with a TiN-film M3a, Al alloy film M3b, and TiN-film M3c. A second pad portion PAD2 on a rewiring 49 in the chip region CA is cleaned, or an Au film 53a is formed thereon by electroless plating method. After forming the Au film 53a, retention inspection is carried out further; and subsequently, after forming an Au film 53b, solder bump electrodes 55 are further formed, thereafter. As a result, erosion by the plating solution or the like of the first pad portion PAD1, formed of the third layer wiring M3 in the scribe area SA where TEGs, are formed is prevented by the TiN-film M3c. In addition, wettability of solder of the second pad portion PAD2 and the shear strength after the solder bump formation thereof can be enhanced by the Au film 53a, 53b. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly, to a technique effective when applied to a semiconductor device having a metal formed by plating under a bump electrode and a manufacturing method thereof.

  Compared to wire bonding, where the bonding pads on the surface of an IC (Integrated Circuit) chip and the package leads are electrically connected by a thin gold wire, wireless bonding has been put to practical use as a package that can be made smaller and thinner. Has been.

  The wireless bonding refers to a mounting form in which protrusions (bumps) formed on a bonding pad portion of a chip are connected without using a bonding wire such as a gold thin wire when the IC chip is mounted on a printed board or the like.

  Among them, CSP (chip size package) is a general term for packages that are the same as or slightly larger than the size of a semiconductor chip, and 1) it is easy to increase the number of pins, 2) a space between bump electrodes can be widened, and For the reason that the diameter of the bump electrode can be increased, the bump electrode constituting the external connection terminal is arranged in an area at the center of the chip (so-called area array structure).

  In order to manufacture an IC having this area array structure, for example, wiring for connecting a pad portion arranged along the peripheral portion of the chip and a bump electrode arranged in an area on the entire surface of the chip, so-called rewiring is required. Become.

For example, Japanese Patent Laid-Open No. 2000-294607 (Patent Document 1) discloses an insulating layer that includes an opening 6A that exposes the surface of the electrode pad portion 2A in an insulating film 6 made of polyimide resin, and includes the inside of the opening 6A. A wiring 7 made of, for example, a copper (Cu) film is formed on the wiring 6. Further, an insulating layer 8 is formed on the wiring 7, and an opening 8 B that exposes one end side of the wiring 7 is formed in the insulating layer 8. A technique for forming electrode pad portions 9B having an arrangement pitch wider than the arrangement pitch of electrode pad portions 2A on 8B is disclosed.
JP 2000-294607 A

  The present inventors are engaged in research and development of semiconductor integrated circuit devices (semiconductor devices), and are considering using rewiring for connecting electrode pad portions and bump electrodes. In addition, a bump electrode is formed on the rewiring, and an Au (gold) film or the like is being studied as the underlying film, and an economical plating method is being considered as the formation method. .

  On the other hand, on the wafer, in order to inspect the basic characteristics of the semiconductor integrated circuit, for example, the connection resistance of the wiring and plug, the temperature characteristics thereof, etc., in the same process as the elements and wiring constituting the actual semiconductor integrated circuit A test pattern (TEG: Test Element Group) is formed.

  Such a TEG is formed on a so-called scribe line between chip regions where an actual semiconductor integrated circuit is formed.

  However, it is not necessary to form a rewiring or bump electrode on the pad portion on the TEG, and when a rewiring or a protective layer on the upper portion is formed, the laminated film thickness on the scribe line is large. Therefore, dicing (separation) becomes difficult.

  Therefore, as will be described in detail later, when the base film or the like is formed, the pad portion on the TEG is exposed, and the pad portion is eroded by the plating solution or the cleaning solution before plating.

  In addition, in the semiconductor integrated circuit, in addition to the test using the TEG, the actual characteristics of the semiconductor integrated circuit are also inspected. For example, in an electrically erasable programmable read only memory (EEPROM) such as a flash memory, for example, in order to inspect (guarante) the life of the flash memory, The sample is exposed (burned in) for about 8 hours in an atmosphere at 250 ° C., and the characteristics of the memory cell before and after that, for example, the change in the amount of charge accumulated in the floating electrode are measured to determine whether it is good or bad.

  At this time, the surface of the pad portion used for the inspection is 1) to reduce the contact resistance of the probe needle contacting the pad portion, and 2) the solder bump formed on the pad portion after the inspection. In order to improve the property, the above-described gold (Au) layer is formed as a base film.

  However, when a thermal load due to burn-in is applied to the Au layer, as will be described in detail later, deterioration of wettability during solder mounting and deterioration of shear strength after formation of solder bumps occurred.

  An object of the present invention is to enable appropriate evaluation of a semiconductor integrated circuit device by preventing erosion of a pad portion on a TEG.

  Another object of the present invention is to prevent the defective plating in the chip area where the actual device is formed by preventing the pad portion on the TEG from being exposed, and thereby to improve the characteristics of the semiconductor integrated circuit device. It is to improve.

  Another object of the present invention is to improve the wettability at the time of solder mounting and the shear strength after the solder mounting and to improve the characteristics of the semiconductor integrated circuit device.

  The above object and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  (1) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the first wiring having the first conductive film and the second conductive film on the top is formed in the chip region of the semiconductor wafer, and the first wiring is formed in the scribe region. A test pattern having the same configuration as that of one wiring is formed, a second wiring is formed on the first wiring via an insulating film, and then a pad region on the second wiring is formed on the surface of the test pattern with the second conductivity. Cleaning is performed with the film exposed. Alternatively, the plating film is formed on the pad region on the second wiring in a state where the second conductive film on the surface of the test pattern is exposed.

  (2) The semiconductor integrated circuit device according to the present invention includes (a) a first wiring having a first conductive film and a second conductive film on the first conductive film, and (b) a first wiring that is a part of the first wiring. An insulating film having an opening in the pad region; and (c) a second conductive film formed on the insulating film including the inside of the opening and a third conductive film formed on the second conductive film. 2 wirings having a second wiring for connecting the first pad region and the second pad region, and (d) a bump electrode formed on the second pad region on the second wiring. . Further, a test pattern having the same configuration as the first wiring is formed in the scribe region of the semiconductor wafer, and the second wiring and the plating film are not formed on the test pattern.

  (3) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the first conductive film is formed on the pad region of the first wiring electrically connected to the semiconductor element formed on the semiconductor wafer. A heat treatment is performed on the wafer, the characteristics of the semiconductor element are inspected using the pad region, and then a second conductive film is further formed on the first conductive film.

  (4) In the method of manufacturing a semiconductor integrated circuit device of the present invention, a polyimide film having an opening is formed in a pad region on a wiring electrically connected to a nonvolatile memory formed on a semiconductor substrate in a wafer state. Thereafter, in the wafer state, a thermal load is applied to the semiconductor substrate for a predetermined time, and the information retention characteristics of the nonvolatile memory are inspected using the pad area.

  (5) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a polyimide film having an opening is formed in a pad region on a wiring electrically connected to a nonvolatile memory formed on a semiconductor substrate in a wafer state. In the wafer state, a thermal load is applied to the semiconductor substrate for a certain time, the information retention characteristics of the nonvolatile memory are inspected using the pad area, and then a plating film is formed on the pad area.

  The effects obtained by the representative ones of the inventions disclosed by the present application will be briefly described as follows.

  (1) Since the first wiring is formed in the chip region of the semiconductor wafer, the test pattern is formed in the scribe region, and these are constituted by the first conductive film and the second conductive film on the first conductive film. Even if the pad area on the second wiring is formed after the second wiring is formed on the one wiring via the insulating film, or the plating film is formed on the second wiring, the surface of the test pattern remains on the second conductive layer. Since it is covered with a conductive film, the test pattern can be prevented from corroding. In addition, the semiconductor integrated circuit device can be appropriately evaluated using the test pattern. Further, by preventing the test pattern from corroding, it is possible to prevent plating defects in the chip region where the actual device is formed. In addition, the characteristics of the semiconductor integrated circuit device can be improved.

  (2) Also, a first conductive film is formed on the pad region of the first wiring electrically connected to the semiconductor element formed on the semiconductor wafer, the semiconductor wafer is subjected to heat treatment, and the pad region is used. Since the second conductive film is further formed on the first conductive film after inspecting the characteristics of the semiconductor element, the wettability during solder mounting and the shear strength after solder formation can be improved. In addition, the characteristics of the semiconductor integrated circuit device can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

(Embodiment 1)
A semiconductor integrated circuit device according to an embodiment of the present invention will be described in accordance with a manufacturing method thereof.

  (1) First, referring to FIG. 1 to FIG. 6, a nonvolatile semiconductor memory cell (hereinafter simply referred to as “memory cell”) is formed in a memory cell formation region (MCFR) of a semiconductor wafer, and n on a peripheral circuit formation region. A process until the channel type MISFET Qn is formed will be described. 1 to 6 are principal part sectional views or principal part plan views of the substrate showing a method of manufacturing the semiconductor integrated circuit device (nonvolatile semiconductor memory) according to the first embodiment of the present invention.

  1 to 3 are cross-sectional views of the main part of the chip area CA of the semiconductor wafer (semiconductor substrate 1), and FIG. 4 is a cross-sectional view of the main part of the scribe area SA of the semiconductor wafer. 1 and 2 are cross-sectional views of the main part of the memory cell formation area (MCFR) in the chip area CA, and FIG. 3 is a cross-sectional view of the main part of the peripheral circuit formation area (PCFR) in the chip area CA. The figure is shown. 5 is a plan view of the principal part of the substrate in the memory cell formation region (MCFR). FIG. 1 corresponds to the AA cross section of FIG. 5, and FIG. 2 corresponds to the BB cross section of FIG. .

  That is, as shown in FIG. 34, the semiconductor wafer (semiconductor substrate) 1 on which the semiconductor integrated circuit device of the present embodiment is formed has a plurality of substantially rectangular chip areas CA. It is partitioned by a scribe area SA. As will be described later, the chip is separated into pieces by cutting the scribe area SA.

  As shown in FIGS. 1 to 5, element isolation 4 is formed in a semiconductor substrate (hereinafter simply referred to as “substrate”) 1 made of, for example, p-type single crystal silicon. This element isolation 4 is formed by the following method, for example.

  A groove is formed by etching the substrate 1. Thereafter, the substrate 1 is thermally oxidized to form a thin silicon oxide film on the inner wall of the groove, and further, for example, a silicon oxide film 6 is formed as an insulating film on the substrate 1 including the inside of the groove by CVD (Chemical Vapor Deposition). Deposit by the method. Next, the silicon oxide film 6 outside the trench is polished by a CMP (Chemical Mechanical Polishing) method to bury the silicon oxide film 6 inside the trench. As a result, the active regions where memory cells and peripheral circuits are formed are separated. The element isolation 4 may be formed by using a LOCOS (Local Oxidation of silicon) method.

  Next, a p-type impurity (for example, boron) is ion-implanted into the substrate 1 and then subjected to a heat treatment to diffuse the impurity, thereby forming a p-type impurity in the memory cell formation region (MCFR) and the peripheral circuit formation region (PCFR). Well 8 is formed. An n-type well is formed in the peripheral circuit formation region (PCFR) as necessary, but the illustration thereof is omitted here.

  Next, a gate insulating film 11 is formed on the surface of the p-type well 8 by thermally oxidizing the substrate 1 (p-type impurity). The gate insulating film 11 becomes a gate insulating film of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) that constitutes the memory cell and the peripheral circuit. If these film thicknesses are different, they are formed in separate steps. To do.

  Next, a polycrystalline silicon film doped with phosphorus as a conductive film is deposited on the substrate 1 by, for example, a CVD method. Next, by dry etching the polycrystalline silicon film using a photoresist film (not shown, hereinafter simply referred to as “resist film”) as a mask, in the memory cell formation region (MCFR), as shown in FIG. A polycrystalline silicon pattern 13a extending in the X direction is formed. FIG. 5 is a plan view of an essential part of the substrate of the memory cell formation region (MCFR) after the formation of the polycrystalline silicon pattern 13a. Further, the gate electrode G is formed in the peripheral circuit formation region (PCFR). The polycrystalline silicon pattern 13a is then etched in the Y direction to become the floating electrode FG of the memory cell (see FIG. 6).

  Next, on the polycrystalline silicon pattern 13a and the gate electrode G, for example, an ONO film 15 is formed as an insulating film. The ONO film 15 is a laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film, and is formed by sequentially depositing these films using, for example, a CVD method. Note that a silicon nitride film may be further deposited on the uppermost silicon oxide film.

  Next, a polycrystalline silicon film 17 doped with phosphorus as a conductive film is deposited on the substrate 1 by, for example, a CVD method. The polycrystalline silicon film 17 becomes a control electrode CG of the memory cell. Subsequently, a silicon nitride film 19 is deposited thereon as an insulating film by, for example, a CVD method.

  Next, the silicon nitride film 19, the polycrystalline silicon film 17, the ONO film 15, and the polycrystalline silicon pattern 13a are dry-etched using a resist film (not shown) in the memory cell formation region (MCFR) as a mask.

  By this dry etching, the polycrystalline silicon pattern 13a is divided for each memory cell and becomes the floating electrode FG. Further, the control electrode CG is formed on the floating electrode FG via the ONO film 15. As shown in FIG. 6, the control electrode CG extends in the Y direction. FIG. 6 is a plan view of the main part of the substrate of the memory cell formation region (MCFR) after the formation of the control electrode CG.

Next, an n-type impurity (for example, arsenic) is ion-implanted into the p-type well 8 using a resist film (not shown) as a mask, and then subjected to heat treatment to diffuse the impurity, thereby forming n ^{− on} both sides of the gate electrode G. A type semiconductor region 21 is formed. Further, the n ⁻ type semiconductor region 21 is formed on one side of the control electrode CG.

Further, an n-type impurity (for example, arsenic) is ion-implanted into the p-type well 8 using a resist film (not shown) as a mask, and then heat treatment is performed to diffuse the impurity, thereby causing n ⁺ on the other side of the control electrode CG. A type semiconductor region 22 (drain) is formed.

  Next, a side wall spacer 23 is formed on the side walls of the control electrode CG and the gate electrode G by depositing a silicon nitride film as an insulating film on the substrate 1 by, for example, a CVD method and anisotropically etching.

Next, an n-type impurity (phosphorus or arsenic) is ion-implanted into the p-type well 8 using a resist film (not shown) as a mask, and then heat treatment is performed to diffuse the impurity, thereby forming n ^{+ on} both sides of the gate electrode G. A type semiconductor region 25 (source and drain regions) is formed. Further, an n ⁺ type semiconductor region 25 (source) is formed on one side (n ⁻ type semiconductor region 21) of the control electrode CG.

  Through the above steps, a memory cell having the control electrode CG, the ONO film 15, the floating electrode FG, and the gate insulating film 11 is formed in the memory cell formation region (MCFR), and the n-channel MISFET is formed in the peripheral circuit formation region (PCFR). Qn is formed. In the present embodiment, the manufacturing process has been described by taking the n-channel MISFET in which the peripheral circuit formation region (PCFR) is formed as an example, but of course the p-channel MISFET is formed in the peripheral circuit formation region (n-type well). May be formed. The p-channel type MISFET can be formed by the same process as the above-described process (in the case of an n-channel type MISFET) except that the conductivity type of the impurity region constituting the MISFET is different. Description is omitted.

  (2) Next, for example, a process of forming a three-layer wiring on the memory cell and the n-channel type MISFET Qn will be described with reference to FIGS. 7 to 12 are principal part sectional views or principal part plan views of the substrate showing the method of manufacturing the semiconductor integrated circuit device (nonvolatile semiconductor memory) according to the first embodiment of the present invention. 7 to 9 are main part sectional views of the chip area CA of the semiconductor wafer (semiconductor substrate 1), and FIG. 10 is a main part sectional view of the scribe area SA of the semiconductor wafer. 7 and 8 are cross-sectional views of the main part of the memory cell formation region (MCFR) in the chip area CA, and FIG. 9 is a cross-sectional view of the main part of the peripheral circuit formation region (PCFR) in the chip area CA. The figure is shown. 11 and 12 are plan views of the principal part of the substrate in the memory cell formation region (MCFR). FIG. 7 corresponds to the AA cross section, and FIG. 8 corresponds to the BB cross section.

First, as shown in FIGS. 7 to 11, a W (tungsten) film is deposited as a conductive film on the substrate 1 by, for example, a CVD method. Next, the W film is dry-etched using a resist film (not shown) as a mask, so that the n ⁺ type semiconductor region 22 (drain) and the n ⁺ type semiconductor region 25 (source) in the memory cell formation region (MCFR) are formed. Then, the conductive layer ML is formed. As shown in FIG. 11, the conductive layer ML is formed separately for each memory cell on the n ⁺ type semiconductor region 22 (drain), and the n ⁺ type semiconductor region 25 (source). In the above, it is formed so as to connect the sources of the memory cells located in the Y direction.

Next, a silicon oxide film 31 is deposited as an insulating film on the conductive layer ML and the silicon nitride film 19 by, for example, a CVD method. Next, the contact hole C1 is formed by removing the silicon oxide film 31 on the conductive layer ML. At this time, the contact hole C1 is also formed on the n ⁺ type semiconductor region 25 (source and drain regions) in the peripheral circuit formation region (PCFR). As shown in FIG. 11, the contact hole C1 on the n ⁺ type semiconductor region 25 (source) in the memory cell formation region (MCFR) appears in a cross section different from that in FIG.

  Next, a laminated film (not shown) of Ti (titanium) and TiN (titanium nitride) is sequentially deposited as a barrier film on the silicon oxide film 31 including the inside of the contact hole C1, for example, by sputtering, and then further conductive. As a conductive film, a W (tungsten) film is deposited by, for example, CVD. Next, the plug P1 is formed by removing the W film, TiN film, and Ti film outside the contact hole C1 by, for example, the CMP method. FIG. 11 is a plan view of the main part of the substrate in the memory cell formation region (MCFR) after the plug P1 is formed.

Next, a W film is deposited as a conductive film on the silicon oxide film 31 including the plug P1 by, for example, a CVD method. Next, the first layer wiring M1 is formed by dry etching the W film using a resist film (not shown) as a mask. The first layer wiring M1 in FIG. 7 and FIG. 8 becomes the sub bit line SBL, and is formed on the n ⁺ type semiconductor region 25 (source) in the memory cell formation region (MCFR) as shown in FIG. The first layer wiring M1 on the plug P1 becomes the common source line CSL. FIG. 12 is a plan view of an essential part of the substrate of the memory cell formation region (MCFR) after the formation of the first layer wiring M1.

  Next, a silicon oxide film 33 is deposited as an insulating film on the silicon oxide film 31 including the first layer wiring M1 by, for example, a CVD method. Next, the contact hole C2 is formed by removing the silicon oxide film 33 on the first layer wiring M1. Next, a plug P2 is formed by embedding a conductive film in the contact hole C2 in the same manner as the plug P1.

  Next, a W film is deposited as a conductive film on the silicon oxide film 33 including the plug P2 by, for example, a CVD method. Next, the second layer wiring M2 is formed by dry etching the W film using a resist film (not shown) as a mask. 7 and 8 is the main bit line MBL connected to the sub bit line SBL via a plug (not shown). The main bit line MBL extends in the same direction (X direction) as the sub bit line SBL.

  Next, a silicon oxide film 35 is deposited as an insulating film on the silicon oxide film 33 including the second layer wiring M2 by, for example, a CVD method. Next, the contact hole C3 is formed by removing the silicon oxide film 35 on the second layer wiring M2. Next, similarly to the plug P1, a plug P3 is formed by embedding a conductive film in the contact hole C3.

  Next, a TiN film M3a, an Al (aluminum) alloy film M3b, and a TiN film M3c are deposited as conductive films on the silicon oxide film 35 including the plug P3 by, for example, a sputtering method. The TiN films M3a and M3c 1) increase the adhesion between the Al alloy film M3b and the insulating film such as the silicon oxide film 35, and 2) improve the electromigration resistance of the third layer wiring made of the Al alloy. It is formed to ensure the reliability of the wiring. In addition to the TiN film, a Ti film, a TiW film, a Ta (tantalum) film, a W (tungsten) film, a WN (tungsten nitride) film, or a stacked film of these films may be used.

  Next, the third layer wiring M3 is formed by dry etching the TiN film M3a, the Al (aluminum) alloy film M3b, and the TiN film M3c using a resist film (not shown) as a mask. 7 and FIG. 8, for example, the third layer wiring M3 extends in the same direction as the control electrode CG, and is connected to the control electrode CG via a plug or wiring (not shown).

  Here, as shown in FIG. 10, the third layer wiring M3 is also formed in the scribe region SA. The third layer wiring M3 in the scribe region SA is, for example, a test pattern (TEG pattern) for evaluating the wiring resistance and temperature characteristics of the third layer wiring M3. Although not shown, the third layer wiring M3 may be connected to other locations to be evaluated (plugs, wirings, memory cells, etc. formed in the scribe region).

  (3) Next, on the chip area CA (memory cell formation area and peripheral circuit formation area) and the third layer wiring M3 on the scribe area SA, a passivation film, a protective film such as a polyimide film, a rewiring, a bump electrode, etc. Although formed, these forming steps will be described with reference to FIGS. 13 to 21 and FIGS. These drawings are a cross-sectional view or a partially enlarged view of two chip areas CA and a scribe area SA between them. Note that layers below the silicon oxide film 35 are omitted.

  As described above, the third layer wiring M3 including the TiN film M3a, the Al (aluminum) alloy film M3b, and the TiN film M3c is formed in the chip area CA and the scribe area SA (FIGS. 7 to 10, FIG. 13 etc.). It does not matter whether the third layer wiring M3 on the chip area CA is formed in the memory cell formation area (MCFR) or in the peripheral circuit formation area (PCFR). .

  Next, as shown in FIG. 13, a silicon nitride film and a silicon oxide film are sequentially deposited as a protective film on the third-layer wiring M3 by, for example, a CVD method to form a passivation film 41 made of these laminated films. The passivation film 41 may be composed of a single layer.

  Next, the passivation film 41 at both ends of the scribe region SA is removed by dry etching to form an opening OA1. Thereby, the scribe area SA described with reference to FIG. 34 becomes clear.

  Next, as shown in FIG. 14, a polyimide resin film 43 having an opening at a desired position is formed on the passivation film 41. In order to form the polyimide resin film 43, first, a photosensitive polyimide resin film is spin-coated by about 5 μm and subjected to heat treatment (pre-baking). Next, after exposing and developing the polyimide resin film to open (OA2), heat treatment (post-bake) is performed to cure (cure) the polyimide resin film. At the post-baking time, for example, heat treatment is performed at 350 ° C. for about one hour.

  Next, as shown in FIG. 15, the lower passivation film 41 is dry-etched using the polyimide resin film 43 as a mask to expose a part of the third layer wiring M3 (TiN film M3c). The exposed region of the third layer wiring M3 is referred to as a first pad portion PAD1. Among the first pad portions PAD1, the first pad portion PAD1 on the chip area CA is used for rewiring and connection with a bump electrode, which will be described later, and the first pad section PAD1 on the scribe area SA is such an area. Further, for example, a probe needle is brought into contact therewith and an opening is made for evaluation (probe inspection). The evaluation includes, for example, evaluation of wiring resistance of the third layer wiring M3 and its temperature characteristics, or characteristics of wiring, plugs, memory cells, etc. (not shown) connected to the third layer wiring M3. In addition, after this process, in the state which 1st pad part PAD1 on scribe area | region SA is exposed, evaluation can be performed suitably.

  Here, what is important is that the uppermost TiN film M3c of the third-layer wiring M3 is not removed but left. That is, the surface of the TiN film M3c is exposed from the first pad portion PAD1.

  Next, as shown in FIG. 16, the polyimide resin film 43 in the scribe region SA is removed by dry etching. Note that this step may be omitted, and the polyimide resin film 43 on the scribe region SA may remain (the state shown in FIG. 15).

  Next, as shown in FIG. 17, a seed layer (power feeding layer) 45 is formed on the polyimide resin film 43 including on the first pad portion PAD <b> 1. The seed layer 45 is made of, for example, a laminated film of a Cr (chromium) film and a Cu (copper) film. For example, a thin Cr film having a thickness of about 75 nm is deposited on the polyimide resin film 43 by a sputtering method. Subsequently, a Cu film having a thickness of about 250 nm is deposited on the Cr film by sputtering.

  Next, as shown in FIG. 18, a resist film having a long groove 47 extending from the upper part of the first pad part PAD1 to the later-described second pad part PAD2 formation region using photolithography technology on the seed layer 45. R is formed.

  Next, as shown in FIG. 19, a Cu film 49a is formed inside the long groove 47 by electrolytic plating. In order to form the Cu film 49a, the substrate 1 is immersed in a Cu plating solution to fix the seed layer 45 to the minus (−) electrode, and the seed layer 45 at the bottom of the long groove 47 not covered with the resist film R is formed. A Cu film 49a having a thickness of about 3.5 μm is deposited on the surface of the film.

  Thereafter, a Ni (nickel) film 49b is formed on the Cu film 49a inside the long groove 47 by an electroplating method. In order to form the Ni film 49b, the substrate 1 is immersed in a plating solution for Ni, the seed layer 45 is fixed to the minus (−) electrode, and the Cu film 49a at the bottom of the long groove 47 not covered with the resist film R is formed. A Ni film 49b having a thickness of about 3.3 μm is deposited on the surface of the film.

  Here, as shown in FIG. 19, the scribe region SA is covered with the resist film R, and the Cu film 49a and the Ni film 49b are not formed. This is because it is not necessary to form a rewiring which will be described later on the scribe area SA, and it is easy to cut (dicing) by making the laminated film thickness on the scribe line as small as possible.

  Thereafter, after removing the resist film R, the seed layer 45 which has become unnecessary by wet etching using the Cu film 49a and the Ni film 49b as a mask is removed. As a result, a rewiring 49 composed of a seed film 45, a laminated film of a Cu film 49a and a Ni film 49b is formed (FIG. 20).

  For this rewiring, for example, it is difficult to form a bump electrode on the first pad portion PAD1 (see FIG. 35) densely formed around the chip area CA. When the bump electrodes are arranged at a wider interval than the first pad portion PAD1, the first pad portion PAD1 and the bump electrode (second pad portion PAD2 described later) are connected. Further, the rewiring can be said to be a wiring for rearranging the first pad portion PAD1 having a narrow interval to the second pad portion PAD2 having a larger interval. Or it can be said that it is wiring for changing the space | interval between pad parts.

  The seed layer 45 below the rewiring 49 has a role of improving the adhesive strength between the Cu film 49 a and the polyimide resin film 43 below the Cu film 49 a and a role of preventing Cu from diffusing into the polyimide resin film 43. Fulfill.

  Here, the reason why the Ni film 49b is laminated on the Cu film 49a is to prevent an undesired product from being formed due to contact between a solder bump electrode 55 (to be described later) and the Cu film 49a. Further, the Ni film has good adhesion to the polyimide resin film to be formed later. In addition to Ni, Cr, Ti, TiN, Ta, TaN, WN, or the like may be used.

  Next, as shown in FIG. 21, a polyimide resin film 51 in which the second pad portion PAD <b> 2 and the scribe region SA on the rewiring 49 are opened is formed. The polyimide resin film 51 can be formed in the same manner as the polyimide resin film 43. That is, a photosensitive polyimide resin film is spin-coated by about 5 μm, and heat treatment (pre-baking) is performed. Next, the polyimide resin film is exposed and developed to open the second pad portion PAD2 and the scribe area SA, and then heat treatment (post bake) is performed to cure (cure) the polyimide resin film. At the post-baking time, for example, heat treatment is performed at 350 ° C. for about one hour.

  Here, from the opening (second pad portion PAD2) of the polyimide resin film 51, the surface of the rewiring 49 (Ni film 49b) is exposed. Further, since the polyimide resin film 51 in the scribe region SA is removed, the surface of the third layer wiring M3 (TiN film M3c) is exposed.

  Next, an Au film 53a is formed by electroless plating on the Ni film 49b exposed at the opening portion (second pad portion PAD2) of the polyimide resin film 51. First, an ashing process is performed. Then, treatment such as alkali degreasing and acid cleaning is performed.

  That is, since an organic contamination layer Or such as an oxide film Ox or a polyimide resin film residue is formed on the Ni film 49b of the second pad portion PAD2 (circle portion in FIG. 21), first, oxygen is added. The organic contamination layer Or is removed by the ashing process used. However, in order to prevent the polyimide resin film 51 and the like from being excessively removed, the asher amount is about 0.2 μm.

  Next, alkali degreasing and acid cleaning are performed to remove the oxide film Ox and activate the surface of the Ni film 49b. The alkaline degreasing treatment is performed, for example, at 60 ° C. for 10 minutes using a sodium metasilicate solution. The acid cleaning is performed, for example, using 20% hydrochloric acid (HCl) at 25 ° C. for 5 minutes.

  Here, according to the present embodiment, although the third-layer wiring M3 in the scribe region SA is exposed, the TiN film M3c remains on the surface, so that the above-described processing such as acid cleaning is performed. It is possible to prevent the underlying Al alloy film M3b from corroding.

  For example, as shown in FIG. 22, the TiN film M3c on the surface of the third layer wiring M3 can be removed, for example, when the first pad portion PAD1 is opened.

  However, in this case, the Al alloy film M3b is exposed from the first pad portion PAD1, and is corroded (dissolved or oxidized) by a cleaning liquid such as HCl, for example.

  On the other hand, according to the present embodiment, as described above, since the TiN film M3c serving as a protective film against the acidic cleaning liquid remains on the Al alloy film M3b, the corrosion of the Al alloy film M3b remains. Can be prevented. Here, in order to improve adhesion and electromigration resistance, a Ti film, a TiW film, a Ta film, a W film or a single film of WN film, or a laminated film of these films is used in addition to the TiN film. As the protective film against the acidic cleaning solution, an oxidation resistant TiN film, Ta film, TaN film, W film or WN film single layer film, or a laminated film of these films is suitable. These films only need to cover the surface of the wiring. For example, a structure in which a Ti film and a TiN film are sequentially stacked on the Al alloy film M3b may be used. Of course, as a protective film against the acidic cleaning liquid, the film may be separately formed after the wiring is formed and before the cleaning process or the plating process.

  Further, when the TiN film M3c on the surface of the third layer wiring M3 is removed, for example, when the first pad portion PAD1 is opened, as shown in FIG. 23, TiN on the surface of the third layer wiring M3 in the chip area CA. The film M3c is also removed. In this case, the opening is deepened by the thickness of the TiN film M3c, and the film forming properties of the Cr film and the Cu film constituting the seed layer 45 are deteriorated at the corner of the opening. On the other hand, according to the present embodiment, as shown in FIG. 24, the step of the opening is reduced, and the coverage of the seed layer 45 at the corner can be improved.

  Further, when etching the TiN film, side etching of the TiN film may occur. That is, when opening the first pad portion PAD1, the side wall of the TiN film M3c recedes from the side wall of the opening portion formed by the passivation film 41 and the polyimide resin film 43, which is the upper layer of the TiN film M3c, and an overhang shape is formed. Therefore, when a Cr film or a Cu film (seed layer 45) is formed in such an opening, the coverage at the corner is deteriorated, resulting in disconnection. In particular, when the TiN film M3c, the passivation film 41, and the polyimide resin film 43 are etched using different masks, the side walls of the TiN film M3c are exposed to the etching many times, which tends to form an overhang, and the step is cut off. Is likely to occur. On the other hand, according to the present embodiment, as shown in FIG. 24, since the TiN film M3c is left, the coverage of the seed layer 45 in the corner portion can be improved.

  23 and 24 are partially enlarged views of the vicinity of the first pad portion (PAD1) in FIGS. 21 and 22, respectively.

  Next, as shown in FIG. 25, an Au film 53a having a thickness of about 20 nm to 150 nm is deposited on the Ni film 49b exposed from the second pad portion PAD2 by electroless plating. As a plating solution, a plating solution for Au, for example, a sodium gold sulfite-based plating solution is used and treated at 55 ° C. for 10 minutes. This plating method utilizes the difference in the ionization tendency between Ni and Au and replaces them to form the Au film 53a. This is called the substitution plating method among the electroless plating methods. In this substitution plating, after the Ni on the surface of the Ni film 49b is replaced with Au to some extent, the deposition of Au is rate-determined, and it is difficult to obtain a thick film (see graph (a) in FIG. 38). ). Therefore, as shown in FIG. 26, discontinuous portions (pinholes) are easily formed in the film. 26 is a partially enlarged view of the vicinity of the second pad portion (PAD2) in FIG. 25 (the same applies to FIGS. 30 to 32).

  As described above, the Au film 53a is formed on the Ni film 49b of the second pad portion PAD2. 1) The contact resistance of the probe needle abutting on the second pad portion PAD2 is reduced during the retention test described later. 2) This is for improving the wettability of the solder bump electrode 55 formed on the second pad portion PAD2. This “wetting property” means, for example, the degree of familiarity between the alloy solder and the Au film when an alloy solder of Sn (tin) and Pb (lead) is mounted on the second pad portion PAD2.

  Here, according to the present embodiment, the third layer wiring M3 is exposed in the scribe region SA, but the TiN film M3c remains on the surface thereof, so that the plating solution (for example, sulfite, for example) Corrosion of the Al alloy film M3b by the gold-sodium-based plating solution) can be prevented. In addition, the film quality of the Au film 53a can be improved and the film formability can be improved.

  For example, as shown in FIG. 22, the TiN film M3c on the surface of the third-layer wiring M3 can be removed when the first pad portion PAD1 is opened. In this case, from the first pad portion PAD1 The Al alloy film M3b is exposed, and the Al alloy film M3b is corroded (dissolved and oxidized) by the plating solution.

  Further, when the inspection using the first pad portion PAD1 has already been completed, it seems that there is no problem even if the Al alloy film M3b is corroded.

  However, when a metal such as Al is dissolved in the plating solution, the plating solution is deteriorated, the deposition of the Au film 53a is inhibited, and the film quality of the Au film 53a is deteriorated.

  In some cases, the third layer wiring M3 (TiN film M3c) in the scribe region SA and the third layer wiring M3 (TiN film M3c) in the chip region CA are electrically connected (see FIG. 22). In this case, a battery effect to be described later occurs, and the deposition of the Au film 53a is inhibited in the chip area CA.

  The battery effect is that, in the scribe area SA, the Al alloy film M3b is dissolved as aluminum ions due to chlorine ions in the plating solution. At this time, the emitted electrons affect the Ni film 49b in the chip area CA. And inhibit the activation of its surface. As a result, the deposition rate of the Au film 53a becomes slow. This phenomenon can also occur during the above-described cleaning using HCl or the like.

  On the other hand, according to the present embodiment, since the TiN film M3c remains on the Al alloy film M3b, the corrosion of the Al alloy film M3b can be prevented, and the surface of the Ni film 49b in the chip area CA is activated. Can be appropriately performed, and its activation can be maintained. As a result, the Au film 53a can be effectively deposited on the Ni film 49b.

  Next, a retention test is performed. This retention inspection is for inspecting information retention characteristics when a memory cell is driven and electric charges are accumulated in the control electrode CG. For example, the retention inspection is accelerated by exposure to high temperatures (retention baking). I do. The retention inspection is preferably performed at the time when a high-temperature heat treatment process such as baking of the polyimide resin film 51 or the like is completed. This is because if there is a high-temperature treatment process after the inspection, the characteristics may change due to the process.

  First, information retention characteristics in the current process are measured. As shown in FIG. 27, the probe needle N is brought into contact with the Au film 53a on the surface of the second pad portion PAD2, and measurement is performed. Here, as described above, according to the present embodiment, since the Au film 53a is formed with good film formability, the above measurement can be performed with high accuracy.

  Next, as shown in FIG. 28, the substrate 1 (semiconductor wafer) is exposed to, for example, a temperature of 250 ° C. for 8 hours (retention bake).

  Next, the information retention characteristic after retention baking is measured. That is, as shown in FIG. 29, the probe needle N is brought into contact with the Au film 53a on the surface of the second pad portion PAD2, and measurement is performed. The TEG evaluation described above may be performed before or after the retention test.

  Next, a bump electrode is formed on the Au film 53a on the surface of the second pad portion PAD2, and the present inventors conducted the following examination.

  When the solder bump electrode 55 was formed on the Au film 53a (FIG. 29), the wettability of the solder was poor, resulting in a failure. At this time, the film thickness of the Au film 53a was 55 nm.

  On the other hand, when the solder bump electrode 55 was formed on the Au film 53a (FIG. 27) before retention baking, there was no poor solder wettability and the shear strength of the solder bump electrode 55 was good.

  Therefore, the above-mentioned defect has been concluded that the deterioration of the surface state of the second pad portion PAD2 due to the retention bake is deeply involved, and the state is examined. In addition, the shear strength of the solder bump electrode 55 was improved.

  First, the surface of the substrate 1 is cleaned using an acidic cleaning liquid such as HCl (hydrogen chloride). The reason for this cleaning will be described below.

  That is, as shown in FIG. 30, when there is a heat treatment exceeding 200 ° C. in the atmosphere such as retention bake, Ni is exposed through the discontinuous portion (pinhole) of the Au film 53a, and the oxide film Ox is formed. . Also, an oxide film is formed on the pinhole and at the interface between the Au film 53a and the Ni film 49b due to oxygen entering from the discontinuous portion (pinhole) of the Au film 53a.

  FIG. 39 shows the relationship between the heat treatment temperature [° C.] and the Ni oxide film thickness [nm]. Graph (a) shows the case where the Au film was not formed, graph (b) shows the case where the Au film was formed to 44 nm, and graph (c) shows the case where the Au film was formed to 22 nm. The heat treatment time was 8 hours.

  As shown in the graphs (a) to (c), the oxide film thickness increases as the heat treatment temperature increases. In any graph, the thickness of the oxide film formed abruptly increases from around 200 ° C. Further, regarding the Ni film on which the Au film was formed, there was a tendency that the smaller the film thickness of the Au film, the larger the oxide film thickness. There was a tendency that the surface of the Ni film on which the Au film was formed had a larger oxide film thickness than the surface of the Ni film (no Au film was formed). This is because when the Au film is thin, the Au film has an island shape, so that the surface thereof becomes uneven and the surface area becomes large. Since Ni in the Ni film diffuses and adsorbs oxygen on this surface, it is presumed that the oxide film thickness is increased by attaching the Au film.

  The presence of such an oxide film Ox degrades the solder wettability when mounting the solder, and also degrades the shear strength of the solder bump electrode. The shear strength is, for example, the stress until the solder bump electrode 55 is peeled off or broken when a lateral stress is mechanically applied to the solder bump electrode 55. Therefore, as described above, for example, 20% hydrochloric acid (HCl) is used for cleaning at 25 ° C. for 5 minutes to remove the oxide film (FIG. 31).

  Next, as shown in FIG. 32, an Au film 53b is deposited on the Au film 53a on the second pad portion PAD2 by performing substitution plating. As a result, a base film 53 made of a laminated film of Au films 53a and 53b is formed. The thickness of this laminated film is, for example, about 85 nm. The reason why the Au film 53b further grows on the Au film 53a in this way is that Ni under the pinhole (discontinuous portion) of the Au film 53a is replaced with Au, and Ni present on the surface of the Au film 53a This is probably because ions are replaced with Au. When the Au film (53a, 53b) after the second plating treatment was observed with a TEM (Transmission Electron Microscope), it was a continuous film as shown in FIG.

  Further, during this cleaning and displacement plating, since the TiN film M3c remains on the Al alloy film M3b on the scribe area SA, corrosion of the Al alloy film M3b can be prevented, and the Ni film 49b in the chip area CA can be prevented. The surface of the surface can be appropriately activated.

  Note that annealing (heat treatment) may be performed in order to stabilize the boundary between the Au film (undercoat film 53) and the Ni film.

  Thereafter, as shown in FIG. 33, a bump electrode 55 made of Sn / Pb alloy solder is connected on the base film 53. The bump electrode 55 is formed by, for example, a printing method or a ball transfer method. In FIG. 33, the Au films 53a and 53b are shown for ease of explanation, but the Au films 53a and 53b are absorbed in the solder after solder mounting.

  Thus, according to the present embodiment, since the oxide film Ox on the second pad portion PAD2 is removed, the wettability of the solder can be improved. Further, since the Au film 53b is further formed on the Au film 53a after the retention bake, the discontinuity (pinhole) of the Au film can be reduced, and the wettability of the solder can be improved. Further, the shear strength of the solder bump electrode 55 can be improved. For example, a shear strength of 250 gf / bump was obtained under the above conditions.

  Here, the inventors reduce the number of pinholes by increasing the replacement plating processing time and setting the thickness of the Au film to, for example, about 74 nm (about twice the thickness of the Au film 53a). A method for suppressing the formation of the Ni oxide film Ox was also examined. In this case, as shown in FIG. 37, a processing time of 1900 seconds or more is required to secure a film thickness of about 70 nm.

  However, in this case as well, defects such as solder wettability occurred and the solder bump electrode 55 peeled off at the interface with the Ni film.

  FIG. 37 shows the relationship between the plating time and the Au film thickness. As shown in the graph (a), the Au film thickness increases as the plating time increases. In the present embodiment, for example, the Au film 53a is formed before the processing shown in the graph (a) (for example, 700 seconds), and then the Au film 53b is formed by the processing shown in the graph (b). Thus, by forming the film in two stages, a desired film thickness can be ensured in a shorter time than in the case of continuous processing (graph (a)).

  In addition, as shown in FIG. 40, for example, the formation of a pinhole, the exposure of the Ni film 49b, and the oxidation thereof were also studied by forming an Au film 153a of about 1000 nm, for example.

  However, in this case, it is difficult to use the above-described displacement plating method. For example, it is necessary to use a method of forming a thick plating film (autocatalytic plating) by adding a reducing agent to the plating solution. . In this case, the plating solution tends to be unstable, and a film with good film quality cannot be obtained. In addition to the Ni film 49b surface, there is a high possibility that the plating film is deposited. Moreover, in order to ensure the film quality, it is necessary to frequently replace the plating solution, which increases the cost. Further, after the retention baking, as shown in FIG. 41, an alloy layer 50 of Au and Ni is formed between the Au film 153a and the Ni film 49b, so that the solder cannot enter the lower portion, and this is applied. The solder bump electrode 55 is easily peeled off at the interface. Thus, the shear strength of the solder bump electrode 55 is deteriorated.

  On the other hand, according to the present embodiment, as described above, the shear strength of the solder bump electrode 55 can be improved.

  As shown in FIG. 38, the plating process does not need to be performed in two stages, and may be formed in three or more processes (graph (b)). In this case, in the continuous treatment (graph (a)), even a film having a film thickness that cannot be formed because the reaction is rate-limiting.

  FIG. 34 is an overall plan view of the semiconductor wafer (semiconductor substrate) 1 in which the formation of the bump electrodes 55 has been completed. Thereafter, the wafer 1 is diced and divided into a plurality of chips CA (FIG. 35). The first pad portion (PAD1) arranged around the chip CA is connected to the bump electrode 55 by rewiring (not shown).

  FIG. 36 is a cross-sectional view showing a state where the chip CA is mounted on the mounting substrate 60. For example, the chip CA is face-down bonded on the mounting substrate 60, the bump electrode 55 is heated and reflowed, and then the underfill resin 62 is filled in the gap between the chip CA and the mounting substrate 60 to complete the CSP.

  In the present embodiment, the repair of the Au film 53a that has deteriorated due to the retention bake has been described as an example. However, the present embodiment can also be applied to repair of the Au film 53a that has been damaged by a probe needle or the like and whose surface condition has deteriorated. is there.

(Embodiment 2)
In the first embodiment, the third layer wiring M3 is formed using an Al alloy film, but may be formed using a Cu film. Note that layers below the third-layer wiring M3, for example, the silicon oxide film 35 and plugs therein can be formed in the same manner as in the first embodiment, and thus description thereof is omitted.

  First, as shown in FIG. 42, a silicon nitride film 237 and a silicon oxide film 239 are sequentially deposited as insulating films on the silicon oxide film 35 by using, for example, a CVD method.

  Next, the wiring trench MG is formed by dry etching the silicon nitride film 237 and the silicon oxide film 239. Note that the silicon nitride film 237 serves as an etching stopper.

  Next, after depositing a tantalum nitride (TaN) film as a barrier film on the silicon oxide film 239 including the inside of the wiring trench MG by, for example, a sputtering method, a Cu film as a conductive film is deposited on the TaN film. Or it forms by CVD method.

  Next, the third layer wiring 2M3 is formed by removing the TaN film and the Cu film outside the wiring trench MG by the CMP method. At this time, the surface of the Cu film or the like is retreated from the surface of the silicon oxide film 239 by overpolishing.

  Next, a TiN film 2M3c is formed on the silicon oxide film 239 and the third layer wiring 2M3 by, for example, a CVD method, and the TiN film 2M3c on the silicon oxide film 239 is removed. As a result, the surface of the third layer wiring 2M3 is covered with the TiN film 2M3c.

  Next, a silicon nitride film 241 and a silicon oxide film 243 are sequentially deposited as insulating films on the silicon oxide film 239 and the third-layer wiring 2M3 (TiN film 2M3c), for example, by using the CVD method. A passivation film made of a laminated film is formed.

  Next, the first pad portion PAD1 is opened by removing the silicon nitride film 241 and the silicon oxide film 243 on the third layer wiring 2M3 (TiN film 2M3c) by etching. Thereafter, similar to the first embodiment, rewiring and bump electrodes are formed.

  Thus, according to the present embodiment, since the TiN film 2M3c is formed on the surface of the third layer wiring 2M3, the acid cleaning is performed even if the third layer wiring 2M3 (TiN film M3c) in the scribe region SA is exposed. The effects described in detail in the first embodiment can be obtained, such as preventing the underlying Cu film from being corroded by treatment such as plating.

  Further, after opening the first pad portion PAD1, the TiN film 244 may be formed in the opening.

  That is, as shown in FIG. 43, a passivation film made of a laminated film of a silicon nitride film 241 and a silicon oxide film 243 is formed as an insulating film on the silicon oxide film 239 and the third layer wiring 2M3, and these films are etched. By removing the first pad portion PAD1, the first pad portion PAD1 is opened.

  Next, a TiN film 244 is deposited on the silicon oxide film 243 including the inside of the opening by, for example, a CVD method, and thereafter, the TiN film 244 on the silicon oxide film 243 is removed by a CMP method, whereby the sidewall and bottom of the opening are formed. The TiN film 244 is left on the (first pad portion PAD1). Thereafter, similar to the first embodiment, rewiring and bump electrodes are formed.

  In this case as well, even if the third layer wiring 2M3 in the scribe region SA is exposed, the TiN film 244 is formed on the upper part, so that the underlying Cu film is corroded by treatment such as acid cleaning or plating. The effects described in detail in Embodiment 1 can be obtained.

  In addition, since the Cu film forms an altered layer by contact with the polyimide resin film, the TiN film (2M3c, 244) can prevent the altered layer from being formed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In particular, in the above-described embodiment, the NOR type nonvolatile memory has been described as an example. However, the present invention can be widely applied to semiconductor integrated circuit devices in addition to AND type, NAND type and the like.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor integrated circuit devices.

It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is a principal part top view of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is a principal part top view of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is a principal part top view of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is a principal part top view of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the semiconductor integrated circuit device for demonstrating the effect of Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the semiconductor integrated circuit device for demonstrating the effect of Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is the whole semiconductor wafer top view after the formation process of the bump electrode of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is a top view of the chip | tip after the formation process of the bump electrode of the semiconductor integrated circuit device which is Embodiment 1 of this invention. 1 is a cross-sectional view showing a state where a semiconductor integrated circuit device (chip) according to a first embodiment of the present invention is mounted on a mounting substrate. It is a figure which shows the relationship between plating time and the film thickness of Au. It is a figure which shows the relationship between plating time and the film thickness of Au. It is a figure which shows the relationship between heat processing temperature [degreeC] and the oxide film thickness [nm] of Ni. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device for demonstrating the effect of Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device for demonstrating the effect of Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 2 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor integrated circuit device which is Embodiment 2 of this invention.

Explanation of symbols

1 Semiconductor wafer (semiconductor substrate)
4 element isolation 6 silicon oxide film 8 p-type well 11 gate insulating film 13a polycrystalline silicon pattern 15 ONO film 17 polycrystalline silicon film 19 silicon nitride film 21 n ⁻ type semiconductor region 22 n ⁺ type semiconductor region 23 sidewall spacer 25 n ⁺ Type semiconductor region 31 silicon oxide film 33 silicon oxide film 35 silicon oxide film 41 passivation film 43 polyimide resin film 45 seed layer 47 long groove 49 rewiring 49a Cu film 49b Ni film 50 alloy layer 51 polyimide resin film 53 base film 53a Au film 53b Au film 55 Bump electrode (solder bump electrode)
60 mounting substrate 62 underfill resin 153a Au film 237 silicon nitride film 239 silicon oxide film 241 silicon nitride film 243 silicon oxide film 244 TiN film 2M3 third layer wiring 2M3c TiN film C1 contact hole C2 contact hole C3 contact hole CG control electrode FG Floating electrode G Gate electrode CA Chip area (chip)
M1 first layer wiring M2 second layer wiring M3 third layer wiring M3a TiN film M3b Al alloy film M3c TiN film CSL common source line MBL main bit line MG wiring groove ML conductive layer N probe needle OA1 opening OA2 opening Or Organic contamination layer Ox oxide film P1 plug P2 plug P3 plug PAD1 first pad part PAD2 second pad part R resist film SA scribe area SBL sub-bit line

Claims (22)

(A) A first wiring formed in a chip region of a semiconductor wafer and a test pattern formed in a scribe region of the semiconductor wafer, which includes a first conductive film and a second conductive film thereabove. A first wiring and a test pattern;
(B) a second wiring that connects a first pad region that is part of the first wiring and a second pad region located in the chip region;
(C) a plating film formed on the second pad region on the second wiring;
Have
(D) The semiconductor integrated circuit device, wherein the second wiring and the plating film are not formed on the test pattern. (A) a first wiring having a first conductive film and a second conductive film thereon;
(B) an insulating film having an opening in a first pad region which is a part of the first wiring;
(C) a second wiring having a third conductive film formed on the insulating film including the inside of the opening and a fourth conductive film formed on the third conductive film, wherein the first wiring A second wiring connecting the pad region and a second pad region which is a part of the second wiring;
(D) a bump electrode formed on the second pad region;
A semiconductor integrated circuit device comprising:   3. The semiconductor integrated circuit device according to claim 2, wherein the first conductive film is mainly composed of Al (aluminum) or Cu (copper).   The second conductive film is a TiN (titanium nitride) film, a Ta (tantalum) film, a TaN (tantalum nitride) film, a W (tungsten) film or a single layer film of a WN (tungsten nitride) film, or of these films. 3. The semiconductor integrated circuit device according to claim 2, comprising a laminated film.   3. The semiconductor integrated circuit device according to claim 2, wherein the third conductive film is a Cr (chromium) film or a laminated film having a Cr film.   3. The semiconductor integrated circuit device according to claim 2, wherein the fourth conductive film is a laminated film of a Cu (copper) film and a Ni (nickel) film.   7. The bump electrode is an Au (gold) film formed on the Ni (nickel) film, and is made of solder formed on an Au film formed by a plating method. Semiconductor integrated circuit device. (A) forming a first wiring electrically connected to the semiconductor element formed on the semiconductor wafer;
(B) forming a first conductive film on a pad region which is a part of the first wiring;
(C) after the step (b), a step of heat-treating the semiconductor wafer;
(D) after the step (c), inspecting the characteristics of the semiconductor element using the pad region;
(E) after the step (d), further forming a second conductive film on the first conductive film;
(F) forming a bump electrode on the second conductive film;
A method for manufacturing a semiconductor integrated circuit device, comprising: The step (b) is a step of forming a first Au (gold) film on the pad region by plating.
9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein the step (e) is a step of forming a second Au film on the first Au film by a plating method.   10. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein the plating method is a displacement plating method. The method for manufacturing the semiconductor integrated circuit device further includes:
9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, further comprising a step of cleaning the surface of the first conductive film before the step (e).   9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein the semiconductor element is a nonvolatile memory.   The semiconductor element in the step (a) is a nonvolatile memory, and the step (d) is a step of inspecting retention characteristics of information stored in a floating electrode of the nonvolatile memory. 9. A method for manufacturing a semiconductor integrated circuit device according to 8. (A) forming a wiring electrically connected to a nonvolatile memory formed on a semiconductor substrate in a wafer state;
(B) forming a polyimide film having an opening in a pad region of the wiring on the wiring;
(C) After the step (b), in the wafer state, applying a heat load for a certain time to the semiconductor substrate, and using the pad region to inspect the information retention characteristics of the nonvolatile memory;
A method for manufacturing a semiconductor integrated circuit device, comprising: The method for manufacturing the semiconductor integrated circuit device includes:
(D) before and after the step (c), a step of forming an Au (gold) film on the pad region by a plating method;
15. The method of manufacturing a semiconductor integrated circuit device according to claim 14, further comprising:   16. The method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the plating method is a displacement plating method. The method for manufacturing the semiconductor integrated circuit device includes:
(D) before and after the step (c), a step of forming an Au (gold) film on the pad region by a plating method;
(E) forming a solder bump electrode on the Au film in the pad region;
15. The method of manufacturing a semiconductor integrated circuit device according to claim 14, further comprising: The method for manufacturing the semiconductor integrated circuit device further includes:
18. The method of manufacturing a semiconductor integrated circuit device according to claim 17, further comprising a step of cleaning a surface of the Au (gold) film formed on the pad region after the step (d). (A) forming a wiring electrically connected to a nonvolatile memory formed on a semiconductor substrate in a wafer state;
(B) forming a polyimide film having an opening in a pad region of the wiring on the wiring;
(C) After the step (b), in the wafer state, applying a heat load for a certain time to the semiconductor substrate, and using the pad region to inspect the information retention characteristics of the nonvolatile memory;
(D) after the step (c), forming a plating film on the pad region;
A method for manufacturing a semiconductor integrated circuit device, comprising:   20. The method of manufacturing a semiconductor integrated circuit device according to claim 19, wherein the plating film is an Au (gold) film. The method for manufacturing the semiconductor integrated circuit device includes:
(E) a step of forming an Au (gold) film on the pad region by a displacement plating method before the step (c);
20. The method of manufacturing a semiconductor integrated circuit device according to claim 19, further comprising: The method for manufacturing the semiconductor integrated circuit device includes:
(F) forming a solder bump electrode on the Au (gold) film;
21. The method of manufacturing a semiconductor integrated circuit device according to claim 20, further comprising:

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